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Mon, 15 May 2023 22:39:49 -0700 Received: from alan-new-dev.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Tue, 16 May 2023 00:39:48 -0500 From: Alan Liu To: Subject: [PATCH 1/7] drm/amd/display: Add new blob properties for secure display ROI Date: Tue, 16 May 2023 13:39:25 +0800 Message-ID: <20230516053931.1700117-2-HaoPing.Liu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516053931.1700117-1-HaoPing.Liu@amd.com> References: <20230516053931.1700117-1-HaoPing.Liu@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT069:EE_|SJ0PR12MB6942:EE_ X-MS-Office365-Filtering-Correlation-Id: 18f58f7e-98d7-4ba5-b3f1-08db55cff7bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3V169W75oL8rst5saIPF7YtRucu0AET5Dm2c9C1tTuw6flgxMWGBkguFn2XViznAztWFjGaXa8McGoNiIGkrUCbizyAki8DqIUSeUHl+oPzX6qOTcTC5UU+1BIR4Lp0jc6/Vi9aGl93gCd/Z+1l3gmsUVnPGLmJUMv98IJm+F1Rj0jtTn8g6R8zasBOltBSiI2RlLmrzIi29Ot+93G3gfODAnxeK1UcaK/bddynkKvuoS/T4M76tsivbGPKsNW7hV8Mk4IXPe8dSFtmDWb/9kr+mDGf0k1jHb/xNFsFCzIixhg8GabXvO94tGHIqAKyJlOXpcWO9wEhpxqO08EalqW4+G5Cy9r/xskP5+asNeOxSGRO9cLV9QvXZOzTGsUWpkbxblMjpM6YCbEomfR8cNJFPtwP+9z/E/v/C03ntAS+MRtxJU6ldypTFbdR7fBmlmEBWpVpZZ2F3gKgQh4H6iDL1GT3fThS8ebRP48jfW58V1jO92g1q8mfesSdBP1YFNBejuK9NO7UpyuLbLh8I3FfjVFksEaWfFdAGq9Yc502PD5rZO9oAcvDa6PLIS3yvtIfPHB/9gJkLXedvdJaO9ATZWoqRINm1Dt8t9hrNHzPgPOpm1iJz3fuaYnyCqkOQ763313exyZ3Yg7C1SjiriMGwhWfuAR5s38Ke/SOb7BQdfUhrvRI09FJ+HdB+YOlp1cqa6pqeAtC4Z4YvDMHiKtE7cUbRwezkvpFkCs4CXGIKyQ6aoVDlFHQ/pxDI824jRtQSV2j22QhmQhjyU/tgEw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(396003)(376002)(136003)(39860400002)(346002)(451199021)(46966006)(40470700004)(36840700001)(36860700001)(81166007)(83380400001)(478600001)(316002)(26005)(1076003)(356005)(47076005)(70206006)(41300700001)(70586007)(426003)(336012)(6916009)(4326008)(82740400003)(54906003)(2616005)(7696005)(8676002)(8936002)(86362001)(6666004)(82310400005)(36756003)(186003)(2906002)(40460700003)(5660300002)(40480700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 05:39:50.5206 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18f58f7e-98d7-4ba5-b3f1-08db55cff7bc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6942 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , wayne.lin@amd.com, lili.gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a new blob properties as well as the create and attach functions for configuring region of interested (ROI) of secure display. Signed-off-by: Alan Liu --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 ++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 4 +++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 5 +++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 31 +++++++++++++++++++ include/uapi/drm/drm_mode.h | 20 ++++++++++++ 5 files changed, 70 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 2e2413fd73a4..ee57c659f230 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -500,6 +500,9 @@ struct amdgpu_display_manager { * all crtcs. */ struct secure_display_context *secure_display_ctxs; + + /* properties for secure_display ROI configuration */ + struct drm_property *secure_display_roi_property; #endif /** * @hpd_rx_offload_wq: @@ -726,6 +729,13 @@ struct dm_crtc_state { struct dc_info_packet vrr_infopacket; int abm_level; + +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + struct { + struct drm_property_blob *roi_blob; + bool roi_changed : 1; + } secure_display_state; +#endif }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 0802f8e8fac5..e7259ec1d644 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -546,10 +546,14 @@ amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) if (!secure_display_ctxs) return NULL; + if (amdgpu_dm_crtc_create_secure_display_properties(adev)) + DRM_ERROR("amdgpu: failed to create secure display properties.\n"); + for (i = 0; i < adev->mode_info.num_crtc; i++) { INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window); INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base; + amdgpu_dm_crtc_attach_secure_display_properties(adev, &adev->mode_info.crtcs[i]->base); } return secure_display_ctxs; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 748e80ef40d0..66f29e3de9f9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -97,10 +97,15 @@ bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc); void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc); struct secure_display_context *amdgpu_dm_crtc_secure_display_create_contexts( struct amdgpu_device *adev); +int amdgpu_dm_crtc_create_secure_display_properties(struct amdgpu_device *adev); +void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev, + struct drm_crtc *crtc); #else #define amdgpu_dm_crc_window_is_activated(x) #define amdgpu_dm_crtc_handle_crc_window_irq(x) #define amdgpu_dm_crtc_secure_display_create_contexts(x) +#define amdgpu_dm_crtc_create_secure_display_properties(x) +#define amdgpu_dm_crtc_attach_secure_display_properties(x) #endif #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index e3762e806617..4af7ea6fbd65 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -265,6 +265,10 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc) state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; state->crc_skip_count = cur->crc_skip_count; state->mpo_requested = cur->mpo_requested; + +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + state->secure_display_state = cur->secure_display_state; +#endif /* TODO Duplicate dc_stream after objects are stream object is flattened */ return &state->base; @@ -290,6 +294,33 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc) __drm_atomic_helper_crtc_reset(crtc, &state->base); } +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +int amdgpu_dm_crtc_create_secure_display_properties(struct amdgpu_device *adev) +{ + struct amdgpu_display_manager *dm = &adev->dm; + struct drm_device *dev = adev_to_drm(adev); + struct drm_property *roi_prop; + + roi_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "SECURE_DISPLAY_ROI", 0); + if (!roi_prop) + return -ENOMEM; + + dm->secure_display_roi_property = roi_prop; + + return 0; +} + +void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev, + struct drm_crtc *crtc) +{ + struct amdgpu_display_manager *dm = &adev->dm; + + if (dm->secure_display_roi_property) + drm_object_attach_property(&crtc->base, dm->secure_display_roi_property, 0); +} +#endif + #ifdef CONFIG_DEBUG_FS static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) { diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 46becedf5b2f..98e0a0aaa1c3 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1303,6 +1303,26 @@ struct drm_mode_rect { __s32 y2; }; +/** + * struct drm_roi - The enablement and region of interest (ROI) of secure display + * @x_start: Horizontal starting coordinate of ROI. + * @y_start: Vertical starting coordinate of ROI. + * @x_end: Horizontal ending coordinate of ROI. + * @y_end: Vertical ending coordinate of ROI. + * @secure_display_enable: To enable or disable secure display. + * + * Userspace uses this structure to configure the region of interest and + * enablement for secure display. + */ +struct drm_roi { + __u32 x_start; + __u32 y_start; + __u32 x_end; + __u32 y_end; + __u8 secure_display_enable; + __u8 pad[7]; +}; + #if defined(__cplusplus) } #endif From patchwork Tue May 16 05:39:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, HaoPing (Alan)" X-Patchwork-Id: 13242550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14D08C77B75 for ; Tue, 16 May 2023 05:40:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0913310E2DC; Tue, 16 May 2023 05:39:58 +0000 (UTC) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2086.outbound.protection.outlook.com [40.107.94.86]) by gabe.freedesktop.org (Postfix) with ESMTPS id 515D310E2DC for ; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(346002)(39860400002)(136003)(396003)(376002)(451199021)(46966006)(36840700001)(40470700004)(86362001)(186003)(36860700001)(26005)(1076003)(6666004)(2616005)(47076005)(83380400001)(7696005)(82310400005)(336012)(426003)(8936002)(8676002)(478600001)(36756003)(2906002)(40460700003)(54906003)(5660300002)(81166007)(82740400003)(356005)(4326008)(41300700001)(6916009)(70206006)(70586007)(316002)(40480700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 05:39:52.5832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40ba0eed-5ce2-4502-5ab0-08db55cff903 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8261 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , wayne.lin@amd.com, lili.gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement set/get functions as the callback for userspace to update or get the secure display ROI configuration. Signed-off-by: Alan Liu --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 4af7ea6fbd65..e1a17f2d6f2d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -319,6 +319,53 @@ void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev, if (dm->secure_display_roi_property) drm_object_attach_property(&crtc->base, dm->secure_display_roi_property, 0); } + +static int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state, + struct drm_property *property, + uint64_t val) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct dm_crtc_state *dm_state = to_dm_crtc_state(crtc_state); + + if (property == adev->dm.secure_display_roi_property) { + struct drm_property_blob *new_blob, **old_blob; + + old_blob = &dm_state->secure_display_state.roi_blob; + + if (val != 0) { + new_blob = drm_property_lookup_blob(dev, val); + if (!new_blob) + return -EINVAL; + } + dm_state->secure_display_state.roi_changed |= + drm_property_replace_blob(old_blob, new_blob); + + } else + return -EINVAL; + + return 0; +} + +static int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc, + const struct drm_crtc_state *crtc_state, + struct drm_property *property, + uint64_t *val) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct dm_crtc_state *dm_state = to_dm_crtc_state(crtc_state); + + if (property == adev->dm.secure_display_roi_property) + *val = (dm_state->secure_display_state.roi_blob) + ? dm_state->secure_display_state.roi_blob->base.id : 0; + + else + return -EINVAL; + + return 0; +} #endif #ifdef CONFIG_DEBUG_FS @@ -348,6 +395,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + .atomic_set_property = amdgpu_dm_crtc_atomic_set_property, + .atomic_get_property = amdgpu_dm_crtc_atomic_get_property, +#endif }; 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Signed-off-by: Alan Liu --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 +++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 1 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 10 ++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 23 ++++++++++++++++--- include/uapi/drm/drm_mode.h | 19 +++++++++++++++ 5 files changed, 53 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index ee57c659f230..74e42257a608 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -503,6 +503,9 @@ struct amdgpu_display_manager { /* properties for secure_display ROI configuration */ struct drm_property *secure_display_roi_property; + + /* properties for secure_display CRC information */ + struct drm_property *secure_display_crc_property; #endif /** * @hpd_rx_offload_wq: diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index e7259ec1d644..a83cabb9b1a6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -550,6 +550,7 @@ amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) DRM_ERROR("amdgpu: failed to create secure display properties.\n"); for (i = 0; i < adev->mode_info.num_crtc; i++) { + spin_lock_init(&secure_display_ctxs[i].crc.lock); INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window); INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 66f29e3de9f9..f2def8c20d83 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -40,6 +40,14 @@ enum amdgpu_dm_pipe_crc_source { }; #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +struct crc_data { + uint32_t crc_R; + uint32_t crc_G; + uint32_t crc_B; + uint32_t frame_count; + spinlock_t lock; +}; + struct crc_window_param { uint16_t x_start; uint16_t y_start; @@ -64,6 +72,8 @@ struct secure_display_context { /* Region of Interest (ROI) */ struct rect rect; + + struct crc_data crc; }; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index e1a17f2d6f2d..4457eac8273e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -299,16 +299,30 @@ int amdgpu_dm_crtc_create_secure_display_properties(struct amdgpu_device *adev) { struct amdgpu_display_manager *dm = &adev->dm; struct drm_device *dev = adev_to_drm(adev); - struct drm_property *roi_prop; + struct drm_property *roi_prop, *crc_prop; roi_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, "SECURE_DISPLAY_ROI", 0); - if (!roi_prop) - return -ENOMEM; + + crc_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "SECURE_DISPLAY_CRC", 0); + + if (!roi_prop || !crc_prop) + goto fail; dm->secure_display_roi_property = roi_prop; + dm->secure_display_crc_property = crc_prop; return 0; + +fail: + if (roi_prop) + drm_property_destroy(dev, roi_prop); + + if (crc_prop) + drm_property_destroy(dev, roi_prop); + + return -ENOMEM; } void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev, @@ -318,6 +332,9 @@ void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev, if (dm->secure_display_roi_property) drm_object_attach_property(&crtc->base, dm->secure_display_roi_property, 0); + + if (dm->secure_display_crc_property) + drm_object_attach_property(&crtc->base, dm->secure_display_crc_property, 0); } static int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc, diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 98e0a0aaa1c3..8c488ce59e7a 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1323,6 +1323,25 @@ struct drm_roi { __u8 pad[7]; }; +/** + * struct drm_crc - The CRC value of the corresponding ROI of secure display. + * @crc_r: CRC value of red color. + * @crc_g: CRC value of green color. + * @crc_b: CRC value of blue color. + * @frame_count: a referenced frame count to indicate which frame the CRC values + * are generated at. + * + * Userspace uses this structure to retrieve the CRC value of the current ROI of + * secure display. @frame_count will be reset once a new ROI is updated or it reaches + * its maximum value. + */ +struct drm_crc { + __u32 crc_r; + __u32 crc_g; + __u32 crc_b; + __u32 frame_count; +}; + #if defined(__cplusplus) } #endif From patchwork Tue May 16 05:39:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, HaoPing (Alan)" X-Patchwork-Id: 13242552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5056EC77B75 for ; Tue, 16 May 2023 05:40:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E442F10E2E0; Tue, 16 May 2023 05:40:02 +0000 (UTC) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id A72D810E2D6 for ; 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Signed-off-by: Alan Liu --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 38 ++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 74e42257a608..b389b1d1c370 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -736,6 +736,7 @@ struct dm_crtc_state { #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY struct { struct drm_property_blob *roi_blob; + struct drm_property_blob *crc_blob; bool roi_changed : 1; } secure_display_state; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 4457eac8273e..0e9834e0506d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -359,6 +359,10 @@ static int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc, dm_state->secure_display_state.roi_changed |= drm_property_replace_blob(old_blob, new_blob); + } else if (property == adev->dm.secure_display_crc_property) { + /* don't let user set CRC data */ + return -EPERM; + } else return -EINVAL; @@ -373,12 +377,44 @@ static int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = drm_to_adev(dev); struct dm_crtc_state *dm_state = to_dm_crtc_state(crtc_state); + struct secure_display_context *secure_display_ctx = + &adev->dm.secure_display_ctxs[crtc->index]; if (property == adev->dm.secure_display_roi_property) *val = (dm_state->secure_display_state.roi_blob) ? dm_state->secure_display_state.roi_blob->base.id : 0; - else + else if (property == adev->dm.secure_display_crc_property) { + struct drm_crc *blob_data; + struct drm_property_blob *blob; + unsigned long flag; + + if (!amdgpu_dm_crc_window_is_activated(crtc)) { + *val = 0; + return 0; + } + + /* save new value to blob */ + blob = drm_property_create_blob(dev, + sizeof(struct drm_crc), + NULL); + if (IS_ERR(blob)) { + *val = 0; + return -ENOMEM; + } + + blob_data = (struct drm_crc *) blob->data; + spin_lock_irqsave(&secure_display_ctx->crc.lock, flag); + blob_data->crc_r = secure_display_ctx->crc.crc_R; + blob_data->crc_g = secure_display_ctx->crc.crc_G; + blob_data->crc_b = secure_display_ctx->crc.crc_B; + blob_data->frame_count = secure_display_ctx->crc.frame_count; + spin_unlock_irqrestore(&secure_display_ctx->crc.lock, flag); + + drm_property_replace_blob(&dm_state->secure_display_state.crc_blob, blob); + *val = blob->base.id; + + } else return -EINVAL; return 0; From patchwork Tue May 16 05:39:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, HaoPing (Alan)" X-Patchwork-Id: 13242554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DE7BC77B75 for ; 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Tue, 16 May 2023 00:40:29 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 16 May 2023 00:39:56 -0500 Received: from alan-new-dev.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Tue, 16 May 2023 00:39:55 -0500 From: Alan Liu To: Subject: [PATCH 5/7] drm/amd/display: Processing secure display new ROI update in atomic commit Date: Tue, 16 May 2023 13:39:29 +0800 Message-ID: <20230516053931.1700117-6-HaoPing.Liu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516053931.1700117-1-HaoPing.Liu@amd.com> References: <20230516053931.1700117-1-HaoPing.Liu@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT053:EE_|CH2PR12MB5020:EE_ X-MS-Office365-Filtering-Correlation-Id: 5eab4699-1d7e-41b0-9e32-08db55d00f7f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 05:40:30.3700 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5eab4699-1d7e-41b0-9e32-08db55d00f7f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5020 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , wayne.lin@amd.com, lili.gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Check if there is a new ROI update during the atomic commit and process it. A new function amdgpu_dm_crtc_set_secure_display_crc_source() is implemented to control the state of CRC engine in hardware. Signed-off-by: Alan Liu --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 38 +++++++++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 57 +++++++++++++++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 + 3 files changed, 98 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 14b296e1d0f6..ee016d5be7ac 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8857,6 +8857,44 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } } #endif + +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + if (new_crtc_state->active && dm_new_crtc_state->secure_display_state.roi_changed) { + struct drm_roi *roi_data = + (struct drm_roi *)dm_new_crtc_state->secure_display_state.roi_blob->data; + + if (roi_data->secure_display_enable) { + if (!amdgpu_dm_crc_window_is_activated(crtc)) { + /* Enable secure display: set crc source to "crtc" */ + amdgpu_dm_crtc_set_secure_display_crc_source(crtc, "crtc"); + + /* wait 1 more frame for CRC engine to start */ + acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; + + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + acrtc->dm_irq_params.window_param.activated = true; + spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); + } + + /* Update ROI: copy ROI from dm_crtc_state to dm_irq_params */ + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + acrtc->dm_irq_params.window_param.x_start = roi_data->x_start; + acrtc->dm_irq_params.window_param.y_start = roi_data->y_start; + acrtc->dm_irq_params.window_param.x_end = roi_data->x_end; + acrtc->dm_irq_params.window_param.y_end = roi_data->y_end; + acrtc->dm_irq_params.window_param.update_win = true; + spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); + + } else { + if (amdgpu_dm_crc_window_is_activated(crtc)) { + /* Disable secure display: set crc source to "none" */ + amdgpu_dm_crtc_set_secure_display_crc_source(crtc, "none"); + } + } + + dm_new_crtc_state->secure_display_state.roi_changed = false; + } +#endif } for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index a83cabb9b1a6..81e9995183ad 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -465,6 +465,63 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) } #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +int amdgpu_dm_crtc_set_secure_display_crc_source(struct drm_crtc *crtc, const char *src_name) +{ + enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); + enum amdgpu_dm_pipe_crc_source cur_crc_src; + struct dm_crtc_state *crtc_state; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + bool enable = false; + bool enabled = false; + int ret = 0; + unsigned long flag; + + if (source < 0) { + DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", + src_name, crtc->index); + return -EINVAL; + } + + enable = amdgpu_dm_is_valid_crc_source(source); + crtc_state = to_dm_crtc_state(crtc->state); + spin_lock_irqsave(&drm_dev->event_lock, flag); + cur_crc_src = acrtc->dm_irq_params.crc_src; + spin_unlock_irqrestore(&drm_dev->event_lock, flag); + + /* Reset secure_display when we change crc source */ + amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream); + + if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { + ret = -EINVAL; + goto cleanup; + } + + /* + * Reading the CRC requires the vblank interrupt handler to be + * enabled. Keep a reference until CRC capture stops. + */ + enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); + if (!enabled && enable) { + ret = drm_crtc_vblank_get(crtc); + if (ret) + goto cleanup; + + } else if (enabled && !enable) { + drm_crtc_vblank_put(crtc); + } + + spin_lock_irqsave(&drm_dev->event_lock, flag); + acrtc->dm_irq_params.crc_src = source; + spin_unlock_irqrestore(&drm_dev->event_lock, flag); + + /* Reset crc_skipped on dm state */ + crtc_state->crc_skip_count = 0; + +cleanup: + return ret; +} + void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) { struct drm_device *drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index f2def8c20d83..1b85d60488b6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -110,12 +110,15 @@ struct secure_display_context *amdgpu_dm_crtc_secure_display_create_contexts( int amdgpu_dm_crtc_create_secure_display_properties(struct amdgpu_device *adev); void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev, struct drm_crtc *crtc); +int amdgpu_dm_crtc_set_secure_display_crc_source(struct drm_crtc *crtc, + const char *src_name); #else #define amdgpu_dm_crc_window_is_activated(x) #define amdgpu_dm_crtc_handle_crc_window_irq(x) #define amdgpu_dm_crtc_secure_display_create_contexts(x) #define amdgpu_dm_crtc_create_secure_display_properties(x) #define amdgpu_dm_crtc_attach_secure_display_properties(x) +#define amdgpu_dm_crtc_set_secure_display_crc_source(x) #endif #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */ From patchwork Tue May 16 05:39:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, HaoPing (Alan)" X-Patchwork-Id: 13242555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 573D6C77B7A for ; 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Tue, 16 May 2023 00:40:30 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 16 May 2023 00:39:58 -0500 Received: from alan-new-dev.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Tue, 16 May 2023 00:39:57 -0500 From: Alan Liu To: Subject: [PATCH 6/7] drm/amd/display: Implement the retrieval of secure display CRC data Date: Tue, 16 May 2023 13:39:30 +0800 Message-ID: <20230516053931.1700117-7-HaoPing.Liu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516053931.1700117-1-HaoPing.Liu@amd.com> References: <20230516053931.1700117-1-HaoPing.Liu@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT053:EE_|SA3PR12MB7976:EE_ X-MS-Office365-Filtering-Correlation-Id: 762f8b4d-63cc-4d94-77b9-08db55d010a2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 05:40:32.2136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 762f8b4d-63cc-4d94-77b9-08db55d010a2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7976 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , wayne.lin@amd.com, lili.gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Retrieve secure display's CRC data from the DC hardware in vline0 irq handler, and store the values in secure display contexts. Signed-off-by: Alan Liu --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 50 ++++++++++++++++--- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 81e9995183ad..f0ccf29af4f8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -529,6 +529,8 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) struct amdgpu_crtc *acrtc = NULL; struct amdgpu_device *adev = NULL; struct secure_display_context *secure_display_ctx = NULL; + bool reset_crc_frame_count = false, crc_is_updated = false; + uint32_t crc[3] = {0}; unsigned long flags1; if (crtc == NULL) @@ -543,15 +545,14 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) /* Early return if CRC capture is not enabled. */ if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) || - !dm_is_crc_source_crtc(cur_crc_src)) - goto cleanup; - - if (!acrtc->dm_irq_params.window_param.activated) - goto cleanup; + !dm_is_crc_source_crtc(cur_crc_src)) { + spin_unlock_irqrestore(&drm_dev->event_lock, flags1); + return; + } - if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { - acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; - goto cleanup; + if (!acrtc->dm_irq_params.window_param.activated) { + spin_unlock_irqrestore(&drm_dev->event_lock, flags1); + return; } secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id]; @@ -562,6 +563,11 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) secure_display_ctx->crtc = crtc; } + if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { + acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; + goto cleanup; + } + if (acrtc->dm_irq_params.window_param.update_win) { /* prepare work for dmub to update ROI */ secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start; @@ -572,6 +578,8 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) acrtc->dm_irq_params.window_param.y_start; schedule_work(&secure_display_ctx->forward_roi_work); + reset_crc_frame_count = true; + acrtc->dm_irq_params.window_param.update_win = false; /* Statically skip 1 frame, because we may need to wait below things @@ -582,12 +590,38 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; } else { + struct dc_stream_state *stream_state = to_dm_crtc_state(crtc->state)->stream; + + if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, + &crc[0], &crc[1], &crc[2])) + DRM_ERROR("Secure Display: fail to get crc\n"); + else + crc_is_updated = true; + /* prepare work for psp to read ROI/CRC and send to I2C */ schedule_work(&secure_display_ctx->notify_ta_work); } cleanup: spin_unlock_irqrestore(&drm_dev->event_lock, flags1); + + spin_lock_irqsave(&secure_display_ctx->crc.lock, flags1); + + if (reset_crc_frame_count || secure_display_ctx->crc.frame_count == UINT_MAX) + /* Reset the reference frame count after user update the ROI + * or it reaches the maximum value. + */ + secure_display_ctx->crc.frame_count = 0; + else + secure_display_ctx->crc.frame_count += 1; + + if (crc_is_updated) { + secure_display_ctx->crc.crc_R = crc[0]; + secure_display_ctx->crc.crc_G = crc[1]; + secure_display_ctx->crc.crc_B = crc[2]; + } + + spin_unlock_irqrestore(&secure_display_ctx->crc.lock, flags1); } struct secure_display_context * From patchwork Tue May 16 05:39:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, HaoPing (Alan)" X-Patchwork-Id: 13242553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0059AC77B7A for ; Tue, 16 May 2023 05:40:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 80FD210E2DE; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 05:40:01.2154 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20affe10-866a-4eb7-83fc-08db55cffe28 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8643 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , wayne.lin@amd.com, lili.gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" When the user requests for secure display ROI or CRC data, the request will be blocked until the CRC result of current frame is calculated and updated to secure display ctx in vline0 irq handler. Signed-off-by: Alan Liu --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++++++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 4 ++++ 4 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ee016d5be7ac..7b7ff9a5458a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8864,7 +8864,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) (struct drm_roi *)dm_new_crtc_state->secure_display_state.roi_blob->data; if (roi_data->secure_display_enable) { + struct secure_display_context *secure_display_ctx = + &dm->secure_display_ctxs[acrtc->crtc_id]; + if (!amdgpu_dm_crc_window_is_activated(crtc)) { + init_completion(&secure_display_ctx->crc.completion); + /* Enable secure display: set crc source to "crtc" */ amdgpu_dm_crtc_set_secure_display_crc_source(crtc, "crtc"); @@ -8874,7 +8879,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); acrtc->dm_irq_params.window_param.activated = true; spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); - } + } else + reinit_completion(&secure_display_ctx->crc.completion); /* Update ROI: copy ROI from dm_crtc_state to dm_irq_params */ spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index f0ccf29af4f8..85cedd207c8d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -619,6 +619,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) secure_display_ctx->crc.crc_R = crc[0]; secure_display_ctx->crc.crc_G = crc[1]; secure_display_ctx->crc.crc_B = crc[2]; + complete_all(&secure_display_ctx->crc.completion); } spin_unlock_irqrestore(&secure_display_ctx->crc.lock, flags1); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 1b85d60488b6..64a0fd0f165f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -46,6 +46,7 @@ struct crc_data { uint32_t crc_B; uint32_t frame_count; spinlock_t lock; + struct completion completion; }; struct crc_window_param { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 0e9834e0506d..af1c4a62a482 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -380,6 +380,10 @@ static int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc, struct secure_display_context *secure_display_ctx = &adev->dm.secure_display_ctxs[crtc->index]; + if (amdgpu_dm_crc_window_is_activated(crtc)) + wait_for_completion_interruptible_timeout( + &secure_display_ctx->crc.completion, 10 * HZ); + if (property == adev->dm.secure_display_roi_property) *val = (dm_state->secure_display_state.roi_blob) ? dm_state->secure_display_state.roi_blob->base.id : 0;