From patchwork Wed May 17 22:30:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boerge Struempfel X-Patchwork-Id: 13245822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B56EC77B7A for ; Wed, 17 May 2023 22:30:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229595AbjEQWas (ORCPT ); Wed, 17 May 2023 18:30:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbjEQWar (ORCPT ); Wed, 17 May 2023 18:30:47 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 064C659FD; Wed, 17 May 2023 15:30:44 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-965fc25f009so235898466b.3; Wed, 17 May 2023 15:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684362642; x=1686954642; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=1xvZgYgSWGaYso+rMNPq2umuAV7PxMbwVAnAP9WIPXc=; b=OZ9CGRQV1SeQ2kcD8yaOaISaKguhXnwPewhpm95OxfALiQ+94wbvi7qyuoi0EhMcLy o+NI1Sn59jiDT886nlK4v7x1q4a77uIZi+ov/J2+TjnGYFqn1zrCxMLAcHkOu3zz7DUL s5ihngf9Q/WBNpaqAkzRljMTUJqM4tb1vRBIudf4y7C/HK6xsN8KnpZsa0rKVWC+XlZa tZCwzhQB26iGoLJtIjxyUY/XFp07GqQPFncDfZU00Yq+MMWrwT3w+C6w5BJV5GHDm4Sj NUgosoE5MoADYEa4yRUGEe8ayujrc8enXF/10AnEFZWFU7ChbRhI+O5YQ6RLcacAfzqE Wnnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684362642; x=1686954642; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1xvZgYgSWGaYso+rMNPq2umuAV7PxMbwVAnAP9WIPXc=; b=ftC1c/Fhx6P9Rs6d3kiDsFOtgOvFhT3wM/7wSZYLsfqQKW5ZekbHTSwNQt8aapyECl 5691XPHpvcqEX0VInzD3ehmvgSqizSa9fKPT41lCEe8qfER9KwIc6blbuHNE+42GeAIV W44NKYURnnVFJkJB4T5TPFUEhXET7JaPMNErm3II1si81Q5h+s4H2OFYHp44ijU4armX FTpqB5a+ckifK99GZzSrggRtawfFvQS2L/KQdSLDFxvyjQG5FbR0w9KKjwjE09nPbhMM u0muUzXCGJZdYLSpRvDGn8kPlK/oWHPwCUhV7w4QXTWN+YL9QxVOb3+3z2QJwZGmq5cA eLOw== X-Gm-Message-State: AC+VfDy/BhUodNcq/b2oUQv7MmzyYdRIVCEUDCwSO3NJWlyAUDO9Zo2w Fonjo36TCjX7BoGNlFAcv6w= X-Google-Smtp-Source: ACHHUZ6nai5aV4t2xJk7IyN+8Ad3ycGG5nCY8zPmux1AvlcXXVCpMuuuutAsIVKWGprRkefr8VzF4Q== X-Received: by 2002:a17:907:3e9c:b0:966:471c:2565 with SMTP id hs28-20020a1709073e9c00b00966471c2565mr37357809ejc.48.1684362642211; Wed, 17 May 2023 15:30:42 -0700 (PDT) Received: from wslxew193.fritz.box (p200300c78700c900633510ddc4028dcd.dip0.t-ipconnect.de. [2003:c7:8700:c900:6335:10dd:c402:8dcd]) by smtp.gmail.com with ESMTPSA id y14-20020a1709064b0e00b0095807ab4b57sm109327eju.178.2023.05.17.15.30.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 15:30:41 -0700 (PDT) From: Boerge Struempfel Cc: boerge.struempfel@gmail.com, bstruempfel@ultratronik.de, andy.shevchenko@gmail.com, festevam@gmail.com, amit.kumar-mahapatra@amd.com, broonie@kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] spi: add SPI_MOSI_IDLE_LOW mode bit Date: Thu, 18 May 2023 00:30:05 +0200 Message-Id: <20230517223007.178432-1-boerge.struempfel@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Some spi controller switch the mosi line to high, whenever they are idle. This may not be desired in all use cases. For example neopixel leds can get confused and flicker due to misinterpreting the idle state. Therefore, we introduce a new spi-mode bit, with which the idle behaviour can be overwritten on a per device basis. Signed-off-by: Boerge Struempfel Link for versions: v1 and v2: https://lore.kernel.org/linux-spi/20230511135632.78344-1-bstruempfel@ultratronik.de/ v3: https://lore.kernel.org/linux-spi/20230517103007.26287-1-boerge.struempfel@gmail.com/T/#t Changes from V3: - Added missing paranthesis which caused builderrors Changes from V2: - Removed the device-tree binding since this should not be managed by the DT but by the device itself. - Replaced all occurences of spi->chip_select with the corresponding macro spi_get_chipselect(spi,0) Changes from V1: - Added patch, introducing the new devicetree binding flag - Split the generic spi part of the patch from the imx-spi specific part - Replaced SPI_CPOL and SPI_CPHA by the combined SPI_MODE_X_MASK bit in the imx-spi.c modebits. - Added the SPI_MOSI_IDLE_LOW bit to spidev Signed-off-by: Your name --- include/uapi/linux/spi/spi.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/spi/spi.h b/include/uapi/linux/spi/spi.h index 9d5f58059703..ca56e477d161 100644 --- a/include/uapi/linux/spi/spi.h +++ b/include/uapi/linux/spi/spi.h @@ -28,6 +28,7 @@ #define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */ #define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */ #define SPI_RX_CPHA_FLIP _BITUL(16) /* flip CPHA on Rx only xfer */ +#define SPI_MOSI_IDLE_LOW _BITUL(17) /* leave mosi line low when idle */ /* * All the bits defined above should be covered by SPI_MODE_USER_MASK. @@ -37,6 +38,6 @@ * These bits must not overlap. A static assert check should make sure of that. * If adding extra bits, make sure to increase the bit index below as well. */ -#define SPI_MODE_USER_MASK (_BITUL(17) - 1) +#define SPI_MODE_USER_MASK (_BITUL(18) - 1) #endif /* _UAPI_SPI_H */ From patchwork Wed May 17 22:30:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boerge Struempfel X-Patchwork-Id: 13245823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A84EC7EE22 for ; Wed, 17 May 2023 22:30:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229456AbjEQWa5 (ORCPT ); Wed, 17 May 2023 18:30:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229522AbjEQWav (ORCPT ); Wed, 17 May 2023 18:30:51 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 612915B90; Wed, 17 May 2023 15:30:45 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-50bcb00a4c2so2051931a12.1; Wed, 17 May 2023 15:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684362644; x=1686954644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/FsOd9MgDJMeorWa734Iw1cUVj+gA3xOrUBWqtCM238=; b=WXWxpAqBqkNlEFcfyF2Ee70k3+pxEhMzzuphULcqCPUNbH3ndOPuPFndR6cpporZj9 iADBSwww9yeXUIPNa6sSE37RZOQca9iZLfXmLZ9YmXn5TCpEmbKBBwfPyG9tSHUDhlRR Y5zbSzo3BtraV4d2UA4VPfrTholfMSaso+P4Y/PhVT4P/ccvmn8GDg39cEe290YxK3FD by/bMBKqfGEkd3soVH38aiWeCYsT2tXW7XwB/2+zvHtnvoSE3hovkbow+OmSXRysIhEq mgbXTpOoVgvCat0mlnstOc6B29pvP1F50roIQ1NtF5BY0E2ruHiCor1uxrsSMILfE7Jy jUPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684362644; x=1686954644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/FsOd9MgDJMeorWa734Iw1cUVj+gA3xOrUBWqtCM238=; b=eTwzY5sPY4E579HLb/XSgtbDkfQzxypXm4+S5X6Ue3v11RCHdLmdxCylQm+bPhs1ue GP3rpBx/2rJpKeqEHhV4Qh82M0fXl6ykE2VBkHhURIkhfNFgZi2BaoHW6u07OStS+rmg AqREhXp8h+g27Znpc0P3ZhooWbjXe1VRZyHZsIpNWaT5H9OWKhwOXWLEMJjt+SRsGf4v vk4fsvojWXfUQdF+9Y3bC+3F5zBBGjk0TOJ5HJ5V6yvZ5yAvNkZH/cX120FYE904Y0O1 +xSCXXvOYrNhAKt8ELQJdVqJKKkk0bDamlRNU+xN28pwMa/cyEwE3lGItA5we5cQIzG5 8IoQ== X-Gm-Message-State: AC+VfDww0R0RDFdIIRAEJtWTY5kX/1lNCjedHcLHqlFBJ9BboqprOsnz TYW2V4GG6Sngx/5MFQLY/rM= X-Google-Smtp-Source: ACHHUZ46OihSG/weHkolyoeQYmK0Y48BG6k3h3k5KmA9VqqYe04BC1s8KpET4pkwKZ8MOQHjZv3nXA== X-Received: by 2002:a17:907:2d1f:b0:968:db2f:383 with SMTP id gs31-20020a1709072d1f00b00968db2f0383mr31445004ejc.53.1684362643725; Wed, 17 May 2023 15:30:43 -0700 (PDT) Received: from wslxew193.fritz.box (p200300c78700c900633510ddc4028dcd.dip0.t-ipconnect.de. [2003:c7:8700:c900:6335:10dd:c402:8dcd]) by smtp.gmail.com with ESMTPSA id y14-20020a1709064b0e00b0095807ab4b57sm109327eju.178.2023.05.17.15.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 15:30:43 -0700 (PDT) From: Boerge Struempfel Cc: boerge.struempfel@gmail.com, bstruempfel@ultratronik.de, andy.shevchenko@gmail.com, festevam@gmail.com, amit.kumar-mahapatra@amd.com, broonie@kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/3] spi: spi-imx: add support for SPI_MOSI_IDLE_LOW mode bit Date: Thu, 18 May 2023 00:30:06 +0200 Message-Id: <20230517223007.178432-2-boerge.struempfel@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230517223007.178432-1-boerge.struempfel@gmail.com> References: <20230517223007.178432-1-boerge.struempfel@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org By default, the spi-imx controller pulls the mosi line high, whenever it is idle. This behaviour can be inverted per CS by setting the corresponding DATA_CTL bit in the config register of the controller. Also, since the controller mode-bits have to be touched anyways, the SPI_CPOL and SPI_CPHA are replaced by the combined SPI_MODE_X_MASK flag. Signed-off-by: Boerge Struempfel --- drivers/spi/spi-imx.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 34e5f81ec431..1c4172fcba2d 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -281,6 +281,7 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4)) #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8)) #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12)) +#define MX51_ECSPI_CONFIG_DATACTL(cs) (1 << ((cs & 3) + 16)) #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20)) #define MX51_ECSPI_INT 0x10 @@ -573,6 +574,11 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi_get_chipselect(spi, 0)); } + if (spi->mode & SPI_MOSI_IDLE_LOW) + cfg |= MX51_ECSPI_CONFIG_DATACTL(spi_get_chipselect(spi, 0)); + else + cfg &= ~MX51_ECSPI_CONFIG_DATACTL(spi_get_chipselect(spi, 0)); + if (spi->mode & SPI_CS_HIGH) cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi_get_chipselect(spi, 0)); else @@ -1743,7 +1749,8 @@ static int spi_imx_probe(struct platform_device *pdev) spi_imx->controller->prepare_message = spi_imx_prepare_message; spi_imx->controller->unprepare_message = spi_imx_unprepare_message; spi_imx->controller->slave_abort = spi_imx_slave_abort; - spi_imx->controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; + spi_imx->controller->mode_bits = SPI_MODE_X_MASK | SPI_CS_HIGH | SPI_NO_CS | + SPI_MOSI_IDLE_LOW; if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) From patchwork Wed May 17 22:30:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boerge Struempfel X-Patchwork-Id: 13245824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35C3AC77B7A for ; Wed, 17 May 2023 22:30:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229628AbjEQWa6 (ORCPT ); Wed, 17 May 2023 18:30:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229525AbjEQWav (ORCPT ); Wed, 17 May 2023 18:30:51 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E101259EE; Wed, 17 May 2023 15:30:46 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-965f7bdab6bso254687166b.3; Wed, 17 May 2023 15:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684362645; x=1686954645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wwJ2jZY3dnjuT0EUFOXSV7VbKcctKtPzov6U1NhPAW4=; b=RbGlBFWRA3xf6AobWogZ/o62Go80hrmxmKteFSu4DIYEpr5gmlsdQwulT80Y4ly1c7 bJrbVGnkXLqeWIfdiqkKsQbuVEKFx5z6t3orih7R8AvI/NU1NvZwm0/cnGSgOXdT1Ka1 CzyvWwrJTzs0nInvcjfrI3yWfr1DP9VvOnxn2WW+KAz/JTV+D5C6o6wmrNXayqkSyC74 MHPgKgGLtL6mBh4NDdpxjhJ86IJpOMM4zyw7J/O81pL9dvooWwQJh+oD/oHf1EMqPu25 ldw5jQoxMJpErAynLkV1xoWyUUgNAbtWdh7+JNueStrPbqB2ZV/WIYkf1+w9IiZeTkdw YOGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684362645; x=1686954645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wwJ2jZY3dnjuT0EUFOXSV7VbKcctKtPzov6U1NhPAW4=; b=dsOTRib2PirQP/+Y5VIOwwV6VpykGHjaii9CZFIWMhsLFaWCza8gBuTkO0uycFeJtw twrdTN9TbBgv4CGhJTI0gyKb8mpUENIbDktQwgZozFa5aJ9KgU0RuFO0XPRmqoeRLYQD STX6mV2IB/ENLZJrcI71OO8nVT59/nI+iFBAhDCH+ziQtJDE4RcnS4NwAws1uwu2sGsA 0kxwYy1fDGkQT5CoeCN4MqM3CkqKouGziZxEI60W3Phi/IS9toTQ3bOty086t9r7Pw+x kCVSKwFQLT37ZmMGjnDJKr3aXr1PZ25AMFJYCqWmv16+IUDiUw0lsGWW8W1qanaq/WVy FNFA== X-Gm-Message-State: AC+VfDwccRfuW86O+H119W4/Q1TCDN879ZVq1MFWdiC+yNuuYC2ZsDDZ vicacVlWw/zstNnqLt47aBg= X-Google-Smtp-Source: ACHHUZ5gQ9+esOzZAXGxhnfjprvTP/lv23I4k0RHwccRhvuqGQGV0LNYQUFXARjh7qch2FWKIbCixw== X-Received: by 2002:a17:906:ee84:b0:959:a9a1:589e with SMTP id wt4-20020a170906ee8400b00959a9a1589emr35427005ejb.76.1684362645340; Wed, 17 May 2023 15:30:45 -0700 (PDT) Received: from wslxew193.fritz.box (p200300c78700c900633510ddc4028dcd.dip0.t-ipconnect.de. [2003:c7:8700:c900:6335:10dd:c402:8dcd]) by smtp.gmail.com with ESMTPSA id y14-20020a1709064b0e00b0095807ab4b57sm109327eju.178.2023.05.17.15.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 15:30:44 -0700 (PDT) From: Boerge Struempfel Cc: boerge.struempfel@gmail.com, bstruempfel@ultratronik.de, andy.shevchenko@gmail.com, festevam@gmail.com, amit.kumar-mahapatra@amd.com, broonie@kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/3] spi: spidev: add SPI_MOSI_IDLE_LOW mode bit Date: Thu, 18 May 2023 00:30:07 +0200 Message-Id: <20230517223007.178432-3-boerge.struempfel@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230517223007.178432-1-boerge.struempfel@gmail.com> References: <20230517223007.178432-1-boerge.struempfel@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Allow userspace to set SPI_MOSI_IDLE_LOW mode bit using the SPI_IOC_WR_MODE32 ioctl. Signed-off-by: Boerge Struempfel --- drivers/spi/spidev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 39d94c850839..e50da54468ec 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -64,7 +64,7 @@ static_assert(N_SPI_MINORS > 0 && N_SPI_MINORS <= 256); | SPI_NO_CS | SPI_READY | SPI_TX_DUAL \ | SPI_TX_QUAD | SPI_TX_OCTAL | SPI_RX_DUAL \ | SPI_RX_QUAD | SPI_RX_OCTAL \ - | SPI_RX_CPHA_FLIP) + | SPI_RX_CPHA_FLIP | SPI_MOSI_IDLE_LOW) struct spidev_data { dev_t devt;