From patchwork Thu May 18 09:49:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13246357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 813C3C7EE22 for ; Thu, 18 May 2023 09:56:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6E40010E057; Thu, 18 May 2023 09:56:21 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id D851E10E4ED for ; Thu, 18 May 2023 09:56:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684403775; x=1715939775; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4K9uom5S9jAdpZbyzEthK86FgUUMbqlkEKBp03ctFyw=; b=fdRlpRsyrp6Jr9WxDFb8Im0ZFaGdg1yDiaFISUlL7BCSQxT56KpnaFaK ndfXJdMM3N0hs1E0nvsS3bOQcCjxlC7/N/YYOxtV5jRSbCrJtGWCx/cjc UKcKLjePC31waqXTG7Z9LlrMFqGrvmKAyBPKeHkuijolkN54eQ6q1Zdqo gQjEWj1O4+sagkYxab2UTqxCOmINMS4MKHV98W9TKzw6Lsqtlk8VpCjo9 SpB57NcLKCaH0ymWuGU2E3Ets50Orx81tkAHXmmRbTUGyuZhlDlyIVTbk e1rOR6r6fqE3OJJfih9SioTsPeNxOPxxqbwP/ttoSfNAgF99+VKbUCF3V w==; X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="438366656" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="438366656" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 02:56:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="791897338" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="791897338" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by FMSMGA003.fm.intel.com with ESMTP; 18 May 2023 02:56:12 -0700 From: Arun R Murthy To: intel-gfx@lists.freedesktop.org Date: Thu, 18 May 2023 15:19:11 +0530 Message-Id: <20230518094916.1142812-1-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/display: Add support for global histogram X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" API are added to enable/disable histogram. Upon generation of histogram interrupt its notified to the usespace. User can then use this histogram and generate a LUT which is then fed back to the enahancement block. Histogram is an image statistics based on the input pixel stream. LUT is a look up table consisiting of pixel data. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/Makefile | 1 + .../drm/i915/display/intel_display_types.h | 3 + .../gpu/drm/i915/display/intel_global_hist.c | 295 ++++++++++++++++++ .../gpu/drm/i915/display/intel_global_hist.h | 117 +++++++ 4 files changed, 416 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.c create mode 100644 drivers/gpu/drm/i915/display/intel_global_hist.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5ab909ec24e5..eac1e0d7bd30 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -295,6 +295,7 @@ i915-y += \ display/intel_dpll.o \ display/intel_dpll_mgr.o \ display/intel_dpt.o \ + display/intel_global_hist.o \ display/intel_drrs.o \ display/intel_dsb.o \ display/intel_fb.o \ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ac6951b3e5bd..9848fcf73b87 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1462,6 +1462,9 @@ struct intel_crtc { /* for loading single buffered registers during vblank */ struct pm_qos_request vblank_pm_qos; + /* GLOBAL_HIST data */ + struct intel_global_hist *global_hist; + #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc; u32 cpu_fifo_underrun_count; diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.c b/drivers/gpu/drm/i915/display/intel_global_hist.c new file mode 100644 index 000000000000..ea5bcd195017 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_global_hist.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include "i915_reg.h" +#include "i915_drv.h" +#include "intel_display_types.h" +#include "intel_de.h" +#include "intel_global_hist.h" + +static int intel_global_hist_get_data(struct drm_i915_private *i915, + enum pipe pipe) +{ + struct intel_crtc *intel_crtc = to_intel_crtc( + drm_crtc_from_index(&i915->drm, pipe)); + struct intel_global_hist *global_hist = intel_crtc->global_hist; + u32 dpstbin; + int ret = 0, i = 0; + + /* + * TODO: PSR to be exited while reading the Histogram data + * Set DPST_CTL Bin Reg function select to TC + * Set DPST_CTL Bin Register Index to 0 + */ + intel_de_rmw(i915, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); + + for (i = 0; i < GLOBAL_HIST_BIN_COUNT; i++) { + dpstbin = intel_de_read(i915, DPST_BIN(pipe)); + if (dpstbin & DPST_BIN_BUSY) { + /* + * If DPST_BIN busy bit is set, then set the + * DPST_CTL bin reg index to 0 and proceed + * from begining + */ + intel_de_rmw(i915, DPST_CTL(pipe), + DPST_CTL_BIN_REG_MASK, 0); + i = 0; + } + global_hist->bindata[i] = dpstbin & DPST_BIN_DATA_MASK; + drm_dbg_atomic(&i915->drm, "Hist[%d]=%x\n", + i, global_hist->bindata[i]); + } + + /* Clear histogram interrupt by setting histogram interrupt status bit*/ + intel_de_rmw(i915, DPST_GUARD(pipe), + DPST_GUARD_HIST_EVENT_STATUS, 1); + + return ret; +} + +int intel_global_hist_compute_config(struct intel_crtc *intel_crtc) +{ + struct intel_global_hist *global_hist = intel_crtc->global_hist; + struct drm_i915_private *i915 = global_hist->i915; + + if (!global_hist->has_edp) { + drm_err(&i915->drm, "Not a eDP panel\n"); + return -EINVAL; + } + if (!global_hist->has_pwm) { + drm_err(&i915->drm, "eDP doesn't have PWM based backlight, cannot enable GLOBAL_HIST\n"); + return -EINVAL; + } + /* Restrictions for enabling GLOBAL_HIST */ + global_hist->can_enable = true; + return 0; +} + +static void intel_global_hist_handle_int_work(struct work_struct *work) +{ + struct intel_global_hist *global_hist = container_of(work, + struct intel_global_hist, handle_global_hist_int_work.work); + struct drm_i915_private *i915 = global_hist->i915; + char *global_hist_event[] = {"GLOBAL_HIST=1", NULL}; + + /* Notify user for Histogram rediness */ + if (kobject_uevent_env(&i915->drm.primary->kdev->kobj, KOBJ_CHANGE, + global_hist_event)) + drm_err(&i915->drm, "sending GLOBAL_HIST event failed\n"); + intel_global_hist_get_data(i915, global_hist->pipe); +} + +void intel_global_hist_irq_handler(struct drm_i915_private *i915, enum pipe pipe) +{ + struct intel_crtc *intel_crtc = + to_intel_crtc(drm_crtc_from_index(&i915->drm, pipe)); + struct intel_global_hist *global_hist = intel_crtc->global_hist; + + if (!global_hist->has_pwm) { + drm_err(&i915->drm, + "eDP doesn't have PWM based backlight, failure in GLOBAL_HIST\n"); + return; + } + queue_delayed_work(global_hist->wq, + &global_hist->handle_global_hist_int_work, 0); +} +static void intel_global_hist_enable_dithering(struct drm_i915_private *dev_priv, + enum pipe pipe) +{ + intel_de_rmw(dev_priv, PIPEMISC(pipe), PIPEMISC_DITHER_ENABLE, + PIPEMISC_DITHER_ENABLE); +} + +static int intel_global_hist_enable(struct intel_crtc *intel_crtc) +{ + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + struct intel_global_hist *global_hist = intel_crtc->global_hist; + int pipe = intel_crtc->pipe; + uint32_t gbandthreshold; + + if (!global_hist->has_pwm) { + drm_err(&i915->drm, + "eDP doesn't have PWM based backlight, cannot enable GLOBAL_HIST\n"); + return -EINVAL; + } + + /* Pipe Dithering should be enabled with GLOBAL_HIST */ + intel_global_hist_enable_dithering(i915, pipe); + + /* + * enable DPST_CTL Histogram mode + * Clear DPST_CTL Bin Reg function select to TC + */ + intel_de_rmw(i915, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE | DPST_CTL_IE_TABLE_VALUE_FORMAT, + DPST_CTL_BIN_REG_FUNC_TC | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV | + DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC); + /* check if wait for one vblank is required */ + drm_crtc_wait_one_vblank(&intel_crtc->base); + + /* TODO: one time programming: Program GuardBand Threshold */ + gbandthreshold = ((intel_crtc->config->hw.adjusted_mode.vtotal * + intel_crtc->config->hw.adjusted_mode.htotal) * + GLOBAL_HIST_GUARDBAND_THRESHOLD_DEFAULT) / + GLOBAL_HIST_GUARDBAND_PRECISION_FACTOR; + + /* Enable histogram interrupt mode */ + intel_de_rmw(i915, DPST_GUARD(pipe), + DPST_GUARD_THRESHOLD_GB_MASK | + DPST_GUARD_INTERRUPT_DELAY_MASK | DPST_GUARD_HIST_INT_EN, + DPST_GUARD_THRESHOLD_GB(gbandthreshold) | + DPST_GUARD_INTERRUPT_DELAY(GLOBAL_HIST_DEFAULT_GUARDBAND_DELAY) | + DPST_GUARD_HIST_INT_EN); + + /* Clear pending interrupts has to be done on seperate write */ + intel_de_rmw(i915, DPST_GUARD(pipe), + DPST_GUARD_HIST_EVENT_STATUS, 1); + + global_hist->enable = true; + + return 0; +} + +static int intel_global_hist_disable(struct intel_crtc *intel_crtc) +{ + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + struct intel_global_hist *global_hist = intel_crtc->global_hist; + int pipe = intel_crtc->pipe; + + /* Pipe Dithering should be enabled with GLOBAL_HIST */ + intel_global_hist_enable_dithering(i915, pipe); + + /* Clear pending interrupts and disable interrupts */ + intel_de_rmw(i915, DPST_GUARD(pipe), + DPST_GUARD_HIST_INT_EN | DPST_GUARD_HIST_EVENT_STATUS, 0); + + /* disable DPST_CTL Histogram mode */ + intel_de_rmw(i915, DPST_CTL(pipe), + DPST_CTL_IE_HIST_EN, 0); + + cancel_delayed_work(&global_hist->handle_global_hist_int_work); + global_hist->enable = false; + + return 0; +} + +int intel_global_hist_update(struct intel_crtc *intel_crtc, bool enable) +{ + struct intel_global_hist *global_hist = intel_crtc->global_hist; + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + + if (!global_hist->can_enable) { + drm_err(&i915->drm, + "GLOBAL_HIST not supported, compute config failed\n"); + return 0; + } + + if (enable) + return intel_global_hist_enable(intel_crtc); + else + return intel_global_hist_disable(intel_crtc); +} + +int intel_global_hist_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) +{ + struct intel_global_hist *global_hist = intel_crtc->global_hist; + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + int pipe = intel_crtc->pipe; + int i = 0; + + if (!global_hist->enable) { + drm_err(&i915->drm, "GLOBAL_HIST not enabled"); + return -EINVAL; + } + + /* + * Set DPST_CTL Bin Reg function select to IE + * Set DPST_CTL Bin Register Index to 0 + */ + intel_de_rmw(i915, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, + DPST_CTL_BIN_REG_FUNC_IE | DPST_CTL_BIN_REG_CLEAR); + for (i = 0; i < GLOBAL_HIST_IET_LENGTH; i++) { + intel_de_rmw(i915, DPST_BIN(pipe), + DPST_BIN_DATA_MASK, data[i]); + drm_dbg_atomic(&i915->drm, "iet_lut[%d]=%x\n", i, data[i]); + } + intel_de_rmw(i915, DPST_CTL(pipe), + DPST_CTL_ENHANCEMENT_MODE_MASK | DPST_CTL_IE_MODI_TABLE_EN, + DPST_CTL_EN_MULTIPLICATIVE | DPST_CTL_IE_MODI_TABLE_EN); + /* Once IE is applied, change DPST CTL to TC */ + intel_de_rmw(i915, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL, DPST_CTL_BIN_REG_FUNC_TC); + + return 0; +} + +void intel_global_hist_deinit(struct intel_crtc *intel_crtc) +{ + struct intel_global_hist *global_hist = intel_crtc->global_hist; + + cancel_delayed_work(&global_hist->handle_global_hist_int_work); + destroy_workqueue(global_hist->wq); + kfree(global_hist); +} + +int intel_global_hist_init(struct intel_crtc *intel_crtc) +{ + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + struct intel_global_hist *global_hist; + + /* Allocate global_hist internal struct */ + global_hist = kzalloc(sizeof(*global_hist), GFP_KERNEL); + if (unlikely(!global_hist)) { + drm_err(&i915->drm, + "Failed to allocate GLOBAL_HIST event\n"); + kfree(global_hist); + return -ENOMEM; + } + + intel_crtc->global_hist = global_hist; + global_hist->pipe = intel_crtc->pipe; + global_hist->can_enable = false; + global_hist->wq = alloc_ordered_workqueue("global_hist_wq", + WQ_MEM_RECLAIM); + if (global_hist->wq == NULL) { + drm_err(&i915->drm, + "failed to create work queue\n"); + kfree(global_hist); + return -ENOMEM; + } + + INIT_DEFERRABLE_WORK(&global_hist->handle_global_hist_int_work, + intel_global_hist_handle_int_work); + + global_hist->i915 = i915; + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.h b/drivers/gpu/drm/i915/display/intel_global_hist.h new file mode 100644 index 000000000000..c6621bf4ea61 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_global_hist.h @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __INTEL_GLOBAL_HIST_H__ +#define __INTEL_GLOBAL_HIST_H__ + +#include +#include +#include "intel_display.h" +#include "../i915_reg.h" + +/* GLOBAL_HIST related registers */ +#define _DPST_CTL_A 0x490C0 +#define _DPST_CTL_B 0x491C0 +#define DPST_CTL(pipe) _MMIO_PIPE(pipe, _DPST_CTL_A, _DPST_CTL_B) +#define DPST_CTL_IE_HIST_EN REG_BIT(31) +#define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) +#define DPST_CTL_HIST_MODE REG_BIT(24) +#define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) +#define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) +#define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) +#define DPST_CTL_BIN_REG_FUNC_SEL REG_BIT(11) +#define DPST_CTL_BIN_REG_FUNC_TC (0 << 0) +#define DPST_CTL_BIN_REG_FUNC_IE (1 << 11) +#define DPST_CTL_BIN_REG_MASK REG_GENMASK(6, 0) +#define DPST_CTL_BIN_REG_CLEAR REG_FIELD_PREP(DPST_CTL_BIN_REG_MASK, 0) + +#define _DPST_GUARD_A 0x490C8 +#define _DPST_GUARD_B 0x491C8 +#define DPST_GUARD(pipe) _MMIO_PIPE(pipe, _DPST_GUARD_A, _DPST_GUARD_B) +#define DPST_GUARD_HIST_INT_EN REG_BIT(31) +#define DPST_GUARD_HIST_EVENT_STATUS REG_BIT(30) +#define DPST_GUARD_INTERRUPT_DELAY_MASK REG_GENMASK(29, 22) +#define DPST_GUARD_INTERRUPT_DELAY(val) REG_FIELD_PREP(DPST_GUARD_INTERRUPT_DELAY_MASK, val) +#define DPST_GUARD_THRESHOLD_GB_MASK REG_GENMASK(21, 0) +#define DPST_GUARD_THRESHOLD_GB(val) REG_FIELD_PREP(DPST_GUARD_THRESHOLD_GB_MASK, val) + +#define _DPST_BIN_A 0x490C4 +#define _DPST_BIN_B 0x491C4 +#define DPST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B) +#define DPST_BIN_DATA_MASK REG_GENMASK(23, 0) +#define DPST_BIN_BUSY REG_BIT(31) + +#define DPST_CTL_IE_TABLE_VALUE_FORMAT_2INT_8FRAC (1 << 15) +#define DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC (0 << 15) +#define DPST_CTL_HIST_MODE_YUV (0 << 24) +#define DPST_CTL_HIST_MODE_HSV (1 << 24) + + +#define INTEL_GLOBAL_HISTOGRAM_PIPEA 0x90000000 +#define INTEL_GLOBAL_HISTOGRAM_PIPEB 0x90000002 +#define INTEL_GLOBAL_HISTOGRAM_EVENT(pipe) _PIPE(pipe, \ + INTEL_GLOBAL_HISTOGRAM_PIPEA, \ + INTEL_GLOBAL_HISTOGRAM_PIPEB) + +#define GLOBAL_HIST_BIN_COUNT 32 +#define GLOBAL_HIST_IET_LENGTH 33 + +#define GLOBAL_HIST_GUARDBAND_THRESHOLD_DEFAULT 300 // 3.0% of the pipe's current pixel count. +#define GLOBAL_HIST_GUARDBAND_PRECISION_FACTOR 10000 // Precision factor for threshold guardband. +#define GLOBAL_HIST_DEFAULT_GUARDBAND_DELAY 0x04 + +enum intel_global_hist_status { + INTEL_GLOBAL_HIST_ENABLE, + INTEL_GLOBAL_HIST_DISABLE, +}; + +enum intel_global_histogram { + INTEL_GLOBAL_HISTOGRAM, +}; + +enum intel_global_hist_lut { + INTEL_GLOBAL_HIST_PIXEL_FACTOR, +}; + +struct intel_global_hist { + struct drm_i915_private *i915; + struct workqueue_struct *wq; + struct delayed_work handle_global_hist_int_work; + bool enable; + bool has_pwm; + bool has_edp; + bool can_enable; + enum pipe pipe; + u32 bindata[GLOBAL_HIST_BIN_COUNT]; +}; + +int intel_global_hist_compute_config(struct intel_crtc *intel_crtc); +void intel_global_hist_irq_handler(struct drm_i915_private *i915, enum pipe pipe); +int intel_global_hist_update(struct intel_crtc *intel_crtc, bool enable); +int intel_global_hist_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data); +int intel_global_hist_init(struct intel_crtc *intel_crtc); +void intel_global_hist_deinit(struct intel_crtc *intel_crtc); + +#endif /* __INTEL_GLOBAL_HIST_H__ */ From patchwork Thu May 18 09:49:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13246356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1943C7EE22 for ; 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a="438366662" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="438366662" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 02:56:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="791897344" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="791897344" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by FMSMGA003.fm.intel.com with ESMTP; 18 May 2023 02:56:14 -0700 From: Arun R Murthy To: intel-gfx@lists.freedesktop.org Date: Thu, 18 May 2023 15:19:12 +0530 Message-Id: <20230518094916.1142812-2-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518094916.1142812-1-arun.r.murthy@intel.com> References: <20230518094916.1142812-1-arun.r.murthy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/display: global histogram irq handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With the enablement of global histogram, upon generation of histogram, an interrupt is triggered. This patch handles the irq. Reviewed-by: Uma Shankar Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/i915_irq.c | 6 +++++- drivers/gpu/drm/i915/i915_reg.h | 5 +++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e28bfb5f7347..d72fb6d9282d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -43,6 +43,7 @@ #include "display/intel_hotplug.h" #include "display/intel_lpe_audio.h" #include "display/intel_psr.h" +#include "display/intel_global_hist.h" #include "gt/intel_breadcrumbs.h" #include "gt/intel_gt.h" @@ -2765,6 +2766,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); + if (iir & GEN9_PIPE_GLOBAL_HIST_EVENT) + intel_global_hist_irq_handler(dev_priv, pipe); + if (iir & GEN8_PIPE_VBLANK) intel_handle_vblank(dev_priv, pipe); @@ -5043,7 +5047,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | - GEN8_PIPE_CDCLK_CRC_DONE; + GEN8_PIPE_CDCLK_CRC_DONE | GEN9_PIPE_GLOBAL_HIST_EVENT; u32 de_pipe_enables; u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 94d0c8d14d43..546207ac4859 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3887,7 +3887,7 @@ #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) -#define PIPE_DPST_EVENT_ENABLE (1UL << 23) +#define PIPE_GLOBAL_HIST_EVENT_ENABLE (1UL << 23) #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) @@ -3910,7 +3910,7 @@ #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) -#define PIPE_DPST_EVENT_STATUS (1UL << 7) +#define PIPE_GLOBAL_HIST_EVENT_STATUS (1UL << 7) #define PIPE_A_PSR_STATUS_VLV (1UL << 6) #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) @@ -5815,6 +5815,7 @@ #define GEN8_PIPE_VSYNC (1 << 1) #define GEN8_PIPE_VBLANK (1 << 0) #define GEN9_PIPE_CURSOR_FAULT (1 << 11) +#define GEN9_PIPE_GLOBAL_HIST_EVENT (1 << 12) #define GEN11_PIPE_PLANE7_FAULT (1 << 22) #define GEN11_PIPE_PLANE6_FAULT (1 << 21) #define GEN11_PIPE_PLANE5_FAULT (1 << 20) From patchwork Thu May 18 09:49:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13246358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86FFEC7EE22 for ; Thu, 18 May 2023 09:56:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD11710E4ED; Thu, 18 May 2023 09:56:33 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id A349F10E4F7 for ; Thu, 18 May 2023 09:56:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684403792; x=1715939792; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aUrhgW2mXQ1AzmAPFKFDnDuTNomifQXE5hAtAcz0CbA=; b=Kf1JLZ90u6a3Jk4v2SXQxq1FXglk/S9nfAQbleUypLPCGY5FNXlGZpS3 qdROY4Us2tQoterliIVdwucOJ8UCbPiJ32U+ipPRqDBXU7KOt6HAwdOrz 21HlsqQW34r3hBv120bXcGGN+tYZDJ9t4UBHZA033Zb76dYkYOQgonFNi zdMCRWchNSOHyTsPoQ79I5OqcwfYzPdLNQ97mUOyPcPSFYeeJe2dJcqwY mo8vq3EcSyonDADndMJt5H+T1vrQ1lbUxOPmt2jdx+EIiXkae8lKPHZ7o kcN0zSsWLC1BgfcNu55wRcWu7MlEt4MbCcuhNd8jpCVzXj0Ydl4h8/XOf g==; X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="438366666" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="438366666" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 02:56:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="791897347" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="791897347" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by FMSMGA003.fm.intel.com with ESMTP; 18 May 2023 02:56:15 -0700 From: Arun R Murthy To: intel-gfx@lists.freedesktop.org Date: Thu, 18 May 2023 15:19:13 +0530 Message-Id: <20230518094916.1142812-3-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518094916.1142812-1-arun.r.murthy@intel.com> References: <20230518094916.1142812-1-arun.r.murthy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/display: global histogram restrictions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For global histogram the panel should be edp and should have pwm based backlight controller. Flags are updated accordingly. Reviewed-by: Uma Shankar Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_modeset_setup.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index cd21b0ddbabb..975d6bdb59f3 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -17,12 +17,14 @@ #include "intel_crtc_state_dump.h" #include "intel_ddi.h" #include "intel_de.h" +#include "intel_dp.h" #include "intel_display.h" #include "intel_display_power.h" #include "intel_display_types.h" #include "intel_modeset_setup.h" #include "intel_pch_display.h" #include "intel_pm.h" +#include "intel_global_hist.h" static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) @@ -309,6 +311,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); struct intel_crtc_state *crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; + struct intel_panel *panel; /* * We need to check both for a crtc link (meaning that the encoder is @@ -376,6 +379,15 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) if (HAS_DDI(i915)) intel_ddi_sanitize_encoder_pll_mapping(encoder); + + /* validate the global hist struct elements */ + if (intel_dp_is_port_edp(i915, encoder->port)) { + crtc->global_hist->has_edp = true; + panel = &connector->panel; + if (panel->backlight.present == true) + crtc->global_hist->has_pwm = true; + } + } /* FIXME read out full plane state for all planes */ From patchwork Thu May 18 09:49:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13246360 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C449C7EE22 for ; Thu, 18 May 2023 09:56:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A2A710E4FD; Thu, 18 May 2023 09:56:38 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 72D4A10E4F7 for ; Thu, 18 May 2023 09:56:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684403794; x=1715939794; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ozjb2E1llFhioCf9BggMukPIdpDIXXPaKen7gE7n8mM=; b=TVfKwwNE5lq0bj3owDkWJ6j9B2rw4ru7wZP9MtiMYzcWmEXD2zb5jXr3 A+vQh6aWE4Cypgxde8272v/RETqw/l/f7ZV9zOB7KpP95jSIQiRB6MySH A1xVatwOyowuY5tBEUCaZIzbxJNx9araFtvmD5zVV32tYm3hEQxNOIwcA 9ew8QsvVDuUyJYUb8a+LC+8dyGiW/51fUnk+J7mYRuQKh5howUG6HdQCX EEuPZuDo191x3JI9vih0Kq4XCqZe7mUzoLmH+StsV38ymmIKlT07I54aI W0C0g1K6el19SdLvM7VmVX5tvAkf/m/xlrnokuSWsv/c5xoPm/oa/tzNZ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="438366672" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="438366672" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 02:56:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="791897352" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="791897352" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by FMSMGA003.fm.intel.com with ESMTP; 18 May 2023 02:56:16 -0700 From: Arun R Murthy To: intel-gfx@lists.freedesktop.org Date: Thu, 18 May 2023 15:19:14 +0530 Message-Id: <20230518094916.1142812-4-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518094916.1142812-1-arun.r.murthy@intel.com> References: <20230518094916.1142812-1-arun.r.murthy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/display: Add crtc properties for global histogram X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" CRTC properties have been added for enable/disable histogram, reading the histogram data and writing the IET data. "GLOBAL_HIST_EN" is the crtc property to enable/disable the global histogram and takes a value 0/1 accordingly. "Global Histogram" is a crtc property to read the binary histogram data. "Global IET" is a crtc property to write the IET binary LUT data. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_atomic.c | 5 + drivers/gpu/drm/i915/display/intel_crtc.c | 200 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_crtc.h | 5 + drivers/gpu/drm/i915/display/intel_display.c | 13 ++ .../drm/i915/display/intel_display_types.h | 19 +- .../gpu/drm/i915/display/intel_global_hist.c | 7 + 6 files changed, 246 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 0e5d57c978fe..bed682854071 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -245,6 +245,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi); + if (crtc_state->global_iet) + drm_property_blob_get(crtc_state->global_iet); /* copy color blobs */ if (crtc_state->hw.degamma_lut) drm_property_blob_get(crtc_state->hw.degamma_lut); @@ -266,6 +268,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->fb_bits = 0; crtc_state->update_planes = 0; crtc_state->dsb = NULL; + crtc_state->global_hist_en_changed = false; return &crtc_state->uapi; } @@ -298,6 +301,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, drm_WARN_ON(crtc->dev, crtc_state->dsb); + if (crtc_state->global_iet) + drm_property_blob_put(crtc_state->global_iet); __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); intel_crtc_free_hw_state(crtc_state); kfree(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 521dc676e2d0..501bcf732aba 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "i915_irq.h" #include "i915_vgpu.h" @@ -26,6 +27,7 @@ #include "intel_display_types.h" #include "intel_drrs.h" #include "intel_dsi.h" +#include "intel_global_hist.h" #include "intel_pipe_crc.h" #include "intel_psr.h" #include "intel_sprite.h" @@ -196,6 +198,7 @@ static struct intel_crtc *intel_crtc_alloc(void) static void intel_crtc_free(struct intel_crtc *crtc) { intel_crtc_destroy_state(&crtc->base, crtc->base.state); + intel_global_hist_deinit(crtc); kfree(crtc); } @@ -215,6 +218,99 @@ static int intel_crtc_late_register(struct drm_crtc *crtc) return 0; } +int intel_crtc_get_property(struct drm_crtc *crtc, + const struct drm_crtc_state *state, + struct drm_property *property, + uint64_t *val) +{ + struct drm_i915_private *i915 = to_i915(crtc->dev); + struct intel_crtc_state *intel_crtc_state = + to_intel_crtc_state(state); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + + if (property == intel_crtc->global_hist_en_property) + *val = intel_crtc_state->global_hist_en; + else if (property == intel_crtc->global_iet_property) + *val = (intel_crtc_state->global_iet) ? + intel_crtc_state->global_iet->base.id : 0; + else if (property == intel_crtc->global_hist_property) + *val = (intel_crtc_state->global_hist) ? + intel_crtc_state->global_hist->base.id : 0; + else { + drm_err(&i915->drm, + "Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); + return -EINVAL; + } + + return 0; +} + +static int +intel_atomic_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced) +{ + struct drm_property_blob *new_blob = NULL; + + if (blob_id != 0) { + new_blob = drm_property_lookup_blob(dev, blob_id); + if (new_blob == NULL) + return -EINVAL; + + if (expected_size > 0 && + new_blob->length != expected_size) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + if (expected_elem_size > 0 && + new_blob->length % expected_elem_size != 0) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + } + + *replaced |= drm_property_replace_blob(blob, new_blob); + drm_property_blob_put(new_blob); + + return 0; +} + +int intel_crtc_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *state, + struct drm_property *property, + u64 val) +{ + struct drm_i915_private *i915 = to_i915(crtc->dev); + struct intel_crtc_state *intel_crtc_state = + to_intel_crtc_state(state); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + bool replaced = false; + + if (property == intel_crtc->global_hist_en_property) { + intel_crtc_state->global_hist_en = val; + intel_crtc_state->global_hist_en_changed = true; + return 0; + } + + if (property == intel_crtc->global_iet_property) { + intel_atomic_replace_property_blob_from_id(crtc->dev, + &intel_crtc_state->global_iet, val, + sizeof(uint32_t) * GLOBAL_HIST_IET_LENGTH, + -1, &replaced); + if (replaced) + intel_crtc_state->global_iet_changed = true; + return 0; + } + + drm_dbg_atomic(&i915->drm, "Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); + return -EINVAL; +} + #define INTEL_CRTC_FUNCS \ .set_config = drm_atomic_helper_set_config, \ .destroy = intel_crtc_destroy, \ @@ -225,7 +321,9 @@ static int intel_crtc_late_register(struct drm_crtc *crtc) .verify_crc_source = intel_crtc_verify_crc_source, \ .get_crc_sources = intel_crtc_get_crc_sources, \ .late_register = intel_crtc_late_register, \ - .pre_crc_read = intel_crtc_pre_crc_read + .pre_crc_read = intel_crtc_pre_crc_read, \ + .atomic_set_property = intel_crtc_set_property, \ + .atomic_get_property = intel_crtc_get_property static const struct drm_crtc_funcs bdw_crtc_funcs = { INTEL_CRTC_FUNCS, @@ -371,6 +469,10 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) intel_crtc_drrs_init(crtc); intel_crtc_crc_init(crtc); + intel_global_hist_init(crtc); + + /* Initialize crtc properties */ + intel_crtc_add_property(crtc); cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE); @@ -713,3 +815,99 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) dbg_vblank_evade(crtc, end_vbl_time); } + +static const struct drm_prop_enum_list global_hist_en_names[] = { + { INTEL_GLOBAL_HIST_DISABLE, "Disable" }, + { INTEL_GLOBAL_HIST_ENABLE, "Enable" }, +}; + +/** + * intel_attach_global_hist_en_property() - add property to enable/disable histogram + * @intel_crtc: pointer to the struct intel_crtc on which the global histogram is to + * be enabled/disabled + * + * "GLOBAL_HIST_EN" is the crtc proeprty to enable/disable global histogram + */ +void intel_attach_global_hist_en_property(struct intel_crtc *intel_crtc) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_property *prop; + + prop = intel_crtc->global_hist_en_property; + if (prop == NULL) { + prop = drm_property_create_enum(dev, 0, + "GLOBAL_HIST_EN", + global_hist_en_names, + ARRAY_SIZE(global_hist_en_names)); + if (prop == NULL) + return; + + intel_crtc->global_hist_en_property = prop; + } + + drm_object_attach_property(&crtc->base, prop, 0); +} + +/** + * intel_attach_global_iet_property() - add property to write Image Enhancement data + * @intel_crtc: pointer to the struct intel_crtc on which global histogram is enabled + * + * "Global IET" is the crtc property to write the Image Enhancement LUT binary data + */ +void intel_attach_global_iet_property(struct intel_crtc *intel_crtc) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_property *prop; + + prop = intel_crtc->global_iet_property; + if (prop == NULL) { + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB | DRM_MODE_PROP_ATOMIC, + "Global IET", 0); + if (prop == NULL) + return; + + intel_crtc->global_iet_property = prop; + } + + drm_object_attach_property(&crtc->base, prop, 0); +} + +/** + * intel_atach_global_hist_property() - crtc proeprty to read the histogram. + * @intel_crtc: pointer to the struct intel_crtc on which the global histogram + * was enabled. + * "Global Histogram" is the crtc property to read the binary histogram data. + */ +void intel_attach_global_hist_property(struct intel_crtc *intel_crtc) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_property *prop; + struct drm_property_blob *blob; + + prop = intel_crtc->global_hist_property; + if (prop == NULL) { + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB | + DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_IMMUTABLE, + "Global Histogram", 0); + if (prop == NULL) + return; + + intel_crtc->global_hist_property = prop; + } + blob = drm_property_create_blob(dev, sizeof(uint32_t) * GLOBAL_HIST_BIN_COUNT, NULL); + intel_crtc->config->global_hist = blob; + + drm_object_attach_property(&crtc->base, prop, blob->base.id); +} + +int intel_crtc_add_property(struct intel_crtc *intel_crtc) +{ + intel_attach_global_hist_en_property(intel_crtc); + intel_attach_global_hist_property(intel_crtc); + intel_attach_global_iet_property(intel_crtc); + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h index 73077137fb99..6744b6a03e19 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.h +++ b/drivers/gpu/drm/i915/display/intel_crtc.h @@ -7,6 +7,7 @@ #define _INTEL_CRTC_H_ #include +#include enum i9xx_plane_id; enum pipe; @@ -36,4 +37,8 @@ void intel_wait_for_vblank_if_active(struct drm_i915_private *i915, enum pipe pipe); void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc); +int intel_crtc_add_property(struct intel_crtc *intel_crtc); +void intel_attach_global_hist_en_property(struct intel_crtc *intel_crtc); +void intel_attach_global_iet_property(struct intel_crtc *intel_crtc); +void intel_attach_global_hist_property(struct intel_crtc *intel_crtc); #endif diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ab3c9e8d4157..6255c6443726 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -52,6 +52,7 @@ #include "display/intel_dp.h" #include "display/intel_dp_mst.h" #include "display/intel_dpll.h" +#include "display/intel_global_hist.h" #include "display/intel_dpll_mgr.h" #include "display/intel_drrs.h" #include "display/intel_dsi.h" @@ -4921,6 +4922,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (ret) return ret; + /* GLOBAL_HIST changed */ + if (crtc_state->global_hist_en_changed) + intel_global_hist_compute_config(crtc); + return 0; } @@ -7730,6 +7735,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * commit_done and later do dsb cleanup in cleanup_work. */ old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); + + /* Re-Visit: GLOBAL_HIST related stuff */ + if (new_crtc_state->global_hist_en_changed) + intel_global_hist_update(crtc, + new_crtc_state->global_hist_en); + if (new_crtc_state->global_iet_changed) + intel_global_hist_set_iet_lut(crtc, + (u32 *)new_crtc_state->global_iet->data); } /* Underruns don't always raise interrupts, so check manually */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9848fcf73b87..15d28e2305da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -94,6 +94,12 @@ enum intel_broadcast_rgb { INTEL_BROADCAST_RGB_LIMITED, }; +/* GLOBAL_HIST property */ +enum intel_global_hist_en_prop { + INTEL_GLOBAL_HIST_PROP_DISABLE, + INTEL_GLOBAL_HIST_PROP_ENABLE, +}; + struct intel_fb_view { /* * The remap information used in the remapped and rotated views to @@ -1360,6 +1366,13 @@ struct intel_crtc_state { /* for loading single buffered registers during vblank */ struct drm_vblank_work vblank_work; + + /* GLOBAL_HIST data */ + int global_hist_en; + struct drm_property_blob *global_iet; + struct drm_property_blob *global_hist; + bool global_iet_changed; + bool global_hist_en_changed; }; enum intel_pipe_crc_source { @@ -1462,9 +1475,11 @@ struct intel_crtc { /* for loading single buffered registers during vblank */ struct pm_qos_request vblank_pm_qos; - /* GLOBAL_HIST data */ struct intel_global_hist *global_hist; - + /* GLOBAL_HIST properties */ + struct drm_property *global_hist_en_property; + struct drm_property *global_iet_property; + struct drm_property *global_hist_property; #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc; u32 cpu_fifo_underrun_count; diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.c b/drivers/gpu/drm/i915/display/intel_global_hist.c index ea5bcd195017..874d80d1e41b 100644 --- a/drivers/gpu/drm/i915/display/intel_global_hist.c +++ b/drivers/gpu/drm/i915/display/intel_global_hist.c @@ -69,6 +69,12 @@ static int intel_global_hist_get_data(struct drm_i915_private *i915, intel_de_rmw(i915, DPST_GUARD(pipe), DPST_GUARD_HIST_EVENT_STATUS, 1); + drm_property_replace_global_blob(&i915->drm, + &intel_crtc->config->global_hist, + sizeof(global_hist->bindata), + global_hist->bindata, &intel_crtc->base.base, + intel_crtc->global_hist_property); + return ret; } @@ -196,6 +202,7 @@ static int intel_global_hist_disable(struct intel_crtc *intel_crtc) cancel_delayed_work(&global_hist->handle_global_hist_int_work); global_hist->enable = false; + intel_crtc->config->global_hist_en = false; return 0; } From patchwork Thu May 18 09:49:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13246359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75910C7EE23 for ; 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a="438366677" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="438366677" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 02:56:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="791897357" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="791897357" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by FMSMGA003.fm.intel.com with ESMTP; 18 May 2023 02:56:18 -0700 From: Arun R Murthy To: intel-gfx@lists.freedesktop.org Date: Thu, 18 May 2023 15:19:15 +0530 Message-Id: <20230518094916.1142812-5-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518094916.1142812-1-arun.r.murthy@intel.com> References: <20230518094916.1142812-1-arun.r.murthy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/display: crtc property for global hist selective fetch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" User can provide the selective fetch co-ordinates for global histogram using crtc blob property. This patch adds the crtc blob property. The selective fetch can be done only on the y co-ordinate and cannot be done on the x co-ordinate. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_crtc.c | 45 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 3 ++ 2 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 501bcf732aba..2a9dcf3b1a19 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -236,6 +236,9 @@ int intel_crtc_get_property(struct drm_crtc *crtc, else if (property == intel_crtc->global_hist_property) *val = (intel_crtc_state->global_hist) ? intel_crtc_state->global_hist->base.id : 0; + else if (property == intel_crtc->global_hist_sf_clips_property) + *val = (intel_crtc_state->global_hist_sf_clips) ? + intel_crtc_state->global_hist_sf_clips->base.id : 0; else { drm_err(&i915->drm, "Unknown property [PROP:%d:%s]\n", @@ -306,6 +309,18 @@ int intel_crtc_set_property(struct drm_crtc *crtc, return 0; } + if (property == intel_crtc->global_hist_sf_clips_property) { + intel_atomic_replace_property_blob_from_id(crtc->dev, + &intel_crtc_state->global_hist_sf_clips, + val, + -1, + sizeof(struct drm_rect), + &replaced); + if (replaced) + intel_crtc_state->global_hist_sf_clips_updates = true; + return 0; + } + drm_dbg_atomic(&i915->drm, "Unknown property [PROP:%d:%s]\n", property->base.id, property->name); return -EINVAL; @@ -903,11 +918,41 @@ void intel_attach_global_hist_property(struct intel_crtc *intel_crtc) drm_object_attach_property(&crtc->base, prop, blob->base.id); } +/** + * intel_attach_global_hist_sf_seg_property() - selective fetch segment property + * @intel_crtc: pointer to struct intel_crtc on which global histogram is enabled + * + * "Global Histogram SF CLIPS" is the crtc porperty used to provide the + * co-ordinates of the damage clips. + */ +void intel_attach_global_hist_sf_seg_property(struct intel_crtc * intel_crtc) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_property *prop; + struct drm_property_blob *blob; + + prop = intel_crtc->global_hist_sf_clips_property; + if (prop == NULL) { + prop = drm_property_create(dev, + DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_BLOB, + "Global Histogram SF CLIPS", 0); + if (prop == NULL) + return; + intel_crtc->global_hist_sf_clips_property = prop; + } + blob = drm_property_create_blob(dev, sizeof(struct drm_rect *), NULL); + intel_crtc->config->global_hist_sf_clips = blob; + + drm_object_attach_property(&crtc->base, prop, blob->base.id); +} + int intel_crtc_add_property(struct intel_crtc *intel_crtc) { intel_attach_global_hist_en_property(intel_crtc); intel_attach_global_hist_property(intel_crtc); intel_attach_global_iet_property(intel_crtc); + intel_attach_global_hist_sf_seg_property(intel_crtc); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 15d28e2305da..703593d4a52f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1371,8 +1371,10 @@ struct intel_crtc_state { int global_hist_en; struct drm_property_blob *global_iet; struct drm_property_blob *global_hist; + struct drm_property_blob *global_hist_sf_clips; bool global_iet_changed; bool global_hist_en_changed; + bool global_hist_sf_clips_updates; }; enum intel_pipe_crc_source { @@ -1480,6 +1482,7 @@ struct intel_crtc { struct drm_property *global_hist_en_property; struct drm_property *global_iet_property; struct drm_property *global_hist_property; + struct drm_property *global_hist_sf_clips_property; #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc; u32 cpu_fifo_underrun_count; From patchwork Thu May 18 09:49:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13246361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A71F4C7EE23 for ; Thu, 18 May 2023 09:56:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A11E10E4FA; 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18 May 2023 02:56:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10713"; a="791897361" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="791897361" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by FMSMGA003.fm.intel.com with ESMTP; 18 May 2023 02:56:19 -0700 From: Arun R Murthy To: intel-gfx@lists.freedesktop.org Date: Thu, 18 May 2023 15:19:16 +0530 Message-Id: <20230518094916.1142812-6-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518094916.1142812-1-arun.r.murthy@intel.com> References: <20230518094916.1142812-1-arun.r.murthy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/display: Enable global hist Selective fetch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch enables support for selective fetch in global histogram. User can provide the selective fetch co-ordinates and only that region will be used in generating the histogram. Signed-off-by: Arun R Murthy --- .../gpu/drm/i915/display/intel_global_hist.c | 65 +++++++++++++++++++ .../gpu/drm/i915/display/intel_global_hist.h | 14 ++++ 2 files changed, 79 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.c b/drivers/gpu/drm/i915/display/intel_global_hist.c index 874d80d1e41b..13ec68463eec 100644 --- a/drivers/gpu/drm/i915/display/intel_global_hist.c +++ b/drivers/gpu/drm/i915/display/intel_global_hist.c @@ -31,6 +31,48 @@ #include "intel_de.h" #include "intel_global_hist.h" +#define MIN_SEGMENTS 32 +#define MAX_SEGMENTS 128 + +static int intel_global_hist_calc_seg_size(struct drm_i915_private *dev_priv, + enum pipe pipe) +{ + uint32_t tmp, source_height; + uint16_t seg_size = MIN_SEGMENTS; + + /* Get the pipe source height from the pipesr register */ + tmp = intel_de_read(dev_priv, PIPESRC(pipe)); + source_height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1; + + while (seg_size <= source_height) { + if ((seg_size % source_height == 0) && + ((source_height / seg_size) < MAX_SEGMENTS)) + break; + seg_size++; + } + + return seg_size; +} + +int intel_global_hist_sf_update_seg(struct drm_i915_private *i915, + enum pipe pipe, struct drm_rect *clip) +{ + uint16_t seg_size; + + seg_size = intel_global_hist_calc_seg_size(i915, pipe); + if (!seg_size) + return -EINVAL; + + intel_de_rmw(i915, DPST_SF_SEG(pipe), + DPST_SF_SEG_SIZE_MASK | DPST_SF_SEG_START_MASK | + DPST_SF_SEG_END_MASK, + DPST_SF_SEG_SIZE(seg_size) | + DPST_SF_SEG_START((clip->y2/seg_size) * seg_size) | + DPST_SF_SEG_END((clip->y1/seg_size) * seg_size)); + + return 0; +} + static int intel_global_hist_get_data(struct drm_i915_private *i915, enum pipe pipe) { @@ -258,6 +300,29 @@ int intel_global_hist_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) return 0; } +int intel_global_hist_sf_en(struct drm_i915_private *i915, + enum pipe pipe, struct drm_rect *clip) +{ + struct intel_crtc *intel_crtc = to_intel_crtc( + drm_crtc_from_index(&i915->drm, pipe)); + struct intel_global_hist *global_hist = intel_crtc->global_hist; + uint32_t dpstsfctl; + + /* If DPST is not enabled, enable it first */ + if (!global_hist->enable) + intel_global_hist_enable(intel_crtc); + + /* Program dpst selective fetch */ + dpstsfctl = intel_de_read(i915, DPST_SF_CTL(pipe)); + dpstsfctl |= DPST_SF_CTL_ENABLE; + intel_de_write(i915, DPST_SF_CTL(pipe), dpstsfctl); + + /* Program the segment size */ + intel_global_hist_sf_update_seg(i915, pipe, clip); + + return 0; +} + void intel_global_hist_deinit(struct intel_crtc *intel_crtc) { struct intel_global_hist *global_hist = intel_crtc->global_hist; diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.h b/drivers/gpu/drm/i915/display/intel_global_hist.h index c6621bf4ea61..827c61badf66 100644 --- a/drivers/gpu/drm/i915/display/intel_global_hist.h +++ b/drivers/gpu/drm/i915/display/intel_global_hist.h @@ -82,6 +82,20 @@ #define GLOBAL_HIST_GUARDBAND_PRECISION_FACTOR 10000 // Precision factor for threshold guardband. #define GLOBAL_HIST_DEFAULT_GUARDBAND_DELAY 0x04 +#define _DPST_SF_CTL_A 0x490D0 +#define _DPST_SF_CTL_B 0x491D0 +#define DPST_SF_CTL(pipe) _MMIO_PIPE(pipe, _DPST_SF_CTL_A, _DPST_SF_CTL_B) +#define DPST_SF_CTL_ENABLE (1 << 31) +#define _DPST_SF_SEG_A 0x490D4 +#define _DPST_SF_SEG_B 0x491D4 +#define DPST_SF_SEG(pipe) _MMIO_PIPE(pipe, _DPST_SF_CTL_A, _DPST_SF_CTL_B) +#define DPST_SF_SEG_START_MASK REG_GENMASK(30, 24) +#define DPST_SF_SEG_START(val) REG_FIELD_PREP(DPST_SF_SEG_START_MASK, val) +#define DPST_SF_SEG_END_MASK REG_GENMASK(22, 16) +#define DPST_SF_SEG_END(val) REG_FIELD_PREP(DPST_SF_SEG_END_MASK, val) +#define DPST_SF_SEG_SIZE_MASK REG_GENMASK(15, 0) +#define DPST_SF_SEG_SIZE(val) REG_FIELD_PREP(DPST_SF_SEG_SIZE_MASK, val) + enum intel_global_hist_status { INTEL_GLOBAL_HIST_ENABLE, INTEL_GLOBAL_HIST_DISABLE,