From patchwork Fri May 19 15:49:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13248509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE9F5C7EE26 for ; Fri, 19 May 2023 15:49:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B3D710E55F; Fri, 19 May 2023 15:49:51 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE42E10E5A6 for ; Fri, 19 May 2023 15:49:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684511389; x=1716047389; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=aF/Oyr4ep6ARZSN/tkKhqNydF6oLK69811WG2HTgg3k=; b=esUB86prMsqhJzKo+xBCMxKyb0XxYTjMZQPPzRxjSy78vfq1uIGsAC1h vA/XEJpP6rDh3mjvQ+0x5iJJTeSQGyD9RUUbEqbBDD9qSyFpgPUySojLW vqsCUffMkgAR8nIWTTCyQTAkslE/mEptO+/652cRnY2rhh4i/dOf94b04 qRIxxQ2E4OoxKx+Dd310vBrdQukHfVGxxlqdxnOWAyiJyH5s2ITbXw9Hp 5cZPSciYwE+Gi7U7Ibs9YLqGFTEkdjaQ7kOQLSkmCCTscDUbPU0h2n/ma l3eFexmMCPXxlHZl+KIaffF5ljDfZZckwsB/dMB3WjSa/42g1hAwopTbO w==; X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="354759565" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="354759565" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="1032652186" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="1032652186" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 May 2023 08:49:40 -0700 Message-Id: <20230519154946.3751971-2-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> References: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 1/7] drm/i915/pmu: Change bitmask of enabled events to u32 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Having it as u64 was a confusing (but harmless) mistake. Also add some asserts to make sure the internal field does not overflow in the future. v2: Fix WARN_ON firing for INTERRUPT event (Umesh) Signed-off-by: Tvrtko Ursulin Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_pmu.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 7ece883a7d95..96543dce2db1 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event) return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff; } -static bool is_engine_config(u64 config) +static bool is_engine_config(const u64 config) { return config < __I915_PMU_OTHER(0); } @@ -88,9 +88,20 @@ static unsigned int config_bit(const u64 config) return other_bit(config); } -static u64 config_mask(u64 config) +static u32 config_mask(const u64 config) { - return BIT_ULL(config_bit(config)); + unsigned int bit = config_bit(config); + + if (__builtin_constant_p(config)) + BUILD_BUG_ON(bit > + BITS_PER_TYPE(typeof_member(struct i915_pmu, + enable)) - 1); + else + WARN_ON_ONCE(bit > + BITS_PER_TYPE(typeof_member(struct i915_pmu, + enable)) - 1); + + return BIT(config_bit(config)); } static bool is_engine_event(struct perf_event *event) @@ -633,11 +644,10 @@ static void i915_pmu_enable(struct perf_event *event) { struct drm_i915_private *i915 = container_of(event->pmu, typeof(*i915), pmu.base); + const unsigned int bit = event_bit(event); struct i915_pmu *pmu = &i915->pmu; unsigned long flags; - unsigned int bit; - bit = event_bit(event); if (bit == -1) goto update; @@ -651,7 +661,7 @@ static void i915_pmu_enable(struct perf_event *event) GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count)); GEM_BUG_ON(pmu->enable_count[bit] == ~0); - pmu->enable |= BIT_ULL(bit); + pmu->enable |= BIT(bit); pmu->enable_count[bit]++; /* @@ -698,7 +708,7 @@ static void i915_pmu_disable(struct perf_event *event) { struct drm_i915_private *i915 = container_of(event->pmu, typeof(*i915), pmu.base); - unsigned int bit = event_bit(event); + const unsigned int bit = event_bit(event); struct i915_pmu *pmu = &i915->pmu; unsigned long flags; @@ -734,7 +744,7 @@ static void i915_pmu_disable(struct perf_event *event) * bitmask when the last listener on an event goes away. */ if (--pmu->enable_count[bit] == 0) { - pmu->enable &= ~BIT_ULL(bit); + pmu->enable &= ~BIT(bit); pmu->timer_enabled &= pmu_needs_timer(pmu, true); } From patchwork Fri May 19 15:49:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13248507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07C16C77B7A for ; Fri, 19 May 2023 15:49:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CFF7310E545; Fri, 19 May 2023 15:49:50 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2350210E5AD for ; Fri, 19 May 2023 15:49:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684511389; x=1716047389; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=fl7dbaPQSl6BpZOYfLgDzVwyNrz9xkVOcq8x2iNPnd4=; b=ZHXDAN1rFDB9+ER2ZcocYKS3MzuBjmWw2KIlOQXlnQfR5CCNLJjDqG8P k7xJ1Xilld/C0s3WkSHwqqT7Sa7laFTxhDbS75Nga8SspiQ+k8Q9xa0Xf PP5FqXYGWTzYg9Bd9JFA9DcbA+lj5AJQshLpqpPvpiv72lJX2jury6qSS DYprrukw7NuYP4NCKxhZNxE2sqgqjTu827aI3WhSBg/DLQhYV70/fRm5C MSNbZ7jsdZ5ooyZM5yB5llP+lXLtVlrYjLzt2JHsbbxBoXJD8CPmW3Tk9 bYD/sfYhspGym/czQwtQg8gRUjHFxE7LZFsf5PyfWST+mtaNiWZVPQR4/ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="354759566" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="354759566" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="1032652187" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="1032652187" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 May 2023 08:49:41 -0700 Message-Id: <20230519154946.3751971-3-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> References: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 2/7] drm/i915/pmu: Support PMU for all engines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Given how the metrics are already exported, we also need to run sampling over engines from all GTs. Problem of GT frequencies is left for later. Signed-off-by: Tvrtko Ursulin Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 96543dce2db1..9edf87ee5d10 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -10,6 +10,7 @@ #include "gt/intel_engine_pm.h" #include "gt/intel_engine_regs.h" #include "gt/intel_engine_user.h" +#include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" #include "gt/intel_gt_regs.h" #include "gt/intel_rc6.h" @@ -425,8 +426,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) struct drm_i915_private *i915 = container_of(hrtimer, struct drm_i915_private, pmu.timer); struct i915_pmu *pmu = &i915->pmu; - struct intel_gt *gt = to_gt(i915); unsigned int period_ns; + struct intel_gt *gt; + unsigned int i; ktime_t now; if (!READ_ONCE(pmu->timer_enabled)) @@ -442,8 +444,13 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) * grabbing the forcewake. However the potential error from timer call- * back delay greatly dominates this so we keep it simple. */ - engines_sample(gt, period_ns); - frequency_sample(gt, period_ns); + + for_each_gt(gt, i915, i) { + engines_sample(gt, period_ns); + + if (i == 0) /* FIXME */ + frequency_sample(gt, period_ns); + } hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD)); From patchwork Fri May 19 15:49:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13248508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07AD5C77B7F for ; Fri, 19 May 2023 15:49:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F98F10E55B; Fri, 19 May 2023 15:49:51 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24A7E10E5B0 for ; Fri, 19 May 2023 15:49:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684511389; x=1716047389; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=CelYkmB1/m4ItmUgogM+FRqPlWoJ6AXltO/8LYu6FVc=; b=QkmypH+Gm6muz3Ja6zjBFKtLvNJRtlPvBMxpmokve8opgnLHs0PoFY0f XvwDSn/p+MWkwzYTd0NrsAD8fJcCQrBQqm9D5MfmtWcE/ewYFhPS22ubK tONRzNYVj+MV6UgRMIm8cJjZj5dagM1V1iqLtGcoVamDxOKhKwl3QEOVo mGl92GbywN4I2TSvUSSn+PuPCUUCWmkCn9ctB44hngIIeKimRXVzouyTx jR5w5jkNAAxTfnaurdDo5CY88yuNSxDrei7Iv1F/zzLkZYWoiPl+UQIGY fbMWSUBZoS4dLSg+J6jNlB+jjfSmWUbwh3CNJMufXJUSCyMmddyWwlRcH g==; X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="354759567" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="354759567" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="1032652188" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="1032652188" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 May 2023 08:49:42 -0700 Message-Id: <20230519154946.3751971-4-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> References: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 3/7] drm/i915/pmu: Skip sampling engines with no enabled counters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin As we have more and more engines do not waste time sampling the ones no- one is monitoring. Signed-off-by: Tvrtko Ursulin Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 9edf87ee5d10..6d594f67f365 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -350,6 +350,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) return; for_each_engine(engine, gt, id) { + if (!engine->pmu.enable) + continue; + if (!intel_engine_pm_get_if_awake(engine)) continue; From patchwork Fri May 19 15:49:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13248513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62E7DC7EE2D for ; Fri, 19 May 2023 15:50:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 245D610E5B5; Fri, 19 May 2023 15:49:53 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4074D10E545 for ; Fri, 19 May 2023 15:49:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684511389; x=1716047389; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=qH0zra8MWjzW157TJu44lU37iW4JiKKiuB+5sr1EUSg=; b=W18MNvEj/ibS5knVfQKtYOKZamu0fVZupXNQw4HMvbr2B/DtH2PBSeAM 2pniACCFG8WxVRdRZ670CKRO03RAm70cSFC1gWUQ4Mu32Xroh2d1nx+bf R24imhw2n94ES6OxuJw45M5o9sLAGexFNk2HbrRg6Ro9J/tm4sp9unZ+B NBu7+c538mBK2c5RnE2WFmH8EAfpqf4PwXEDyOdC396eDFci/qGJzikf4 XFvxIi/bSrx818tRvRSCxBoXFl9HiNupESBxqh1fOsLZFIt98N/vN5e39 KhKywlGvqBZjwoH/Wxa+/gnoL5KShY43MsBmVSoD/OvLSPJWKtcODl0CN A==; X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="354759568" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="354759568" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="1032652189" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="1032652189" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 May 2023 08:49:43 -0700 Message-Id: <20230519154946.3751971-5-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> References: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 4/7] drm/i915/pmu: Transform PMU parking code to be GT based X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Trivial prep work for full multi-tile enablement later. Signed-off-by: Tvrtko Ursulin Signed-off-by: Vinay Belgaumkar Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++-- drivers/gpu/drm/i915/i915_pmu.c | 16 ++++++++-------- drivers/gpu/drm/i915/i915_pmu.h | 9 +++++---- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index e02cb90723ae..c2e69bafd02b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf) intel_rc6_unpark(>->rc6); intel_rps_unpark(>->rps); - i915_pmu_gt_unparked(i915); + i915_pmu_gt_unparked(gt); intel_guc_busyness_unpark(gt); intel_gt_unpark_requests(gt); @@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf) intel_guc_busyness_park(gt); i915_vma_parked(gt); - i915_pmu_gt_parked(i915); + i915_pmu_gt_parked(gt); intel_rps_park(>->rps); intel_rc6_park(>->rc6); diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 6d594f67f365..890693fdaf9e 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -228,11 +228,11 @@ static void init_rc6(struct i915_pmu *pmu) } } -static void park_rc6(struct drm_i915_private *i915) +static void park_rc6(struct intel_gt *gt) { - struct i915_pmu *pmu = &i915->pmu; + struct i915_pmu *pmu = >->i915->pmu; - pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915)); + pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt); pmu->sleep_last = ktime_get_raw(); } @@ -247,16 +247,16 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu) } } -void i915_pmu_gt_parked(struct drm_i915_private *i915) +void i915_pmu_gt_parked(struct intel_gt *gt) { - struct i915_pmu *pmu = &i915->pmu; + struct i915_pmu *pmu = >->i915->pmu; if (!pmu->base.event_init) return; spin_lock_irq(&pmu->lock); - park_rc6(i915); + park_rc6(gt); /* * Signal sampling timer to stop if only engine events are enabled and @@ -267,9 +267,9 @@ void i915_pmu_gt_parked(struct drm_i915_private *i915) spin_unlock_irq(&pmu->lock); } -void i915_pmu_gt_unparked(struct drm_i915_private *i915) +void i915_pmu_gt_unparked(struct intel_gt *gt) { - struct i915_pmu *pmu = &i915->pmu; + struct i915_pmu *pmu = >->i915->pmu; if (!pmu->base.event_init) return; diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index c30f43319a78..a686fd7ccedf 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -13,6 +13,7 @@ #include struct drm_i915_private; +struct intel_gt; /* * Non-engine events that we need to track enabled-disabled transition and @@ -151,15 +152,15 @@ int i915_pmu_init(void); void i915_pmu_exit(void); void i915_pmu_register(struct drm_i915_private *i915); void i915_pmu_unregister(struct drm_i915_private *i915); -void i915_pmu_gt_parked(struct drm_i915_private *i915); -void i915_pmu_gt_unparked(struct drm_i915_private *i915); +void i915_pmu_gt_parked(struct intel_gt *gt); +void i915_pmu_gt_unparked(struct intel_gt *gt); #else static inline int i915_pmu_init(void) { return 0; } static inline void i915_pmu_exit(void) {} static inline void i915_pmu_register(struct drm_i915_private *i915) {} static inline void i915_pmu_unregister(struct drm_i915_private *i915) {} -static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {} -static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {} +static inline void i915_pmu_gt_parked(struct intel_gt *gt) {} +static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {} #endif #endif From patchwork Fri May 19 15:49:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13248514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E617C7EE2E for ; Fri, 19 May 2023 15:50:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D943910E5B4; Fri, 19 May 2023 15:49:53 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4AAF210E55B for ; Fri, 19 May 2023 15:49:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684511389; x=1716047389; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=5foPLz3hX8+kvLpqF2fF0iQy+5fR4swqGym2SoYWqnQ=; b=Q3+4hB3KJivsVxgNZJTJ4eEkvKz27w/tWpBkmMOyilNfFBtuZ8kMdi6s 0T+1Ew5oy3teYWreqsWu+56IFGT6tj6WXpl3b8A8YZkRuzE4fcU7BBXVo B3iD3Llc2dJJMzvoTvt6TXtQzAceSt8YU+lxHXVerLR9Z8S0juH50RAaH agsftEQYTZmeQU014Od/QcLolEbXWmnxzmdO83VeJ0eME6ygBAt/ZUuaq vDIq2Stk36+KdbFa7HxPFMovzaxCwuQl2KiwqwDUi5QvQYb0pXwb5DP7n kpQUwTsA57vCuHyeSW9aSYDmh5S9OwyLfidAky8X6zXrVwMl++2F2VXpf g==; X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="354759569" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="354759569" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="1032652190" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="1032652190" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 May 2023 08:49:44 -0700 Message-Id: <20230519154946.3751971-6-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> References: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 5/7] drm/i915/pmu: Add reference counting to the sampling timer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin We do not want to have timers per tile and waste CPU cycles and energy via multiple wake-up sources, for a relatively un-important task of PMU sampling, so keeping a single timer works well. But we also do not want the first GT which goes idle to turn off the timer. Add some reference counting, via a mask of unparked GTs, to solve this. v2: Drop the check for unparked in i915_sample (Ashutosh) v3: Revert v2 (Tvrtko) Signed-off-by: Tvrtko Ursulin Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_pmu.c | 12 ++++++++++-- drivers/gpu/drm/i915/i915_pmu.h | 4 ++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 890693fdaf9e..ecb57a94143e 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -262,7 +262,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt) * Signal sampling timer to stop if only engine events are enabled and * GPU went idle. */ - pmu->timer_enabled = pmu_needs_timer(pmu, false); + pmu->unparked &= ~BIT(gt->info.id); + if (pmu->unparked == 0) + pmu->timer_enabled = pmu_needs_timer(pmu, false); spin_unlock_irq(&pmu->lock); } @@ -279,7 +281,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt) /* * Re-enable sampling timer when GPU goes active. */ - __i915_pmu_maybe_start_timer(pmu); + if (pmu->unparked == 0) + __i915_pmu_maybe_start_timer(pmu); + + pmu->unparked |= BIT(gt->info.id); spin_unlock_irq(&pmu->lock); } @@ -449,6 +454,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) */ for_each_gt(gt, i915, i) { + if (!(pmu->unparked & BIT(i))) + continue; + engines_sample(gt, period_ns); if (i == 0) /* FIXME */ diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index a686fd7ccedf..3a811266ac6a 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -76,6 +76,10 @@ struct i915_pmu { * @lock: Lock protecting enable mask and ref count handling. */ spinlock_t lock; + /** + * @unparked: GT unparked mask. + */ + unsigned int unparked; /** * @timer: Timer for internal i915 PMU sampling. */ From patchwork Fri May 19 15:49:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13248511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3004C7EE2A for ; Fri, 19 May 2023 15:49:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ED20210E5AD; Fri, 19 May 2023 15:49:51 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5CE6610E5A6 for ; Fri, 19 May 2023 15:49:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684511389; x=1716047389; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=RI+Y5t5q9yJ/Ejn6DvnpKgAdrS/PFMtRXNLrfDoazP8=; b=n6hD50DS7Esjzr/oSqYAwD+DJcc/0RUQlmQCtJTJJHGGMBUq+DE09d8q 41jn1WwwoBUp5ZMW1OgVWPm32hr40CY3+b5q2zaTsHdQLSrDDlBuXDdfE YzcyOYdcbUle7TDJ+8IRXElTiLcbWgAYew8j3y12pRikPZT9hqA9gC6KQ jq94/sf1vqrqdgBKbhoIAyD8PvSW+2nzfVzoDx4Slih5CF+QLovNrQcXR ychdXC1Oyq1t+w+fhBrW7Esf4M5BzuXW2A85rWN2Qv45Ok9CXDv5Ju8B9 WG/rwkiaUYBwNpQmId4L0+9mkCVSbz6Supo4qEGbHgzPjPv4nK4EUKFh6 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="354759571" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="354759571" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="1032652191" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="1032652191" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 May 2023 08:49:45 -0700 Message-Id: <20230519154946.3751971-7-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> References: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in non-engine counters. Drop FIXME. - Set MAX GTs to 4. Drop FIXME. v3: (Ashutosh, Tvrtko) - Drop BUG_ON that would never fire - Make enable u64 - Pull in some code from next patch v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko) v5: s/u64/u32 where needed (Ashutosh) Signed-off-by: Tvrtko Ursulin Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_pmu.c | 146 +++++++++++++++++++++++--------- drivers/gpu/drm/i915/i915_pmu.h | 9 +- include/uapi/drm/i915_drm.h | 17 +++- 3 files changed, 127 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index ecb57a94143e..5cfc322e69b4 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -56,11 +56,21 @@ static bool is_engine_config(const u64 config) return config < __I915_PMU_OTHER(0); } +static unsigned int config_gt_id(const u64 config) +{ + return config >> __I915_PMU_GT_SHIFT; +} + +static u64 config_counter(const u64 config) +{ + return config & ~(~0ULL << __I915_PMU_GT_SHIFT); +} + static unsigned int other_bit(const u64 config) { unsigned int val; - switch (config) { + switch (config_counter(config)) { case I915_PMU_ACTUAL_FREQUENCY: val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED; break; @@ -78,7 +88,9 @@ static unsigned int other_bit(const u64 config) return -1; } - return I915_ENGINE_SAMPLE_COUNT + val; + return I915_ENGINE_SAMPLE_COUNT + + config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT + + val; } static unsigned int config_bit(const u64 config) @@ -115,6 +127,18 @@ static unsigned int event_bit(struct perf_event *event) return config_bit(event->attr.config); } +static u32 frequency_enabled_mask(void) +{ + unsigned int i; + u32 mask = 0; + + for (i = 0; i < I915_PMU_MAX_GTS; i++) + mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) | + config_mask(__I915_PMU_REQUESTED_FREQUENCY(i)); + + return mask; +} + static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) { struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu); @@ -131,9 +155,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) * Mask out all the ones which do not need the timer, or in * other words keep all the ones that could need the timer. */ - enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) | - config_mask(I915_PMU_REQUESTED_FREQUENCY) | - ENGINE_SAMPLE_MASK; + enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK; /* * When the GPU is idle per-engine counters do not need to be @@ -175,9 +197,37 @@ static inline s64 ktime_since_raw(const ktime_t kt) return ktime_to_ns(ktime_sub(ktime_get_raw(), kt)); } +static unsigned int +__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample) +{ + unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample; + + GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample)); + + return idx; +} + +static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample) +{ + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur; +} + +static void +store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val) +{ + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val; +} + +static void +add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul) +{ + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val, mul); +} + static u64 get_rc6(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; + const unsigned int gt_id = gt->info.id; struct i915_pmu *pmu = &i915->pmu; unsigned long flags; bool awake = false; @@ -192,7 +242,7 @@ static u64 get_rc6(struct intel_gt *gt) spin_lock_irqsave(&pmu->lock, flags); if (awake) { - pmu->sample[__I915_SAMPLE_RC6].cur = val; + store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val); } else { /* * We think we are runtime suspended. @@ -201,14 +251,14 @@ static u64 get_rc6(struct intel_gt *gt) * on top of the last known real value, as the approximated RC6 * counter value. */ - val = ktime_since_raw(pmu->sleep_last); - val += pmu->sample[__I915_SAMPLE_RC6].cur; + val = ktime_since_raw(pmu->sleep_last[gt_id]); + val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6); } - if (val < pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur) - val = pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur; + if (val < read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED)) + val = read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED); else - pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = val; + store_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED, val); spin_unlock_irqrestore(&pmu->lock, flags); @@ -218,13 +268,20 @@ static u64 get_rc6(struct intel_gt *gt) static void init_rc6(struct i915_pmu *pmu) { struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu); - intel_wakeref_t wakeref; + struct intel_gt *gt; + unsigned int i; + + for_each_gt(gt, i915, i) { + intel_wakeref_t wakeref; + + with_intel_runtime_pm(gt->uncore->rpm, wakeref) { + u64 val = __get_rc6(gt); - with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref) { - pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915)); - pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = - pmu->sample[__I915_SAMPLE_RC6].cur; - pmu->sleep_last = ktime_get_raw(); + store_sample(pmu, i, __I915_SAMPLE_RC6, val); + store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED, + val); + pmu->sleep_last[i] = ktime_get_raw(); + } } } @@ -232,8 +289,8 @@ static void park_rc6(struct intel_gt *gt) { struct i915_pmu *pmu = >->i915->pmu; - pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt); - pmu->sleep_last = ktime_get_raw(); + store_sample(pmu, gt->info.id, __I915_SAMPLE_RC6, __get_rc6(gt)); + pmu->sleep_last[gt->info.id] = ktime_get_raw(); } static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu) @@ -373,34 +430,30 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) } } -static void -add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul) -{ - sample->cur += mul_u32_u32(val, mul); -} - -static bool frequency_sampling_enabled(struct i915_pmu *pmu) +static bool +frequency_sampling_enabled(struct i915_pmu *pmu, unsigned int gt) { return pmu->enable & - (config_mask(I915_PMU_ACTUAL_FREQUENCY) | - config_mask(I915_PMU_REQUESTED_FREQUENCY)); + (config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt)) | + config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt))); } static void frequency_sample(struct intel_gt *gt, unsigned int period_ns) { struct drm_i915_private *i915 = gt->i915; + const unsigned int gt_id = gt->info.id; struct i915_pmu *pmu = &i915->pmu; struct intel_rps *rps = >->rps; - if (!frequency_sampling_enabled(pmu)) + if (!frequency_sampling_enabled(pmu, gt_id)) return; /* Report 0/0 (actual/requested) frequency while parked. */ if (!intel_gt_pm_get_if_awake(gt)) return; - if (pmu->enable & config_mask(I915_PMU_ACTUAL_FREQUENCY)) { + if (pmu->enable & config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt_id))) { u32 val; /* @@ -416,12 +469,12 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) if (!val) val = intel_gpu_freq(rps, rps->cur_freq); - add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT], + add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_ACT, val, period_ns / 1000); } - if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) { - add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ], + if (pmu->enable & config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt_id))) { + add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_REQ, intel_rps_get_requested_frequency(rps), period_ns / 1000); } @@ -458,9 +511,7 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer) continue; engines_sample(gt, period_ns); - - if (i == 0) /* FIXME */ - frequency_sample(gt, period_ns); + frequency_sample(gt, period_ns); } hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD)); @@ -502,7 +553,13 @@ config_status(struct drm_i915_private *i915, u64 config) { struct intel_gt *gt = to_gt(i915); - switch (config) { + unsigned int gt_id = config_gt_id(config); + unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0; + + if (gt_id > max_gt_id) + return -ENOENT; + + switch (config_counter(config)) { case I915_PMU_ACTUAL_FREQUENCY: if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) /* Requires a mutex for sampling! */ @@ -513,6 +570,8 @@ config_status(struct drm_i915_private *i915, u64 config) return -ENODEV; break; case I915_PMU_INTERRUPTS: + if (gt_id) + return -ENOENT; break; case I915_PMU_RC6_RESIDENCY: if (!gt->rc6.supported) @@ -610,22 +669,27 @@ static u64 __i915_pmu_event_read(struct perf_event *event) val = engine->pmu.sample[sample].cur; } } else { - switch (event->attr.config) { + const unsigned int gt_id = config_gt_id(event->attr.config); + const u64 config = config_counter(event->attr.config); + + switch (config) { case I915_PMU_ACTUAL_FREQUENCY: val = - div_u64(pmu->sample[__I915_SAMPLE_FREQ_ACT].cur, + div_u64(read_sample(pmu, gt_id, + __I915_SAMPLE_FREQ_ACT), USEC_PER_SEC /* to MHz */); break; case I915_PMU_REQUESTED_FREQUENCY: val = - div_u64(pmu->sample[__I915_SAMPLE_FREQ_REQ].cur, + div_u64(read_sample(pmu, gt_id, + __I915_SAMPLE_FREQ_REQ), USEC_PER_SEC /* to MHz */); break; case I915_PMU_INTERRUPTS: val = READ_ONCE(pmu->irq_count); break; case I915_PMU_RC6_RESIDENCY: - val = get_rc6(to_gt(i915)); + val = get_rc6(i915->gt[gt_id]); break; case I915_PMU_SOFTWARE_GT_AWAKE_TIME: val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915))); diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index 3a811266ac6a..33d80fbaab8b 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -38,13 +38,16 @@ enum { __I915_NUM_PMU_SAMPLERS }; +#define I915_PMU_MAX_GTS 2 + /* * How many different events we track in the global PMU mask. * * It is also used to know to needed number of event reference counters. */ #define I915_PMU_MASK_BITS \ - (I915_ENGINE_SAMPLE_COUNT + __I915_PMU_TRACKED_EVENT_COUNT) + (I915_ENGINE_SAMPLE_COUNT + \ + I915_PMU_MAX_GTS * __I915_PMU_TRACKED_EVENT_COUNT) #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1) @@ -124,11 +127,11 @@ struct i915_pmu { * Only global counters are held here, while the per-engine ones are in * struct intel_engine_cs. */ - struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS]; + struct i915_pmu_sample sample[I915_PMU_MAX_GTS * __I915_NUM_PMU_SAMPLERS]; /** * @sleep_last: Last time GT parked for RC6 estimation. */ - ktime_t sleep_last; + ktime_t sleep_last[I915_PMU_MAX_GTS]; /** * @irq_count: Number of interrupts * diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index ba40855dbc93..f31dfacde601 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -280,7 +280,16 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ENGINE_SEMA(class, instance) \ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) -#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) +/* + * Top 4 bits of every non-engine counter are GT id. + */ +#define __I915_PMU_GT_SHIFT (60) + +#define ___I915_PMU_OTHER(gt, x) \ + (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \ + ((__u64)(gt) << __I915_PMU_GT_SHIFT)) + +#define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x) #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) @@ -290,6 +299,12 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY +#define __I915_PMU_ACTUAL_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 0) +#define __I915_PMU_REQUESTED_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 1) +#define __I915_PMU_INTERRUPTS(gt) ___I915_PMU_OTHER(gt, 2) +#define __I915_PMU_RC6_RESIDENCY(gt) ___I915_PMU_OTHER(gt, 3) +#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___I915_PMU_OTHER(gt, 4) + /* Each region is a minimum of 16k, and there are at most 255 of them. */ #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use From patchwork Fri May 19 15:49:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 13248510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC8ECC77B7F for ; Fri, 19 May 2023 15:49:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E081B10E5A6; Fri, 19 May 2023 15:49:51 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7327C10E5AD for ; Fri, 19 May 2023 15:49:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684511389; x=1716047389; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=8U1+FsY5FvqvzgyahiY3ZoI/CgZVyUI7OJzjnWt+rbA=; b=TCf9sUBm1o41iXjur49Cs65HCcv/m/tXx3ZrdFyQjQNkD3Rqi/wY7KON NnQEYBtVK/eieic6RJGAbxHl7DMbIFpWV1KLZDFzjAbET543ZG5aAli0Z y8VibGLm/mg3PNFGFoJP4STLzGixjsr8eWiH/nmXmklkSbr3y+drbBE3H JoYbA7FQf7Vf5IJQP+/g8FE/mTBjWQQmocJsTahdOP1nVE2Aty+tcX6eH /7MyzeTBIcu2dHvtvQvcGUF/80YhKRI6NQTmJsDG62P9kc6Lo4N+xT5AA 1NeL7LsZp96fSB4hX7HZ5Y2+ISIbGcbdr2VV/S7mkXDxCVeOSp+CqOP7f g==; X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="354759572" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="354759572" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10715"; a="1032652192" X-IronPort-AV: E=Sophos;i="6.00,177,1681196400"; d="scan'208";a="1032652192" Received: from orsosgc001.jf.intel.com ([10.165.21.138]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 08:49:47 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 May 2023 08:49:46 -0700 Message-Id: <20230519154946.3751971-8-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> References: <20230519154946.3751971-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7 7/7] drm/i915/pmu: Export counters from all tiles X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin Start exporting frequency and RC6 counters from all tiles. Existing counters keep their names and config values and new one use the namespace added in the previous patch, with the "-gtN" added to their names. Interrupts counter is an odd one off. Because it is the global device counters (not only GT) we choose not to add per tile versions for now. Signed-off-by: Tvrtko Ursulin Signed-off-by: Aravind Iddamsetty Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 82 ++++++++++++++++++++++----------- 1 file changed, 55 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 5cfc322e69b4..a814583e19fd 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -940,11 +940,20 @@ static const struct attribute_group i915_pmu_cpumask_attr_group = { .attrs = i915_cpumask_attrs, }; -#define __event(__config, __name, __unit) \ +#define __event(__counter, __name, __unit) \ { \ - .config = (__config), \ + .counter = (__counter), \ .name = (__name), \ .unit = (__unit), \ + .global = false, \ +} + +#define __global_event(__counter, __name, __unit) \ +{ \ + .counter = (__counter), \ + .name = (__name), \ + .unit = (__unit), \ + .global = true, \ } #define __engine_event(__sample, __name) \ @@ -983,15 +992,16 @@ create_event_attributes(struct i915_pmu *pmu) { struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu); static const struct { - u64 config; + unsigned int counter; const char *name; const char *unit; + bool global; } events[] = { - __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"), - __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"), - __event(I915_PMU_INTERRUPTS, "interrupts", NULL), - __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"), - __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME, "software-gt-awake-time", "ns"), + __event(0, "actual-frequency", "M"), + __event(1, "requested-frequency", "M"), + __global_event(2, "interrupts", NULL), + __event(3, "rc6-residency", "ns"), + __event(4, "software-gt-awake-time", "ns"), }; static const struct { enum drm_i915_pmu_engine_sample sample; @@ -1006,12 +1016,17 @@ create_event_attributes(struct i915_pmu *pmu) struct i915_ext_attribute *i915_attr = NULL, *i915_iter; struct attribute **attr = NULL, **attr_iter; struct intel_engine_cs *engine; - unsigned int i; + struct intel_gt *gt; + unsigned int i, j; /* Count how many counters we will be exposing. */ - for (i = 0; i < ARRAY_SIZE(events); i++) { - if (!config_status(i915, events[i].config)) - count++; + for_each_gt(gt, i915, j) { + for (i = 0; i < ARRAY_SIZE(events); i++) { + u64 config = ___I915_PMU_OTHER(j, events[i].counter); + + if (!config_status(i915, config)) + count++; + } } for_each_uabi_engine(engine, i915) { @@ -1041,26 +1056,39 @@ create_event_attributes(struct i915_pmu *pmu) attr_iter = attr; /* Initialize supported non-engine counters. */ - for (i = 0; i < ARRAY_SIZE(events); i++) { - char *str; - - if (config_status(i915, events[i].config)) - continue; - - str = kstrdup(events[i].name, GFP_KERNEL); - if (!str) - goto err; + for_each_gt(gt, i915, j) { + for (i = 0; i < ARRAY_SIZE(events); i++) { + u64 config = ___I915_PMU_OTHER(j, events[i].counter); + char *str; - *attr_iter++ = &i915_iter->attr.attr; - i915_iter = add_i915_attr(i915_iter, str, events[i].config); + if (config_status(i915, config)) + continue; - if (events[i].unit) { - str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name); + if (events[i].global || !HAS_EXTRA_GT_LIST(i915)) + str = kstrdup(events[i].name, GFP_KERNEL); + else + str = kasprintf(GFP_KERNEL, "%s-gt%u", + events[i].name, j); if (!str) goto err; - *attr_iter++ = &pmu_iter->attr.attr; - pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit); + *attr_iter++ = &i915_iter->attr.attr; + i915_iter = add_i915_attr(i915_iter, str, config); + + if (events[i].unit) { + if (events[i].global || !HAS_EXTRA_GT_LIST(i915)) + str = kasprintf(GFP_KERNEL, "%s.unit", + events[i].name); + else + str = kasprintf(GFP_KERNEL, "%s-gt%u.unit", + events[i].name, j); + if (!str) + goto err; + + *attr_iter++ = &pmu_iter->attr.attr; + pmu_iter = add_pmu_attr(pmu_iter, str, + events[i].unit); + } } }