From patchwork Tue May 23 06:15:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13251545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17A74C7EE2E for ; Tue, 23 May 2023 06:15:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235100AbjEWGPj (ORCPT ); Tue, 23 May 2023 02:15:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235079AbjEWGPh (ORCPT ); Tue, 23 May 2023 02:15:37 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D181119; Mon, 22 May 2023 23:15:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1684822535; x=1716358535; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gzSWfAKPB5qBX1sE5pYvWf6PLtnvJPojqONIqDbzLR4=; b=lzyN5dVPw4tp2vdKeILHfhL+gzEzbMucG21RvuRxGEmf250jCH82wBo+ eRieDDpKxT85lqcMVKQUX8kXytaewonfb9mFZ1ZR+oJP8ALYXPe/kl7B4 jMjyJ2VNQEomKA98FsvKf75PPh0M8RabhrjQKTcfZ2Z9wy5jg4fX8RGnp Sm630V/3yYGyc/UZBBv4p96KMTnbehidmmbk3cv0e71VcYrp7LLFOivs/ 8TDRqFsfzIYNroeIoHbWc7Y6SlD/5m7VmjVFnRZN9CaB15M74FDABhzvS PLgdsAbaRGKUKNCYzzasYIde4pjsQfP/2aNvY7piH1Oz0UVZLPn5WNdnF w==; X-IronPort-AV: E=Sophos;i="6.00,185,1681196400"; d="scan'208";a="153433852" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 May 2023 23:15:34 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 22 May 2023 23:15:30 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 22 May 2023 23:15:27 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 1/4] ARM: dts: at91: use generic name for shutdown controller Date: Tue, 23 May 2023 09:15:09 +0300 Message-ID: <20230523061512.195271-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523061512.195271-1-claudiu.beznea@microchip.com> References: <20230523061512.195271-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Use poweroff generic name for shdwc node to cope with device tree specifications. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-qil_a9260.dts | 2 +- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 2 +- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 +- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 2 +- arch/arm/boot/dts/at91sam9260.dtsi | 2 +- arch/arm/boot/dts/at91sam9260ek.dts | 2 +- arch/arm/boot/dts/at91sam9261.dtsi | 2 +- arch/arm/boot/dts/at91sam9263.dtsi | 2 +- arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 2 +- arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- arch/arm/boot/dts/sam9x60.dtsi | 2 +- arch/arm/boot/dts/sama5d2.dtsi | 2 +- arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- arch/arm/boot/dts/sama7g5.dtsi | 2 +- arch/arm/boot/dts/usb_a9260.dts | 2 +- arch/arm/boot/dts/usb_a9263.dts | 2 +- 20 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 9d26f9996348..5ccb3c139592 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -108,7 +108,7 @@ dbgu: serial@fffff200 { status = "okay"; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 0dc6ca377b0c..cb6243cfe182 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -139,7 +139,7 @@ i2c3: i2c@600 { }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; atmel,wakeup-rtc-timer; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 76a711b167b0..86b860d80726 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -204,7 +204,7 @@ i2c2: i2c@600 { }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; input@0 { diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 85949c24b687..024a553842a9 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -348,7 +348,7 @@ i2c2: i2c@600 { }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; atmel,wakeup-rtc-timer; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 16e3b24b4ddd..35a007365b6a 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -130,7 +130,7 @@ reset-controller@fffffd00 { clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index bb72f050a4fe..720c15472c4a 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -112,7 +112,7 @@ pinctrl_board_mmc0_slot1: mmc0_slot1-board { }; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index fe9ead867e2a..528ffc6f6f96 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -614,7 +614,7 @@ reset-controller@fffffd00 { clocks = <&slow_xtal>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index ee5e6ed44dd4..75d8ff2d12c8 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -158,7 +158,7 @@ reset-controller@fffffd00 { clocks = <&slow_xtal>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 024af2db638e..565b99e79c52 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -126,7 +126,7 @@ flash@1 { }; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 498cb92b29f9..7cccc606e36c 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -152,7 +152,7 @@ pit: timer@fffffd30 { }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9rl-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0e28101b26bf..8dc04e9031a6 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -140,7 +140,7 @@ pit: timer@fffffe30 { clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; - shdwc@fffffe10 { + poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index d7e8a115c916..3d089ffbe162 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -778,7 +778,7 @@ reset-controller@fffffd00 { clocks = <&clk32k>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 0123ee47151c..a1fed912f2ee 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -141,7 +141,7 @@ reset_controller: reset-controller@fffffe00 { clocks = <&clk32k>; }; - shutdown_controller: shdwc@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 933d73505a8b..47c4f267a45c 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -675,7 +675,7 @@ reset_controller: reset-controller@fffffe00 { clocks = <&clk32k 0>; }; - shutdown_controller: shdwc@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "microchip,sam9x60-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 7b6471655dee..daeeb24e5f4d 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -680,7 +680,7 @@ reset_controller: reset-controller@f8048000 { clocks = <&clk32k>; }; - shutdown_controller: shdwc@f8048010 { + shutdown_controller: poweroff@f8048010 { compatible = "atmel,sama5d2-shdwc"; reg = <0xf8048010 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 0eebf6c760b3..d9e66700d1c2 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1016,7 +1016,7 @@ reset_controller: reset-controller@fffffe00 { clocks = <&clk32k>; }; - shutdown_controller: shutdown-controller@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index de6c82969232..41284e013f53 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -740,7 +740,7 @@ reset_controller: reset-controller@fc068600 { clocks = <&clk32k>; }; - shutdown_controller: shdwc@fc068610 { + shutdown_controller: poweroff@fc068610 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfc068610 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index f0478a43edc2..886b6209a71e 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -257,7 +257,7 @@ reset_controller: reset-controller@e001d000 { clocks = <&clk32k 0>; }; - shdwc: shdwc@e001d010 { + shdwc: poweroff@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts index 6cfa83921ac2..66f8da89007d 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/usb_a9260.dts @@ -22,7 +22,7 @@ memory@20000000 { ahb { apb { - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index b6cb9cdf8197..45745915b2e1 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -67,7 +67,7 @@ flash@0 { }; }; - shdwc@fffffd10 { + poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; From patchwork Tue May 23 06:15:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13251544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAD10C77B7A for ; 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X-IronPort-AV: E=Sophos;i="6.00,185,1681196400"; d="scan'208";a="153433853" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 May 2023 23:15:34 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 22 May 2023 23:15:33 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 22 May 2023 23:15:30 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 2/4] dt-bindings: power: reset: atmel,at91sam9260-shdwc: convert to yaml Date: Tue, 23 May 2023 09:15:10 +0300 Message-ID: <20230523061512.195271-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523061512.195271-1-claudiu.beznea@microchip.com> References: <20230523061512.195271-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Convert Atmel shutdown controller to YAML. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 31 ------- .../power/reset/atmel,at91sam9260-shdwc.yaml | 81 +++++++++++++++++++ 2 files changed, 81 insertions(+), 31 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/reset/atmel,at91sam9260-shdwc.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index ab1b352344ae..e6b2fb291b45 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -52,37 +52,6 @@ Example: reg = <0xe3804000 0x1000>; }; -SHDWC Shutdown Controller - -required properties: -- compatible: Should be "atmel,-shdwc". - can be "at91sam9260", "at91sam9rl" or "at91sam9x5". -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -optional properties: -- atmel,wakeup-mode: String, operation mode of the wakeup mode. - Supported values are: "none", "high", "low", "any". -- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). - -optional at91sam9260 properties: -- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. - -optional at91sam9rl properties: -- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. -- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. - -optional at91sam9x5 properties: -- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. - -Example: - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - SHDWC SAMA5D2-Compatible Shutdown Controller 1) shdwc node diff --git a/Documentation/devicetree/bindings/power/reset/atmel,at91sam9260-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,at91sam9260-shdwc.yaml new file mode 100644 index 000000000000..3b3162677db3 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/atmel,at91sam9260-shdwc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/atmel,at91sam9260-shdwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel SHDWC Shutdown Controller + +maintainers: + - Claudiu Beznea + +description: | + Atmel SHDWC shutdown controller controls the power supplies VDDIO and VDDCORE + and the wake-up detection on debounced input lines. + +properties: + compatible: + enum: + - atmel,at91sam9260-shdwc + - atmel,at91sam9rl-shdwc + - atmel,at91sam9x5-shdwc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + atmel,wakeup-mode: + description: operation mode of the wakeup mode + $ref: /schemas/types.yaml#/definitions/string + enum: [ none, high, low, any ] + + atmel,wakeup-counter: + description: counter on wake-up 0 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ] + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + enum: + - atmel,at91sam9260-shdwc + - atmel,at91sam9rl-shdwc + then: + properties: + atmel,wakeup-rtt-timer: + description: enable real-time timer wake-up + type: boolean + + - if: + properties: + compatible: + contains: + enum: + - atmel,at91sam9rl-shdwc + - atmel,at91sam9x5-shdwc + then: + properties: + atmel,wakeup-rtc-timer: + description: enable real-time clock wake-up + type: boolean + +unevaluatedProperties: false + +examples: + - | + shdwc: poweroff@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; + }; + +... From patchwork Tue May 23 06:15:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13251546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B27B2C7EE23 for ; Tue, 23 May 2023 06:15:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235105AbjEWGPn (ORCPT ); Tue, 23 May 2023 02:15:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235095AbjEWGPl (ORCPT ); Tue, 23 May 2023 02:15:41 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 706D3129; Mon, 22 May 2023 23:15:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1684822540; x=1716358540; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B6ogvYvBGrrc5/DBPkLgD1u82vMdLt29VA39gaBblow=; b=Tf/pkXjyd/dXMwutCC4Bw83hd0k7htUcWxP5/L3U4wCpSsbN51s6JxCa 32HegZgwWvsY2OtVvx7sSws5UQvAkk+KAwPIrYNTkW8FSMGZKruKjbh9n VZvBR2JKZgqf/3N4+iSQ/LlaE31Q7X3CTbZ/Onm/0ahU4U2zUt9SIsn+t 54uyPLGEEFXH9rUYPkE+9wri/tlaULg9nrWEprjosQlSEVBuwVnqEjzL9 28hhrKkGW9yShqw0dBr10V2EE/WupUX/pZfxouXlpVCawUS8UtCX77Bvx 4acSbf3wGJ+CQPaKf8WHpu0TmwG1/prbsC5q3Lo+PbuqLDNoHE0IhtVM7 A==; X-IronPort-AV: E=Sophos;i="6.00,185,1681196400"; d="scan'208";a="226538541" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 May 2023 23:15:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 22 May 2023 23:15:38 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 22 May 2023 23:15:34 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 3/4] dt-bindings: power: reset: atmel,sama5d2-shdwc: convert to yaml Date: Tue, 23 May 2023 09:15:11 +0300 Message-ID: <20230523061512.195271-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523061512.195271-1-claudiu.beznea@microchip.com> References: <20230523061512.195271-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Convert Atmel SAMA5D2 shutdown controller to YAML. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 63 ---------- .../power/reset/atmel,sama5d2-shdwc.yaml | 114 ++++++++++++++++++ 2 files changed, 114 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index e6b2fb291b45..67a66bf74895 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -52,69 +52,6 @@ Example: reg = <0xe3804000 0x1000>; }; -SHDWC SAMA5D2-Compatible Shutdown Controller - -1) shdwc node - -required properties: -- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or - "microchip,sama7g5-shdwc" -- reg: should contain registers location and length -- clocks: phandle to input clock. -- #address-cells: should be one. The cell is the wake-up input index. -- #size-cells: should be zero. - -optional properties: - -- debounce-delay-us: minimum wake-up inputs debouncer period in - microseconds. It's usually a board-related property. -- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. - -optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: -- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. - -The node contains child nodes for each wake-up input that the platform uses. - -2) input nodes - -Wake-up input nodes are usually described in the "board" part of the Device -Tree. Note also that input 0 is linked to the wake-up pin and is frequently -used. - -Required properties: -- reg: should contain the wake-up input index [0 - 15]. - -Optional properties: -- atmel,wakeup-active-high: boolean, the corresponding wake-up input described - by the child, forces the wake-up of the core power supply on a high level. - The default is to be active low. - -Example: - -On the SoC side: - shdwc@f8048010 { - compatible = "atmel,sama5d2-shdwc"; - reg = <0xf8048010 0x10>; - clocks = <&clk32k>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - }; - -On the board side: - shdwc@f8048010 { - debounce-delay-us = <976>; - - input@0 { - reg = <0>; - }; - - input@1 { - reg = <1>; - atmel,wakeup-active-high; - }; - }; - Special Function Registers (SFR) Special Function Registers (SFR) manage specific aspects of the integrated diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml new file mode 100644 index 000000000000..613668d6099b --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/atmel,sama5d2-shdwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel SAMA5D2 SHDWC Shutdown Controller + +maintainers: + - Claudiu Beznea + +description: | + Atmel SHDWC shutdown controller controls the power supplies VDDIO and VDDCORE + and the wake-up detection on debounced input lines. + +properties: + compatible: + oneOf: + - items: + - const: microchip,sama7g5-shdwc + - const: syscon + - items: + enum: + - atmel,sama5d2-shdwc + - microchip,sam9x60-shdwc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + debounce-delay-us: + description: | + Minimum wake-up inputs debouncer period in microseconds. It is usually a + board-related property. + + atmel,wakeup-rtc-timer: + description: enable real-time clock wake-up + type: boolean + +patternProperties: + "^input@[0-15]$": + description: | + Wake-up input nodes. These are usually described in the "board" part of + the Device Tree. Note also that input 0 is linked to the wake-up pin and + is frequently used. + type: object + properties: + reg: + description: contains the wake-up input index + enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ] + + atmel,wakeup-active-high: + description: | + The corresponding wake-up input described by the child forces the + wake-up of the core power supply on a high level. The default is to + be active low. + type: boolean + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sam9x60-shdwc + - microchip,sama7g5-shdwc + then: + properties: + atmel,wakeup-rtt-timer: + description: enable real-time timer wake-up + type: boolean + +unevaluatedProperties: false + +examples: + - | + shdwc: poweroff@f8048010 { + compatible = "atmel,sama5d2-shdwc"; + reg = <0xf8048010 0x10>; + clocks = <&clk32k>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + debounce-delay-us = <976>; + + input@0 { + reg = <0>; + }; + + input@1 { + reg = <1>; + atmel,wakeup-active-high; + }; + }; + +... From patchwork Tue May 23 06:15:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13251547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D46C7EE2D for ; Tue, 23 May 2023 06:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235154AbjEWGP7 (ORCPT ); Tue, 23 May 2023 02:15:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234680AbjEWGPo (ORCPT ); Tue, 23 May 2023 02:15:44 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FE3C11A; Mon, 22 May 2023 23:15:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1684822542; x=1716358542; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hX0vBHxCDkOd3pRwjtiOcZRwcusvy0J39jQkffoEfYY=; b=mPZxDhFrHh+aHeFirY08Bp9pC0HZxJ/c9Xw4APPnDH+Bi9zpV23cLX3Z ORTEXpWT2N6bD/jKJAPXYneUSDaOTBvNjAI02NInehh3Ho+6+schuoRP9 o2PfXmQiCIDTNerfzvZfWIHd+6/oEyO44LgNpm3DNgtbZ8gwYGGxt+1u7 u7yeRmyLnF5foC5K7tywqy4p+DeFUTtHAS8AJzpd5oCy2ehy6O44bXevo 30gadZ+0j89YXro4QMjncCLpJDjb7qZkOHf3txxberCkBoFHmNRSiA+jR tQrtI62ucoQ8cIW3WHiEj+pmPhArE3DaVsY1SYKyhbBvoHqXY9ylf59F4 g==; X-IronPort-AV: E=Sophos;i="6.00,185,1681196400"; d="scan'208";a="153433884" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 May 2023 23:15:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 22 May 2023 23:15:42 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 22 May 2023 23:15:38 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 4/4] MAINTAINERS: add documentation file for Microchip SAMA5D2 shutdown controller Date: Tue, 23 May 2023 09:15:12 +0300 Message-ID: <20230523061512.195271-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523061512.195271-1-claudiu.beznea@microchip.com> References: <20230523061512.195271-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add documentation file for SAMA5D2 shutdown controller. Signed-off-by: Claudiu Beznea --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 74a6b6b13d84..cdf4b41cf62b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13811,6 +13811,7 @@ F: include/dt-bindings/iio/adc/at91-sama5d2_adc.h MICROCHIP SAMA5D2-COMPATIBLE SHUTDOWN CONTROLLER M: Claudiu Beznea S: Supported +F: Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml F: drivers/power/reset/at91-sama5d2_shdwc.c MICROCHIP SPI DRIVER