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Thu, 25 May 2023 09:54:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT094.mail.protection.outlook.com (10.13.176.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.32 via Frontend Transport; Thu, 25 May 2023 09:54:42 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 25 May 2023 04:54:41 -0500 From: Nava kishore Manne To: , , , , , , Subject: [RFC PATCH] fpga: fpga-bridge: Add manual set option via sysfs Date: Thu, 25 May 2023 15:24:38 +0530 Message-ID: <20230525095438.2766625-1-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT094:EE_|PH7PR12MB9201:EE_ X-MS-Office365-Filtering-Correlation-Id: b82dac1e-0163-4e4f-9ba5-08db5d060ffc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2023 09:54:42.1988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b82dac1e-0163-4e4f-9ba5-08db5d060ffc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT094.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9201 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch is intended for manual testing only. It is provide an option to manually test bridges. Enabling bridge (!0 values are handled) br1# echo 1 > /sys/class/fpga_bridge//set Disable bridge br1# echo 0 > /sys/class/fpga_bridge//set Signed-off-by: Nava kishore Manne --- .../ABI/testing/sysfs-class-fpga-bridge | 9 ++++++ drivers/fpga/fpga-bridge.c | 30 +++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-class-fpga-bridge b/Documentation/ABI/testing/sysfs-class-fpga-bridge index 312ae2c579d8..e157eb737bfb 100644 --- a/Documentation/ABI/testing/sysfs-class-fpga-bridge +++ b/Documentation/ABI/testing/sysfs-class-fpga-bridge @@ -9,3 +9,12 @@ Date: January 2016 KernelVersion: 4.5 Contact: Alan Tull Description: Show bridge state as "enabled" or "disabled" + +What: /sys/class/fpga_bridge//set +Date: May 2023 +KernelVersion: 6.4 +Contact: Nava kishore Manne +Description: Manual set bridge state (0-disable, !0 enable). + Enabling this option requires that the module is + compiled with #define DEBUG which is enabled by default + when CONFIG_DEBUG_KERNEL is setup. diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c index a6c25dee9cc1..54d15b709b10 100644 --- a/drivers/fpga/fpga-bridge.c +++ b/drivers/fpga/fpga-bridge.c @@ -13,6 +13,12 @@ #include #include +/* For enabling manual bridge set(enable/disable) function */ +#ifdef CONFIG_DEBUG_KERNEL +#undef DEBUG +#define DEBUG +#endif + static DEFINE_IDA(fpga_bridge_ida); static struct class *fpga_bridge_class; @@ -307,9 +313,33 @@ static ssize_t state_show(struct device *dev, static DEVICE_ATTR_RO(name); static DEVICE_ATTR_RO(state); +#ifdef DEBUG +static ssize_t set_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fpga_bridge *bridge = to_fpga_bridge(dev); + long enable; + int ret; + + ret = kstrtol(buf, 16, &enable); + if (ret) + return ret; + + if (bridge->br_ops && bridge->br_ops->enable_set) + enable = bridge->br_ops->enable_set(bridge, !!enable); + + return count; +} +static DEVICE_ATTR_WO(set); +#endif + static struct attribute *fpga_bridge_attrs[] = { &dev_attr_name.attr, &dev_attr_state.attr, +#ifdef DEBUG + &dev_attr_set.attr, +#endif NULL, }; ATTRIBUTE_GROUPS(fpga_bridge);