From patchwork Sat May 27 04:02:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13257535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6DCBC77B73 for ; Sat, 27 May 2023 04:04:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231563AbjE0EEg (ORCPT ); Sat, 27 May 2023 00:04:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbjE0EEc (ORCPT ); Sat, 27 May 2023 00:04:32 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5943AD7 for ; Fri, 26 May 2023 21:04:31 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-5657f376d8dso35568987b3.2 for ; Fri, 26 May 2023 21:04:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685160270; x=1687752270; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=YHzsFiaji3R6LFuYZV3olh4p0y72F3S93sl+y+EJDgg=; b=tXRV7/8vaXCBmNvtRzMV0UTHrROqViarCwmmvALY8aLcpKOu4xRm91QNaRI34zQ8v8 yvLYZ1GU58l5FB/cjDoO40R/Z9cSiIJqqRZNSNv4nT8eeNOM9sC/MTkqBlahXlSb6FOb YEz1zKPvzwS09qQoUfpVwwChYweXdNma7oX+Su9R3sb4Apr9TGtS1UBKzdIVs4NTCGyY efKwRDyUP4EN4C9cvir8Cel8fAQPgCtt3xAF7dx0txEhPQARq6ttu0gHmWMud3io/OYo NtwEmzBt55fsPBQMr0neMCUGj7Kuyq78I2B4S7IX5XU/3LtYh0XQ4L7d7gXjDRmn9kz5 teGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685160270; x=1687752270; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YHzsFiaji3R6LFuYZV3olh4p0y72F3S93sl+y+EJDgg=; b=TvpYwCEsH9XN0M9h3PDSp6iXhU2QCmPQWxIUtRYXykrMU3gpVfFCyZ2hfxZEIVz1UJ ts1M+pjJ/sCWoH3a87iSxbnI1eiXO5jJF2BSEWLJp8pDLVMwQ+HeVTIcaRpFJ9WpY400 FJNq822+hCvVQ/pzBqab02hpRvqkZ6Ing5dl6hrF6ZWwysZaJJZZYKt0gQrjsvKJ2Orr RCw8DzuSLccc45TyW+ha9AIs3xsPT464QliN6N5iOGz3ni08yKcWsae55VDaGQ8dv3/Z Cxk/rewNWMhspJQ9NJFORST3jxZUuXzzKkhdUFe8vly2mS5aDccp4yZ9lWyFC1Q5iHAA ectw== X-Gm-Message-State: AC+VfDyzwHMGSNfHOoHZXV9jiTGq3egGO9kxaoKFiMhmNBYqXtsYhtGh aeWgOY7UyN9SaXYhIfZLqLl3UFwvS0I= X-Google-Smtp-Source: ACHHUZ4VFYAdIHLqeJ14za1MxIqkvJrkGV6Yf1oNFWGOG8pJc58iQwSXrcfI0IoqFC+oVQuwesnB8fXEw+Y= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a81:b71d:0:b0:55a:3133:86fa with SMTP id v29-20020a81b71d000000b0055a313386famr2380185ywh.3.1685160270657; Fri, 26 May 2023 21:04:30 -0700 (PDT) Date: Fri, 26 May 2023 21:02:33 -0700 In-Reply-To: <20230527040236.1875860-1-reijiw@google.com> Mime-Version: 1.0 References: <20230527040236.1875860-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230527040236.1875860-2-reijiw@google.com> Subject: [PATCH 1/4] KVM: arm64: PMU: Introduce a helper to set the guest's PMU From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Will Deacon , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce a new helper function to set the guest's PMU (kvm->arch.arm_pmu), and use it when the guest's PMU needs to be set. This helper will make it easier for the following patches to modify the relevant code. No functional change intended. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/pmu-emul.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 45727d50d18d..d50c8f7a2410 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -869,6 +869,21 @@ static bool pmu_irq_is_valid(struct kvm *kvm, int irq) return true; } +static int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) +{ + lockdep_assert_held(&kvm->arch.config_lock); + + if (!arm_pmu) { + arm_pmu = kvm_pmu_probe_armpmu(); + if (!arm_pmu) + return -ENODEV; + } + + kvm->arch.arm_pmu = arm_pmu; + + return 0; +} + static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *vcpu, int pmu_id) { struct kvm *kvm = vcpu->kvm; @@ -888,7 +903,7 @@ static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *vcpu, int pmu_id) break; } - kvm->arch.arm_pmu = arm_pmu; + WARN_ON_ONCE(kvm_arm_set_vm_pmu(kvm, arm_pmu)); cpumask_copy(kvm->arch.supported_cpus, &arm_pmu->supported_cpus); ret = 0; break; @@ -913,9 +928,10 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) if (!kvm->arch.arm_pmu) { /* No PMU set, get the default one */ - kvm->arch.arm_pmu = kvm_pmu_probe_armpmu(); - if (!kvm->arch.arm_pmu) - return -ENODEV; + int ret = kvm_arm_set_vm_pmu(kvm, NULL); + + if (ret) + return ret; } switch (attr->attr) { From patchwork Sat May 27 04:02:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13257536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDC26C77B7E for ; Sat, 27 May 2023 04:04:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231757AbjE0EEm (ORCPT ); Sat, 27 May 2023 00:04:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231571AbjE0EEk (ORCPT ); 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Fri, 26 May 2023 21:04:38 -0700 (PDT) Date: Fri, 26 May 2023 21:02:34 -0700 In-Reply-To: <20230527040236.1875860-1-reijiw@google.com> Mime-Version: 1.0 References: <20230527040236.1875860-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230527040236.1875860-3-reijiw@google.com> Subject: [PATCH 2/4] KVM: arm64: PMU: Set the default PMU for the guest on vCPU reset From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Will Deacon , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Set the default PMU for the guest on the first vCPU reset, not when userspace initially uses KVM_ARM_VCPU_PMU_V3_CTRL. The following patches will use the PMUVer of the PMU as the default value of the ID_AA64DFR0_EL1.PMUVer for vCPUs with PMU configured. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/pmu-emul.c | 10 +--------- arch/arm64/kvm/reset.c | 20 +++++++++++++------- include/kvm/arm_pmu.h | 6 ++++++ 3 files changed, 20 insertions(+), 16 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index d50c8f7a2410..0194a94c4bae 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -869,7 +869,7 @@ static bool pmu_irq_is_valid(struct kvm *kvm, int irq) return true; } -static int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) +int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) { lockdep_assert_held(&kvm->arch.config_lock); @@ -926,14 +926,6 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) if (vcpu->arch.pmu.created) return -EBUSY; - if (!kvm->arch.arm_pmu) { - /* No PMU set, get the default one */ - int ret = kvm_arm_set_vm_pmu(kvm, NULL); - - if (ret) - return ret; - } - switch (attr->attr) { case KVM_ARM_VCPU_PMU_V3_IRQ: { int __user *uaddr = (int __user *)(long)attr->addr; diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index b5dee8e57e77..f5e24492926c 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -258,13 +258,24 @@ static int kvm_set_vm_width(struct kvm_vcpu *vcpu) int kvm_reset_vcpu(struct kvm_vcpu *vcpu) { struct vcpu_reset_state reset_state; + struct kvm *kvm = vcpu->kvm; int ret; bool loaded; u32 pstate; - mutex_lock(&vcpu->kvm->arch.config_lock); + mutex_lock(&kvm->arch.config_lock); ret = kvm_set_vm_width(vcpu); - mutex_unlock(&vcpu->kvm->arch.config_lock); + if (!ret && kvm_vcpu_has_pmu(vcpu)) { + if (!kvm_arm_support_pmu_v3()) + ret = -EINVAL; + else if (unlikely(!kvm->arch.arm_pmu)) + /* + * As no PMU is set for the guest yet, + * set the default one. + */ + ret = kvm_arm_set_vm_pmu(kvm, NULL); + } + mutex_unlock(&kvm->arch.config_lock); if (ret) return ret; @@ -315,11 +326,6 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) } else { pstate = VCPU_RESET_PSTATE_EL1; } - - if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) { - ret = -EINVAL; - goto out; - } break; } diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 1a6a695ca67a..5ece2a3c1858 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -96,6 +96,7 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5) u8 kvm_arm_pmu_get_pmuver_limit(void); +int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu); #else struct kvm_pmu { @@ -168,6 +169,11 @@ static inline u8 kvm_arm_pmu_get_pmuver_limit(void) return 0; } +static inline int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) +{ + return 0; +} + #endif #endif From patchwork Sat May 27 04:02:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13257537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50C20C77B73 for ; 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Fri, 26 May 2023 21:04:59 -0700 (PDT) Date: Fri, 26 May 2023 21:02:35 -0700 In-Reply-To: <20230527040236.1875860-1-reijiw@google.com> Mime-Version: 1.0 References: <20230527040236.1875860-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230527040236.1875860-4-reijiw@google.com> Subject: [PATCH 3/4] KVM: arm64: PMU: Use PMUVer of the guest's PMU for ID_AA64DFR0.PMUVer From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Will Deacon , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently, KVM uses the sanitized value of ID_AA64DFR0_EL1.PMUVer as the default value and the limit value of this field for vCPUs with PMU configured. But, the sanitized value could be inappropriate for the vCPUs on some heterogeneous PMU systems, as arm64_ftr_bits for PMUVer is defined as FTR_EXACT with safe_val == 0 (if the ID_AA64DFR0_EL1.PMUVer of all PEs on the host is not uniform, the sanitized value will be 0). Use the PMUver of the guest's PMU (kvm->arch.arm_pmu->pmuver) as the default value and the limit value of ID_AA64DFR0_EL1.PMUVer for vCPUs with PMU configured. When the guest's PMU is switched to a different PMU, reset the value of ID_AA64DFR0_EL1.PMUVer for the vCPUs based on the new PMU, unless userspace has already modified the PMUVer and the value is still valid even with the new PMU. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/arm.c | 6 ---- arch/arm64/kvm/pmu-emul.c | 28 +++++++++++++----- arch/arm64/kvm/sys_regs.c | 48 ++++++++++++++++++++----------- include/kvm/arm_pmu.h | 4 +-- 5 files changed, 57 insertions(+), 31 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 7e7e19ef6993..8ca0e7210a59 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -231,6 +231,8 @@ struct kvm_arch { #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 7 /* SMCCC filter initialized for the VM */ #define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED 8 + /* PMUVer set by userspace for the VM */ +#define KVM_ARCH_FLAG_PMUVER_DIRTY 9 unsigned long flags; /* diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 14391826241c..3c2fddfe90f7 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -164,12 +164,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) set_default_spectre(kvm); kvm_arm_init_hypercalls(kvm); - /* - * Initialise the default PMUver before there is a chance to - * create an actual PMU. - */ - kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit(); - return 0; err_free_cpumask: diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 0194a94c4bae..6cd08d5e5b72 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -871,6 +871,8 @@ static bool pmu_irq_is_valid(struct kvm *kvm, int irq) int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) { + u8 new_limit; + lockdep_assert_held(&kvm->arch.config_lock); if (!arm_pmu) { @@ -880,6 +882,22 @@ int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) } kvm->arch.arm_pmu = arm_pmu; + new_limit = kvm_arm_pmu_get_pmuver_limit(kvm); + + /* + * Reset the value of ID_AA64DFR0_EL1.PMUVer to the new limit value, + * unless the current value was set by userspace and is still a valid + * value for the new PMU. + */ + if (!test_bit(KVM_ARCH_FLAG_PMUVER_DIRTY, &kvm->arch.flags)) { + kvm->arch.dfr0_pmuver.imp = new_limit; + return 0; + } + + if (kvm->arch.dfr0_pmuver.imp > new_limit) { + kvm->arch.dfr0_pmuver.imp = new_limit; + clear_bit(KVM_ARCH_FLAG_PMUVER_DIRTY, &kvm->arch.flags); + } return 0; } @@ -1049,13 +1067,9 @@ int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) return -ENXIO; } -u8 kvm_arm_pmu_get_pmuver_limit(void) +u8 kvm_arm_pmu_get_pmuver_limit(struct kvm *kvm) { - u64 tmp; + u8 host_pmuver = kvm->arch.arm_pmu ? kvm->arch.arm_pmu->pmuver : 0; - tmp = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - tmp = cpuid_feature_cap_perfmon_field(tmp, - ID_AA64DFR0_EL1_PMUVer_SHIFT, - ID_AA64DFR0_EL1_PMUVer_V3P5); - return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp); + return min_t(u8, host_pmuver, ID_AA64DFR0_EL1_PMUVer_V3P5); } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 71b12094d613..a76155ad997c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1382,8 +1382,11 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, { u8 pmuver, host_pmuver; bool valid_pmu; + u64 current_val = read_id_reg(vcpu, rd); + int ret = -EINVAL; - host_pmuver = kvm_arm_pmu_get_pmuver_limit(); + mutex_lock(&vcpu->kvm->arch.config_lock); + host_pmuver = kvm_arm_pmu_get_pmuver_limit(vcpu->kvm); /* * Allow AA64DFR0_EL1.PMUver to be set from userspace as long @@ -1393,26 +1396,31 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, */ pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val); if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver)) - return -EINVAL; + goto out; valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF); /* Make sure view register and PMU support do match */ if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) - return -EINVAL; + goto out; /* We can only differ with PMUver, and anything else is an error */ - val ^= read_id_reg(vcpu, rd); + val ^= current_val; val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); if (val) - return -EINVAL; + goto out; - if (valid_pmu) + if (valid_pmu) { vcpu->kvm->arch.dfr0_pmuver.imp = pmuver; - else + set_bit(KVM_ARCH_FLAG_PMUVER_DIRTY, &vcpu->kvm->arch.flags); + } else vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver; - return 0; + ret = 0; +out: + mutex_unlock(&vcpu->kvm->arch.config_lock); + + return ret; } static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, @@ -1421,8 +1429,11 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, { u8 perfmon, host_perfmon; bool valid_pmu; + u64 current_val = read_id_reg(vcpu, rd); + int ret = -EINVAL; - host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); + mutex_lock(&vcpu->kvm->arch.config_lock); + host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit(vcpu->kvm)); /* * Allow DFR0_EL1.PerfMon to be set from userspace as long as @@ -1433,26 +1444,31 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val); if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) || (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)) - return -EINVAL; + goto out; valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF); /* Make sure view register and PMU support do match */ if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) - return -EINVAL; + goto out; /* We can only differ with PerfMon, and anything else is an error */ - val ^= read_id_reg(vcpu, rd); + val ^= current_val; val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); if (val) - return -EINVAL; + goto out; - if (valid_pmu) + if (valid_pmu) { vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon); - else + set_bit(KVM_ARCH_FLAG_PMUVER_DIRTY, &vcpu->kvm->arch.flags); + } else vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon); - return 0; + ret = 0; +out: + mutex_unlock(&vcpu->kvm->arch.config_lock); + + return ret; } /* diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 5ece2a3c1858..00c05d17cf3a 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -95,7 +95,7 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); #define kvm_pmu_is_3p5(vcpu) \ (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5) -u8 kvm_arm_pmu_get_pmuver_limit(void); +u8 kvm_arm_pmu_get_pmuver_limit(struct kvm *kvm); int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu); #else @@ -164,7 +164,7 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {} static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {} static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {} -static inline u8 kvm_arm_pmu_get_pmuver_limit(void) +static inline u8 kvm_arm_pmu_get_pmuver_limit(struct kvm *kvm) { return 0; } From patchwork Sat May 27 04:02:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13257538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B30A7C7EE2E for ; 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Fri, 26 May 2023 21:05:09 -0700 (PDT) Date: Fri, 26 May 2023 21:02:36 -0700 In-Reply-To: <20230527040236.1875860-1-reijiw@google.com> Mime-Version: 1.0 References: <20230527040236.1875860-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230527040236.1875860-5-reijiw@google.com> Subject: [PATCH 4/4] KVM: arm64: PMU: Don't use the PMUVer of the PMU set for guest From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Will Deacon , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Avoid using the PMUVer of the PMU hardware that is associated to the guest, except in a few cases, as the PMUVer may be different from the value of ID_AA64DFR0_EL1.PMUVer for the guest. The first case is when using the PMUVer as the limit value of the ID_AA64DFR0_EL1.PMUVer for the guest. The second case is when using the PMUVer to determine the valid range of events for KVM_ARM_VCPU_PMU_V3_FILTER, as it has been allowing userspace to specify events that are valid for the PMU hardware, regardless of the value of the guest's ID_AA64DFR0_EL1.PMUVer. KVM will change the valid range of the event that the guest can use based on the value of the guest's ID_AA64DFR0_EL1.PMUVer though. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/pmu-emul.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 6cd08d5e5b72..67512b13ba2d 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -35,12 +35,8 @@ static struct kvm_pmc *kvm_vcpu_idx_to_pmc(struct kvm_vcpu *vcpu, int cnt_idx) return &vcpu->arch.pmu.pmc[cnt_idx]; } -static u32 kvm_pmu_event_mask(struct kvm *kvm) +static u32 __kvm_pmu_event_mask(u8 pmuver) { - unsigned int pmuver; - - pmuver = kvm->arch.arm_pmu->pmuver; - switch (pmuver) { case ID_AA64DFR0_EL1_PMUVer_IMP: return GENMASK(9, 0); @@ -55,6 +51,11 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm) } } +static u32 kvm_pmu_event_mask(struct kvm *kvm) +{ + return __kvm_pmu_event_mask(kvm->arch.dfr0_pmuver.imp); +} + /** * kvm_pmc_is_64bit - determine if counter is 64bit * @pmc: counter context @@ -757,7 +758,7 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) * Don't advertise STALL_SLOT, as PMMIR_EL0 is handled * as RAZ */ - if (vcpu->kvm->arch.arm_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4) + if (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P4) val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32); base = 32; } @@ -970,11 +971,17 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) return 0; } case KVM_ARM_VCPU_PMU_V3_FILTER: { + u8 pmuver = kvm_arm_pmu_get_pmuver_limit(kvm); struct kvm_pmu_event_filter __user *uaddr; struct kvm_pmu_event_filter filter; int nr_events; - nr_events = kvm_pmu_event_mask(kvm) + 1; + /* + * Allow userspace to specify an event filter for the entire + * event range supported by PMUVer of the hardware, rather + * than the guest's PMUVer for KVM backward compatibility. + */ + nr_events = __kvm_pmu_event_mask(pmuver) + 1; uaddr = (struct kvm_pmu_event_filter __user *)(long)attr->addr;