From patchwork Sat May 27 16:44:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Rojek X-Patchwork-Id: 13257693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D2C2C7EE23 for ; Sat, 27 May 2023 16:45:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229903AbjE0Qp1 (ORCPT ); Sat, 27 May 2023 12:45:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229494AbjE0Qp0 (ORCPT ); Sat, 27 May 2023 12:45:26 -0400 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47443D3; Sat, 27 May 2023 09:45:15 -0700 (PDT) X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu Received: by mail.gandi.net (Postfix) with ESMTPSA id 9D16920004; Sat, 27 May 2023 16:45:12 +0000 (UTC) From: Artur Rojek To: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Geert Uytterhoeven Cc: Rafael Ignacio Zurita , linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org, Artur Rojek Subject: [PATCH v2 1/3] sh: dma: Fix dma channel offset calculation Date: Sat, 27 May 2023 18:44:50 +0200 Message-Id: <20230527164452.64797-2-contact@artur-rojek.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230527164452.64797-1-contact@artur-rojek.eu> References: <20230527164452.64797-1-contact@artur-rojek.eu> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Various SoCs of the SH3, SH4 and SH4A family, which use this driver, feature a differing number of DMA channels, which can be distributed between up to two DMAC modules. Existing implementation fails to correctly accommodate for all those variations, resulting in wrong channel offset calculations and leading to kernel panics. Rewrite dma_base_addr() in order to properly calculate channel offsets in a DMAC module. Fix dmaor_read_reg() and dmaor_write_reg(), so that the correct DMAC module base is selected for the DMAOR register. Fixes: 7f47c7189b3e8f19 ("sh: dma: More legacy cpu dma chainsawing.") Signed-off-by: Artur Rojek Reviewed-by: Geert Uytterhoeven Reviewed-by: John Paul Adrian Glaubitz --- v2: also handle differing numbers of DMAC modules and channels arch/sh/drivers/dma/dma-sh.c | 37 +++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index 96c626c2cd0a..306fba1564e5 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c @@ -18,6 +18,18 @@ #include #include +/* + * Some of the SoCs feature two DMAC modules. In such a case, the channels are + * distributed equally among them. + */ +#ifdef SH_DMAC_BASE1 +#define SH_DMAC_NR_MD_CH (CONFIG_NR_ONCHIP_DMA_CHANNELS / 2) +#else +#define SH_DMAC_NR_MD_CH CONFIG_NR_ONCHIP_DMA_CHANNELS +#endif + +#define SH_DMAC_CH_SZ 0x10 + /* * Define the default configuration for dual address memory-memory transfer. * The 0x400 value represents auto-request, external->external. @@ -29,7 +41,7 @@ static unsigned long dma_find_base(unsigned int chan) unsigned long base = SH_DMAC_BASE0; #ifdef SH_DMAC_BASE1 - if (chan >= 6) + if (chan >= SH_DMAC_NR_MD_CH) base = SH_DMAC_BASE1; #endif @@ -40,13 +52,13 @@ static unsigned long dma_base_addr(unsigned int chan) { unsigned long base = dma_find_base(chan); - /* Normalize offset calculation */ - if (chan >= 9) - chan -= 6; - if (chan >= 4) - base += 0x10; + chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ; + + /* DMAOR is placed inside the channel register space. Step over it. */ + if (chan >= DMAOR) + base += SH_DMAC_CH_SZ; - return base + (chan * 0x10); + return base + chan; } #ifdef CONFIG_SH_DMA_IRQ_MULTI @@ -250,12 +262,11 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan) #define NR_DMAOR 1 #endif -/* - * DMAOR bases are broken out amongst channel groups. DMAOR0 manages - * channels 0 - 5, DMAOR1 6 - 11 (optional). - */ -#define dmaor_read_reg(n) __raw_readw(dma_find_base((n)*6)) -#define dmaor_write_reg(n, data) __raw_writew(data, dma_find_base(n)*6) +#define dmaor_read_reg(n) __raw_readw(dma_find_base((n) * \ + SH_DMAC_NR_MD_CH) + DMAOR) +#define dmaor_write_reg(n, data) __raw_writew(data, \ + dma_find_base((n) * \ + SH_DMAC_NR_MD_CH) + DMAOR) static inline int dmaor_reset(int no) { From patchwork Sat May 27 16:44:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Rojek X-Patchwork-Id: 13257694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D07FC77B7E for ; Sat, 27 May 2023 16:45:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229977AbjE0Qp1 (ORCPT ); Sat, 27 May 2023 12:45:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229497AbjE0Qp0 (ORCPT ); Sat, 27 May 2023 12:45:26 -0400 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D95189E; Sat, 27 May 2023 09:45:16 -0700 (PDT) X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu Received: by mail.gandi.net (Postfix) with ESMTPSA id 3FB2020008; Sat, 27 May 2023 16:45:14 +0000 (UTC) From: Artur Rojek To: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Geert Uytterhoeven Cc: Rafael Ignacio Zurita , linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org, Artur Rojek Subject: [PATCH v2 2/3] sh: dma: Drop incorrect SH_DMAC_BASE1 for SH4 Date: Sat, 27 May 2023 18:44:51 +0200 Message-Id: <20230527164452.64797-3-contact@artur-rojek.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230527164452.64797-1-contact@artur-rojek.eu> References: <20230527164452.64797-1-contact@artur-rojek.eu> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org None of the supported SH4 family SoCs features a second DMAC module. As this define negatively impacts DMA channel calculation for the above targets, remove it from the code. Signed-off-by: Artur Rojek Reviewed-by: Geert Uytterhoeven Reviewed-by: John Paul Adrian Glaubitz --- v2: new patch arch/sh/include/cpu-sh4/cpu/dma.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h index 38187d06b234..e97fb2c79177 100644 --- a/arch/sh/include/cpu-sh4/cpu/dma.h +++ b/arch/sh/include/cpu-sh4/cpu/dma.h @@ -13,6 +13,5 @@ #define DMAE0_IRQ evt2irq(0x6c0) #define SH_DMAC_BASE0 0xffa00000 -#define SH_DMAC_BASE1 0xffa00070 #endif /* __ASM_CPU_SH4_DMA_H */ From patchwork Sat May 27 16:44:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Rojek X-Patchwork-Id: 13257695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6058C77B73 for ; Sat, 27 May 2023 16:45:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230038AbjE0Qp2 (ORCPT ); Sat, 27 May 2023 12:45:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229649AbjE0Qp0 (ORCPT ); Sat, 27 May 2023 12:45:26 -0400 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ABAED8; Sat, 27 May 2023 09:45:18 -0700 (PDT) X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu X-GND-Sasl: contact@artur-rojek.eu Received: by mail.gandi.net (Postfix) with ESMTPSA id C5A4A20003; Sat, 27 May 2023 16:45:15 +0000 (UTC) From: Artur Rojek To: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Geert Uytterhoeven Cc: Rafael Ignacio Zurita , linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org, Artur Rojek Subject: [PATCH v2 3/3] sh: dma: Correct the number of DMA channels in SH7709 Date: Sat, 27 May 2023 18:44:52 +0200 Message-Id: <20230527164452.64797-4-contact@artur-rojek.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230527164452.64797-1-contact@artur-rojek.eu> References: <20230527164452.64797-1-contact@artur-rojek.eu> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org According to the hardware manual [1], the DMAC found in SH7709 features only 4 channels. While at it, also sort the existing targets and clarify that NR_ONCHIP_DMA_CHANNELS must be a multiply of two. [1] https://www.renesas.com/us/en/document/mah/sh7709s-group-hardware-manual (p. 373) Signed-off-by: Artur Rojek Reviewed-by: Geert Uytterhoeven Reviewed-by: John Paul Adrian Glaubitz --- v2: - sort existing targets - clarify that the value must be a multiply of two arch/sh/drivers/dma/Kconfig | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig index 7d54f284ce10..382fbb189fcf 100644 --- a/arch/sh/drivers/dma/Kconfig +++ b/arch/sh/drivers/dma/Kconfig @@ -28,17 +28,19 @@ config SH_DMA_API config NR_ONCHIP_DMA_CHANNELS int depends on SH_DMA - default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ - CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7091 + default "4" if CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750 || \ + CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7751 || \ + CPU_SUBTYPE_SH7091 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \ CPU_SUBTYPE_SH7760 - default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \ - CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724 + default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7724 || \ + CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 default "6" help This allows you to specify the number of channels that the on-chip - DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the - SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. + DMAC supports. This will be 4 for SH7709/SH7750/SH7750S/SH7751/SH7091, + 8 for SH7750R/SH7751R/SH7760, and 12 for SH7723/SH7724/SH7780/SH7785. + Default is 6. Must be an even number. config SH_DMABRG bool "SH7760 DMABRG support"