From patchwork Mon May 29 18:19:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Xiang X-Patchwork-Id: 13258867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B816C77B7E for ; Mon, 29 May 2023 18:21:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3hTw-0007dQ-Ii; Mon, 29 May 2023 14:20:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3hTu-0007cw-Jn for qemu-devel@nongnu.org; Mon, 29 May 2023 14:20:34 -0400 Received: from mail-qk1-x72e.google.com ([2607:f8b0:4864:20::72e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3hTs-00018a-RP for qemu-devel@nongnu.org; Mon, 29 May 2023 14:20:34 -0400 Received: by mail-qk1-x72e.google.com with SMTP id af79cd13be357-75b01271ad4so200713685a.1 for ; Mon, 29 May 2023 11:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1685384428; x=1687976428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HnYi90ggTG0Ds7eZTyC/rI0dhRliL/IK6cmFzV+ubwg=; b=SwKgh8ZvhC1yKIvPXbfjcwSnnX3zqussFaWo1bU1+vxKVtwNuj05/liiix4rzTSwXv tMD2TvKuWdyjc4ASMnrCWgy7WNKjQsQb8bOPKqccxuyJQNr72T6IhfmjM+2C+vXWmBq7 HxIPPsLr2mhfZA2pLo4VwIuep+sHgs8teZYnfZ5MYEA847ghPuWTWlsAx/ACB793dpBn iAnebh73K4FMr6MY0Pb2izvUX6ucSFObcA0TM8QltHiMEsU8+Tk+HDOcgb6Xc8zqotry VHqxVZWxC0f1/soAhPN3FrBZlZ2WQMYqcj8I9qJemI0de/lCX5ECuvD2Z/JUgARsTF/0 uniw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685384428; x=1687976428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HnYi90ggTG0Ds7eZTyC/rI0dhRliL/IK6cmFzV+ubwg=; b=dlHBPsO8jUiskfHtv9LrFcKt4sR9nIQKoNuIJxWSes/aQXquH6VWKNtPZhiDX5de8v KpRIVetf6YbHuSPeWFVNqej+1fg099455+mSlUJCaiX5KznCFLwNrTMH8+ydWC7gY9Tl MmdDlX8euTCzz/+s9t7A2+hIPu7e6KdfLPHMIWE6plUdM/gQdahNYpgANJrbUH1CNM3C SS3KJSZpvfADkKFt12jCOqWI2UhWIcUu/Qbt8d5i8M6SX1BTW+Il6EP5kCrPFQru9J5r rBWsQp+10bFP0Vr7QTujEEgUDhaVxt+VARzVWm6A9YnZl8T5V1227aNMz7Np9kdCAUSA zeGg== X-Gm-Message-State: AC+VfDzxk0s9fz4wko3Io+pj7d6/RIekresJUPMmRobo5XdRxmF3n6MD 0iHfBLbyTAjI2LvwsuTDmWFhiA== X-Google-Smtp-Source: ACHHUZ7dOVC6aFr2aRPppOQTh1ca6A8WzVvbcj4g4qV0zfZtKtqkaZbktCJQ4EuZYGKt59WqEAyVrA== X-Received: by 2002:a05:620a:4454:b0:75b:7eea:8178 with SMTP id w20-20020a05620a445400b0075b7eea8178mr10218452qkp.47.1685384428757; Mon, 29 May 2023 11:20:28 -0700 (PDT) Received: from n231-230-216.byted.org ([147.160.184.95]) by smtp.gmail.com with ESMTPSA id b15-20020a05620a126f00b0074e3cf3b44dsm2873314qkl.125.2023.05.29.11.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 11:20:28 -0700 (PDT) From: Hao Xiang To: pbonzini@redhat.com, quintela@redhat.com, qemu-devel@nongnu.org Cc: Hao Xiang Subject: [PATCH 1/4] Introduce new instruction set enqcmd/mmovdir64b to the build system. Date: Mon, 29 May 2023 18:19:58 +0000 Message-Id: <20230529182001.2232069-2-hao.xiang@bytedance.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230529182001.2232069-1-hao.xiang@bytedance.com> References: <20230529182001.2232069-1-hao.xiang@bytedance.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=hao.xiang@bytedance.com; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 1. Enable instruction set enqcmd in build. 2. Enable instruction set movdir64b in build. Signed-off-by: Hao Xiang --- meson.build | 3 +++ meson_options.txt | 4 ++++ scripts/meson-buildoptions.sh | 6 ++++++ 3 files changed, 13 insertions(+) diff --git a/meson.build b/meson.build index 2d48aa1e2e..46f1bb2e34 100644 --- a/meson.build +++ b/meson.build @@ -2682,6 +2682,8 @@ config_host_data.set('CONFIG_AVX512BW_OPT', get_option('avx512bw') \ int main(int argc, char *argv[]) { return bar(argv[0]); } '''), error_message: 'AVX512BW not available').allowed()) +config_host_data.set('CONFIG_DSA_OPT', get_option('enqcmd')) + have_pvrdma = get_option('pvrdma') \ .require(rdma.found(), error_message: 'PVRDMA requires OpenFabrics libraries') \ .require(cc.compiles(gnu_source_prefix + ''' @@ -4123,6 +4125,7 @@ summary_info += {'memory allocator': get_option('malloc')} summary_info += {'avx2 optimization': config_host_data.get('CONFIG_AVX2_OPT')} summary_info += {'avx512bw optimization': config_host_data.get('CONFIG_AVX512BW_OPT')} summary_info += {'avx512f optimization': config_host_data.get('CONFIG_AVX512F_OPT')} +summary_info += {'dsa acceleration': config_host_data.get('CONFIG_DSA_OPT')} if get_option('gprof') gprof_info = 'YES (deprecated)' else diff --git a/meson_options.txt b/meson_options.txt index 90237389e2..51097da56c 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -117,6 +117,10 @@ option('avx512f', type: 'feature', value: 'disabled', description: 'AVX512F optimizations') option('avx512bw', type: 'feature', value: 'auto', description: 'AVX512BW optimizations') +option('enqcmd', type: 'boolean', value: false, + description: 'MENQCMD optimizations') +option('movdir64b', type: 'boolean', value: false, + description: 'MMOVDIR64B optimizations') option('keyring', type: 'feature', value: 'auto', description: 'Linux keyring support') diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index 5714fd93d9..5ef4ec36f4 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -81,6 +81,8 @@ meson_options_help() { printf "%s\n" ' avx2 AVX2 optimizations' printf "%s\n" ' avx512bw AVX512BW optimizations' printf "%s\n" ' avx512f AVX512F optimizations' + printf "%s\n" ' enqcmd ENQCMD optimizations' + printf "%s\n" ' movdir64b MOVDIR64B optimizations' printf "%s\n" ' blkio libblkio block device driver' printf "%s\n" ' bochs bochs image format support' printf "%s\n" ' bpf eBPF support' @@ -221,6 +223,10 @@ _meson_option_parse() { --disable-avx512bw) printf "%s" -Davx512bw=disabled ;; --enable-avx512f) printf "%s" -Davx512f=enabled ;; --disable-avx512f) printf "%s" -Davx512f=disabled ;; + --enable-enqcmd) printf "%s" -Denqcmd=true ;; + --disable-enqcmd) printf "%s" -Denqcmd=false ;; + --enable-movdir64b) printf "%s" -Dmovdir64b=true ;; + --disable-movdir64b) printf "%s" -Dmovdir64b=false ;; --enable-gcov) printf "%s" -Db_coverage=true ;; --disable-gcov) printf "%s" -Db_coverage=false ;; --enable-lto) printf "%s" -Db_lto=true ;; From patchwork Mon May 29 18:19:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Xiang X-Patchwork-Id: 13258871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B75FBC7EE23 for ; Mon, 29 May 2023 18:21:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3hU3-0007et-5c; Mon, 29 May 2023 14:20:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3hTw-0007df-AJ for qemu-devel@nongnu.org; Mon, 29 May 2023 14:20:36 -0400 Received: from mail-qk1-x730.google.com ([2607:f8b0:4864:20::730]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3hTs-00019a-Gw for qemu-devel@nongnu.org; Mon, 29 May 2023 14:20:35 -0400 Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-75b17298108so214951185a.0 for ; Mon, 29 May 2023 11:20:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1685384430; x=1687976430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0JqkkF9dhAzE0OkPFi/BNF1Vq1buivPQjPn42c685Sk=; b=LsbwtNjFfFIRzMXViJZ/XIyzIHoFNUMcSFmz2dyiSvUZwKElAqG9gP8aI3IHNqDsbs 7/wao4b9le7HwbuRDvK/mzXTlP7cavjNX2VjsmQsCohkrkf9d6tMae38WQ2bVE2y5xNH YinKC6/F4HPSqVQXj8xZJIRIPkllrlHC8MomDsSCpVdHumQFC8bB+aupubI/ZgDDP4Ty S19/HGiUn7+TPAkkMAfGZAoX3go6NEVRuRrJ/FYHK3L9AvygqbmSAISwFnrbQgoD3IIR MVnvjFqj5csz8kecbGciR/TVXAfXNV73LP4bsYDvF3oJaj6/ff8TRcxqWgskrZLOkFEf HgnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685384430; x=1687976430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0JqkkF9dhAzE0OkPFi/BNF1Vq1buivPQjPn42c685Sk=; b=c18KXPQpAMF1OUCtUVamkK11y5MjJsYA2UiBdvJrAwHsU2lPVAyqNHGlKoKcM0KZrx DcCxab8qLZ6B9Ceg66MgDpVE0pioQ3A+dGkW+24oEUBoTp8cUADRYmVj0cLc2yk6BBvP yUGlMdUuYvoBgCK1Hf5Ohk65E06RDVq4GyIrFxMt1KXb3KMEAMpu/FKd48Pcp3IjjNbQ oGHtqX/bKIzozLIlygi6cGjTwxJ/AfUE/M/vqKqgwjxAzoAwJoowZWRsL9XBCNEBhQl7 +HQkwlzDG7EKVgJLwESe7mCG/JSXjs5vbJ4B7K/13SSvp4Kzwk+l5L0qKzlp8rxvsIq/ tDoQ== X-Gm-Message-State: AC+VfDwZ0LIZgXq/8dgsjp59SukyvG9mY95zQPIqTSsJhnL05wD7Xtrh ozchr0beb2PWaGtARS2mly2+oRc4Zg6ehKZKhs0= X-Google-Smtp-Source: ACHHUZ6u0epKKcxgVMsKOIQFF2U68CdJYEfHbruZuWlCkfA2dx6j0t3jWrcpG3Qrbmn0zA94ftxeUg== X-Received: by 2002:a37:396:0:b0:75b:23a1:401 with SMTP id 144-20020a370396000000b0075b23a10401mr8150666qkd.23.1685384430528; Mon, 29 May 2023 11:20:30 -0700 (PDT) Received: from n231-230-216.byted.org ([147.160.184.95]) by smtp.gmail.com with ESMTPSA id b15-20020a05620a126f00b0074e3cf3b44dsm2873314qkl.125.2023.05.29.11.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 11:20:30 -0700 (PDT) From: Hao Xiang To: pbonzini@redhat.com, quintela@redhat.com, qemu-devel@nongnu.org Cc: Hao Xiang Subject: [PATCH 2/4] Add dependency idxd. Date: Mon, 29 May 2023 18:19:59 +0000 Message-Id: <20230529182001.2232069-3-hao.xiang@bytedance.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230529182001.2232069-1-hao.xiang@bytedance.com> References: <20230529182001.2232069-1-hao.xiang@bytedance.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=hao.xiang@bytedance.com; helo=mail-qk1-x730.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Idxd is the device driver for DSA (Intel Data Streaming Accelerator). The driver is fully functioning since Linux kernel 5.19. This change adds the driver's header file used for userspace development. Signed-off-by: Hao Xiang --- linux-headers/linux/idxd.h | 356 +++++++++++++++++++++++++++++++++++++ 1 file changed, 356 insertions(+) create mode 100644 linux-headers/linux/idxd.h diff --git a/linux-headers/linux/idxd.h b/linux-headers/linux/idxd.h new file mode 100644 index 0000000000..1d553bedbd --- /dev/null +++ b/linux-headers/linux/idxd.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */ +/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ +#ifndef _USR_IDXD_H_ +#define _USR_IDXD_H_ + +#ifdef __KERNEL__ +#include +#else +#include +#endif + +/* Driver command error status */ +enum idxd_scmd_stat { + IDXD_SCMD_DEV_ENABLED = 0x80000010, + IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, + IDXD_SCMD_WQ_ENABLED = 0x80000021, + IDXD_SCMD_DEV_DMA_ERR = 0x80020000, + IDXD_SCMD_WQ_NO_GRP = 0x80030000, + IDXD_SCMD_WQ_NO_NAME = 0x80040000, + IDXD_SCMD_WQ_NO_SVM = 0x80050000, + IDXD_SCMD_WQ_NO_THRESH = 0x80060000, + IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, + IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, + IDXD_SCMD_PERCPU_ERR = 0x80090000, + IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, + IDXD_SCMD_CDEV_ERR = 0x800b0000, + IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, + IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, + IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, + IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, + IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, + IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, +}; + +#define IDXD_SCMD_SOFTERR_MASK 0x80000000 +#define IDXD_SCMD_SOFTERR_SHIFT 16 + +/* Descriptor flags */ +#define IDXD_OP_FLAG_FENCE 0x0001 +#define IDXD_OP_FLAG_BOF 0x0002 +#define IDXD_OP_FLAG_CRAV 0x0004 +#define IDXD_OP_FLAG_RCR 0x0008 +#define IDXD_OP_FLAG_RCI 0x0010 +#define IDXD_OP_FLAG_CRSTS 0x0020 +#define IDXD_OP_FLAG_CR 0x0080 +#define IDXD_OP_FLAG_CC 0x0100 +#define IDXD_OP_FLAG_ADDR1_TCS 0x0200 +#define IDXD_OP_FLAG_ADDR2_TCS 0x0400 +#define IDXD_OP_FLAG_ADDR3_TCS 0x0800 +#define IDXD_OP_FLAG_CR_TCS 0x1000 +#define IDXD_OP_FLAG_STORD 0x2000 +#define IDXD_OP_FLAG_DRDBK 0x4000 +#define IDXD_OP_FLAG_DSTS 0x8000 + +/* IAX */ +#define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 +#define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 +#define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 +#define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 +#define IDXD_OP_FLAG_SRC2_STS 0x100000 +#define IDXD_OP_FLAG_CRC_RFC3720 0x200000 + +/* Opcode */ +enum dsa_opcode { + DSA_OPCODE_NOOP = 0, + DSA_OPCODE_BATCH, + DSA_OPCODE_DRAIN, + DSA_OPCODE_MEMMOVE, + DSA_OPCODE_MEMFILL, + DSA_OPCODE_COMPARE, + DSA_OPCODE_COMPVAL, + DSA_OPCODE_CR_DELTA, + DSA_OPCODE_AP_DELTA, + DSA_OPCODE_DUALCAST, + DSA_OPCODE_CRCGEN = 0x10, + DSA_OPCODE_COPY_CRC, + DSA_OPCODE_DIF_CHECK, + DSA_OPCODE_DIF_INS, + DSA_OPCODE_DIF_STRP, + DSA_OPCODE_DIF_UPDT, + DSA_OPCODE_CFLUSH = 0x20, +}; + +enum iax_opcode { + IAX_OPCODE_NOOP = 0, + IAX_OPCODE_DRAIN = 2, + IAX_OPCODE_MEMMOVE, + IAX_OPCODE_DECOMPRESS = 0x42, + IAX_OPCODE_COMPRESS, + IAX_OPCODE_CRC64, + IAX_OPCODE_ZERO_DECOMP_32 = 0x48, + IAX_OPCODE_ZERO_DECOMP_16, + IAX_OPCODE_ZERO_COMP_32 = 0x4c, + IAX_OPCODE_ZERO_COMP_16, + IAX_OPCODE_SCAN = 0x50, + IAX_OPCODE_SET_MEMBER, + IAX_OPCODE_EXTRACT, + IAX_OPCODE_SELECT, + IAX_OPCODE_RLE_BURST, + IAX_OPCODE_FIND_UNIQUE, + IAX_OPCODE_EXPAND, +}; + +/* Completion record status */ +enum dsa_completion_status { + DSA_COMP_NONE = 0, + DSA_COMP_SUCCESS, + DSA_COMP_SUCCESS_PRED, + DSA_COMP_PAGE_FAULT_NOBOF, + DSA_COMP_PAGE_FAULT_IR, + DSA_COMP_BATCH_FAIL, + DSA_COMP_BATCH_PAGE_FAULT, + DSA_COMP_DR_OFFSET_NOINC, + DSA_COMP_DR_OFFSET_ERANGE, + DSA_COMP_DIF_ERR, + DSA_COMP_BAD_OPCODE = 0x10, + DSA_COMP_INVALID_FLAGS, + DSA_COMP_NOZERO_RESERVE, + DSA_COMP_XFER_ERANGE, + DSA_COMP_DESC_CNT_ERANGE, + DSA_COMP_DR_ERANGE, + DSA_COMP_OVERLAP_BUFFERS, + DSA_COMP_DCAST_ERR, + DSA_COMP_DESCLIST_ALIGN, + DSA_COMP_INT_HANDLE_INVAL, + DSA_COMP_CRA_XLAT, + DSA_COMP_CRA_ALIGN, + DSA_COMP_ADDR_ALIGN, + DSA_COMP_PRIV_BAD, + DSA_COMP_TRAFFIC_CLASS_CONF, + DSA_COMP_PFAULT_RDBA, + DSA_COMP_HW_ERR1, + DSA_COMP_HW_ERR_DRB, + DSA_COMP_TRANSLATION_FAIL, +}; + +enum iax_completion_status { + IAX_COMP_NONE = 0, + IAX_COMP_SUCCESS, + IAX_COMP_PAGE_FAULT_IR = 0x04, + IAX_COMP_ANALYTICS_ERROR = 0x0a, + IAX_COMP_OUTBUF_OVERFLOW, + IAX_COMP_BAD_OPCODE = 0x10, + IAX_COMP_INVALID_FLAGS, + IAX_COMP_NOZERO_RESERVE, + IAX_COMP_INVALID_SIZE, + IAX_COMP_OVERLAP_BUFFERS = 0x16, + IAX_COMP_INT_HANDLE_INVAL = 0x19, + IAX_COMP_CRA_XLAT, + IAX_COMP_CRA_ALIGN, + IAX_COMP_ADDR_ALIGN, + IAX_COMP_PRIV_BAD, + IAX_COMP_TRAFFIC_CLASS_CONF, + IAX_COMP_PFAULT_RDBA, + IAX_COMP_HW_ERR1, + IAX_COMP_HW_ERR_DRB, + IAX_COMP_TRANSLATION_FAIL, + IAX_COMP_PRS_TIMEOUT, + IAX_COMP_WATCHDOG, + IAX_COMP_INVALID_COMP_FLAG = 0x30, + IAX_COMP_INVALID_FILTER_FLAG, + IAX_COMP_INVALID_INPUT_SIZE, + IAX_COMP_INVALID_NUM_ELEMS, + IAX_COMP_INVALID_SRC1_WIDTH, + IAX_COMP_INVALID_INVERT_OUT, +}; + +#define DSA_COMP_STATUS_MASK 0x7f +#define DSA_COMP_STATUS_WRITE 0x80 + +struct dsa_hw_desc { + uint32_t pasid:20; + uint32_t rsvd:11; + uint32_t priv:1; + uint32_t flags:24; + uint32_t opcode:8; + uint64_t completion_addr; + union { + uint64_t src_addr; + uint64_t rdback_addr; + uint64_t pattern; + uint64_t desc_list_addr; + }; + union { + uint64_t dst_addr; + uint64_t rdback_addr2; + uint64_t src2_addr; + uint64_t comp_pattern; + }; + union { + uint32_t xfer_size; + uint32_t desc_count; + }; + uint16_t int_handle; + uint16_t rsvd1; + union { + uint8_t expected_res; + /* create delta record */ + struct { + uint64_t delta_addr; + uint32_t max_delta_size; + uint32_t delt_rsvd; + uint8_t expected_res_mask; + }; + uint32_t delta_rec_size; + uint64_t dest2; + /* CRC */ + struct { + uint32_t crc_seed; + uint32_t crc_rsvd; + uint64_t seed_addr; + }; + /* DIF check or strip */ + struct { + uint8_t src_dif_flags; + uint8_t dif_chk_res; + uint8_t dif_chk_flags; + uint8_t dif_chk_res2[5]; + uint32_t chk_ref_tag_seed; + uint16_t chk_app_tag_mask; + uint16_t chk_app_tag_seed; + }; + /* DIF insert */ + struct { + uint8_t dif_ins_res; + uint8_t dest_dif_flag; + uint8_t dif_ins_flags; + uint8_t dif_ins_res2[13]; + uint32_t ins_ref_tag_seed; + uint16_t ins_app_tag_mask; + uint16_t ins_app_tag_seed; + }; + /* DIF update */ + struct { + uint8_t src_upd_flags; + uint8_t upd_dest_flags; + uint8_t dif_upd_flags; + uint8_t dif_upd_res[5]; + uint32_t src_ref_tag_seed; + uint16_t src_app_tag_mask; + uint16_t src_app_tag_seed; + uint32_t dest_ref_tag_seed; + uint16_t dest_app_tag_mask; + uint16_t dest_app_tag_seed; + }; + + uint8_t op_specific[24]; + }; +} __attribute__((packed)); + +struct iax_hw_desc { + uint32_t pasid:20; + uint32_t rsvd:11; + uint32_t priv:1; + uint32_t flags:24; + uint32_t opcode:8; + uint64_t completion_addr; + uint64_t src1_addr; + uint64_t dst_addr; + uint32_t src1_size; + uint16_t int_handle; + union { + uint16_t compr_flags; + uint16_t decompr_flags; + }; + uint64_t src2_addr; + uint32_t max_dst_size; + uint32_t src2_size; + uint32_t filter_flags; + uint32_t num_inputs; +} __attribute__((packed)); + +struct dsa_raw_desc { + uint64_t field[8]; +} __attribute__((packed)); + +/* + * The status field will be modified by hardware, therefore it should be + * volatile and prevent the compiler from optimize the read. + */ +struct dsa_completion_record { + volatile uint8_t status; + union { + uint8_t result; + uint8_t dif_status; + }; + uint16_t rsvd; + uint32_t bytes_completed; + uint64_t fault_addr; + union { + /* common record */ + struct { + uint32_t invalid_flags:24; + uint32_t rsvd2:8; + }; + + uint32_t delta_rec_size; + uint64_t crc_val; + + /* DIF check & strip */ + struct { + uint32_t dif_chk_ref_tag; + uint16_t dif_chk_app_tag_mask; + uint16_t dif_chk_app_tag; + }; + + /* DIF insert */ + struct { + uint64_t dif_ins_res; + uint32_t dif_ins_ref_tag; + uint16_t dif_ins_app_tag_mask; + uint16_t dif_ins_app_tag; + }; + + /* DIF update */ + struct { + uint32_t dif_upd_src_ref_tag; + uint16_t dif_upd_src_app_tag_mask; + uint16_t dif_upd_src_app_tag; + uint32_t dif_upd_dest_ref_tag; + uint16_t dif_upd_dest_app_tag_mask; + uint16_t dif_upd_dest_app_tag; + }; + + uint8_t op_specific[16]; + }; +} __attribute__((packed)); + +struct dsa_raw_completion_record { + uint64_t field[4]; +} __attribute__((packed)); + +struct iax_completion_record { + volatile uint8_t status; + uint8_t error_code; + uint16_t rsvd; + uint32_t bytes_completed; + uint64_t fault_addr; + uint32_t invalid_flags; + uint32_t rsvd2; + uint32_t output_size; + uint8_t output_bits; + uint8_t rsvd3; + uint16_t xor_csum; + uint32_t crc; + uint32_t min; + uint32_t max; + uint32_t sum; + uint64_t rsvd4[2]; +} __attribute__((packed)); + +struct iax_raw_completion_record { + uint64_t field[8]; +} __attribute__((packed)); + +#endif From patchwork Mon May 29 18:20:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Xiang X-Patchwork-Id: 13258870 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65194C7EE23 for ; Mon, 29 May 2023 18:21:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3hU2-0007ec-0k; Mon, 29 May 2023 14:20:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3hTw-0007dz-OT for qemu-devel@nongnu.org; Mon, 29 May 2023 14:20:38 -0400 Received: from mail-qk1-x72b.google.com ([2607:f8b0:4864:20::72b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3hTt-00019q-8c for qemu-devel@nongnu.org; Mon, 29 May 2023 14:20:36 -0400 Received: by mail-qk1-x72b.google.com with SMTP id af79cd13be357-75b191fa0afso200010685a.0 for ; Mon, 29 May 2023 11:20:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1685384432; x=1687976432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cw5z9EKJ5wTgcvigkqtkmb/9lbpBGpT9tuRtIHF2xgM=; b=O/vTZqeq/H+kl5jpUgV69Y7Dc/haWtOpN5q1FCpX6XQH0EAiBjTF3wHWUIuKa04V44 PDOYk3o1TnNsXcghb1eNgmbvsqUfKe8GcpJppgUxxqeUZ9x6vo0FNwwadMI/JsFxoRbV uvF8sFMw67XrJ0VU+IsykmZSaFIw80fna2PLXxQYix0OqF8aXqZhLuAETn5WyVptX9Te yOAglaqr20Cf/F2TE+AfsQ1SNGI1KEPJuwHWTMWatMvBKhjNuThL9Dj6GLk5ykkgndxe LXMC1Z0pwHtqSau0FaOA+m7IUweU4SajtIcXkrgClGVai+iN2SFI1QzE0WklMKz6luWL ErXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685384432; x=1687976432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cw5z9EKJ5wTgcvigkqtkmb/9lbpBGpT9tuRtIHF2xgM=; b=g9KQ0q3n2SXspHvlLQd61a5geXQFZmcY/P8b73+1NXW/lKNq3A5C0AeECQDJ32X0tP yYkO9A3mhA7v47DiTVz/Uw6B8AvkxW7TKnr8ArYsckdrwRz4Sxm8T/qs1KYv5ZPmHIAK sIhn5nLLtz0MGg5ucj/lb3Lubo5X297BatXqQFHx16HtsHN35Lh4SxBLahpGzMirTDZx 6cqwAAfafUN4k354xNqtkoOmjRhjLedIcFyMJO6UGTnl+mf4EWmum5nKF2wg+8/4SXKy kzXS4OXg/VSdJbDl9rJl44T04wdWaSsvd/hfIdZ7nU21349Nmw20wPLi2dy3Kfg10gME /AZg== X-Gm-Message-State: AC+VfDwiyTRt1yAKYwoPvFi9FZL6vbZcWX7wjwpa5ZpUxq4nnp4/Qw6M EQ4I5ymr95Q8qsXFnspzoeKyfw== X-Google-Smtp-Source: ACHHUZ4ID/4ZatFhLYODlAWSgR53jgWt0PPjebGJOSGFX98JlfLE229WabB5Z1nlERGw3N3u2YxKkQ== X-Received: by 2002:a37:4656:0:b0:75b:23a1:d84e with SMTP id t83-20020a374656000000b0075b23a1d84emr6781908qka.16.1685384432187; Mon, 29 May 2023 11:20:32 -0700 (PDT) Received: from n231-230-216.byted.org ([147.160.184.95]) by smtp.gmail.com with ESMTPSA id b15-20020a05620a126f00b0074e3cf3b44dsm2873314qkl.125.2023.05.29.11.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 11:20:31 -0700 (PDT) From: Hao Xiang To: pbonzini@redhat.com, quintela@redhat.com, qemu-devel@nongnu.org Cc: Hao Xiang Subject: [PATCH 3/4] Implement zero page checking using DSA. Date: Mon, 29 May 2023 18:20:00 +0000 Message-Id: <20230529182001.2232069-4-hao.xiang@bytedance.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230529182001.2232069-1-hao.xiang@bytedance.com> References: <20230529182001.2232069-1-hao.xiang@bytedance.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=hao.xiang@bytedance.com; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 1. Adds a memory comparison function by submitting the work to the idxd driver. 2. Add interface to set bufferiszero accel function to DSA offloading. 3. Fallback to use CPU accel function if DSA offloading fails due to page fault. Signed-off-by: Hao Xiang --- include/qemu/cutils.h | 6 + migration/ram.c | 4 + util/bufferiszero.c | 14 ++ util/dsa.c | 295 ++++++++++++++++++++++++++++++++++++++++++ util/meson.build | 1 + 5 files changed, 320 insertions(+) create mode 100644 util/dsa.c diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h index 92c436d8c7..9d0286ac99 100644 --- a/include/qemu/cutils.h +++ b/include/qemu/cutils.h @@ -188,9 +188,15 @@ char *freq_to_str(uint64_t freq_hz); /* used to print char* safely */ #define STR_OR_NULL(str) ((str) ? (str) : "null") +typedef bool (*buffer_accel_fn)(const void *, size_t); +void set_accel(buffer_accel_fn, size_t len); +void get_fallback_accel(buffer_accel_fn *); bool buffer_is_zero(const void *buf, size_t len); bool test_buffer_is_zero_next_accel(void); +int configure_dsa(const char *dsa_path); +void dsa_cleanup(void); + /* * Implementation of ULEB128 (http://en.wikipedia.org/wiki/LEB128) * Input is limited to 14-bit numbers diff --git a/migration/ram.c b/migration/ram.c index 88a6c82e63..b586ac4a99 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -2280,6 +2280,10 @@ static int ram_save_host_page(RAMState *rs, PageSearchStatus *pss) if (preempt_active) { qemu_mutex_unlock(&rs->bitmap_mutex); } + /* + * TODO: Make ram_save_target_page asyn to take advantage + * of DSA offloading. + */ tmppages = migration_ops->ram_save_target_page(rs, pss); if (tmppages >= 0) { pages += tmppages; diff --git a/util/bufferiszero.c b/util/bufferiszero.c index 3e6a5dfd63..3d089ef1fe 100644 --- a/util/bufferiszero.c +++ b/util/bufferiszero.c @@ -206,6 +206,7 @@ buffer_zero_avx512(const void *buf, size_t len) static unsigned used_accel = INIT_USED; static unsigned length_to_accel = INIT_LENGTH; static bool (*buffer_accel)(const void *, size_t) = INIT_ACCEL; +static bool (*buffer_accel_fallback)(const void *, size_t) = INIT_ACCEL; static unsigned __attribute__((noinline)) select_accel_cpuinfo(unsigned info) @@ -231,6 +232,7 @@ select_accel_cpuinfo(unsigned info) if (info & all[i].bit) { length_to_accel = all[i].len; buffer_accel = all[i].fn; + buffer_accel_fallback = all[i].fn; return all[i].bit; } } @@ -272,6 +274,17 @@ bool test_buffer_is_zero_next_accel(void) } #endif +void set_accel(buffer_accel_fn fn, size_t len) +{ + buffer_accel = fn; + length_to_accel = len; +} + +void get_fallback_accel(buffer_accel_fn *fn) +{ + *fn = buffer_accel_fallback; +} + /* * Checks if a buffer is all zeroes */ @@ -288,3 +301,4 @@ bool buffer_is_zero(const void *buf, size_t len) includes a check for an unrolled loop over 64-bit integers. */ return select_accel_fn(buf, len); } + diff --git a/util/dsa.c b/util/dsa.c new file mode 100644 index 0000000000..2fdcdb4f49 --- /dev/null +++ b/util/dsa.c @@ -0,0 +1,295 @@ +/* + * Use Intel Data Streaming Accelerator to offload certain background + * operations. + * + * Copyright (c) 2023 Hao Xiang + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include "qemu/bswap.h" +#include "qemu/error-report.h" + +#ifdef CONFIG_DSA_OPT + +#pragma GCC push_options +#pragma GCC target("enqcmd") +#pragma GCC target("movdir64b") + +#include +#include "x86intrin.h" + +#define DSA_WQ_SIZE 4096 + +static bool use_simulation; +static uint64_t total_bytes_checked; +static uint64_t total_function_calls; +static uint64_t total_success_count; +static int max_retry_count; +static int top_retry_count; + +static void *dsa_wq = MAP_FAILED; +static uint8_t zero_page_buffer[4096]; +static bool dedicated_mode; +static int length_to_accel = 64; + +static buffer_accel_fn buffer_zero_fallback; + +/** + * @brief This function opens a DSA device's work queue and + * maps the DSA device memory into the current process. + * + * @param dsa_wq_path A pointer to the DSA device work queue's file path. + * @return A pointer to the mapped memory. + */ +static void *map_dsa_device(const char *dsa_wq_path) +{ + void *dsa_device; + int fd; + + fd = open(dsa_wq_path, O_RDWR); + if (fd < 0) { + fprintf(stderr, "open %s failed with errno = %d.\n", + dsa_wq_path, errno); + return MAP_FAILED; + } + dsa_device = mmap(NULL, DSA_WQ_SIZE, PROT_WRITE, + MAP_SHARED | MAP_POPULATE, fd, 0); + close(fd); + if (dsa_device == MAP_FAILED) { + fprintf(stderr, "mmap failed with errno = %d.\n", errno); + return MAP_FAILED; + } + return dsa_device; +} + +/** + * @brief Submits a DSA work item to the device work queue. + * + * @param wq A pointer to the DSA work queue's device memory. + * @param descriptor A pointer to the DSA work item descriptor. + * @return Zero if successful, non-zero otherwise. + */ +static int submit_wi(void *wq, void *descriptor) +{ + int retry = 0; + + _mm_sfence(); + + if (dedicated_mode) { + _movdir64b(dsa_wq, descriptor); + } else { + while (true) { + if (_enqcmd(dsa_wq, descriptor) == 0) { + break; + } + retry++; + if (retry > max_retry_count) { + fprintf(stderr, "Submit work retry %d times.\n", retry); + exit(1); + } + } + } + + return 0; +} + +/** + * @brief Poll for the DSA work item completion. + * + * @param completion A pointer to the DSA work item completion record. + * @param opcode The DSA opcode. + * @return Zero if successful, non-zero otherwise. + */ +static int poll_completion(struct dsa_completion_record *completion, + enum dsa_opcode opcode) +{ + int retry = 0; + + while (true) { + if (completion->status != DSA_COMP_NONE) { + /* TODO: Error handling here. */ + if (completion->status != DSA_COMP_SUCCESS && + completion->status != DSA_COMP_PAGE_FAULT_NOBOF) { + fprintf(stderr, "DSA opcode %d failed with status = %d.\n", + opcode, completion->status); + exit(1); + } else { + total_success_count++; + } + break; + } + retry++; + if (retry > max_retry_count) { + fprintf(stderr, "Wait for completion retry %d times.\n", retry); + exit(1); + } + _mm_pause(); + } + + if (retry > top_retry_count) { + top_retry_count = retry; + } + + return 0; +} + +static bool buffer_zero_dsa_simulation(const void *buf, size_t len) +{ + /* TODO: Handle page size greater than 4k. */ + if (len > sizeof(zero_page_buffer)) { + fprintf(stderr, "Page size greater than %lu is not supported by DSA " + "buffer zero checking.\n", sizeof(zero_page_buffer)); + exit(1); + } + + total_bytes_checked += len; + total_function_calls++; + + return memcmp(buf, zero_page_buffer, len) == 0; +} + +/** + * @brief Sends a memory comparison work item to a DSA device and wait + * for completion. + * + * @param buf A pointer to the memory buffer for comparison. + * @param len Length of the memory buffer for comparison. + * @return true if the memory buffer is all zero, false otherwise. + */ +static bool buffer_zero_dsa(const void *buf, size_t len) +{ + struct dsa_completion_record completion __attribute__((aligned(32))); + struct dsa_hw_desc descriptor; + uint8_t test_byte; + + /* TODO: Handle page size greater than 4k. */ + if (len > sizeof(zero_page_buffer)) { + fprintf(stderr, "Page size greater than %lu is not supported by DSA " + "buffer zero checking.\n", sizeof(zero_page_buffer)); + exit(1); + } + + total_bytes_checked += len; + total_function_calls++; + + memset(&completion, 0, sizeof(completion)); + memset(&descriptor, 0, sizeof(descriptor)); + + descriptor.opcode = DSA_OPCODE_COMPARE; + descriptor.flags = IDXD_OP_FLAG_RCR | IDXD_OP_FLAG_CRAV; + descriptor.xfer_size = len; + descriptor.src_addr = (uintptr_t)buf; + descriptor.dst_addr = (uintptr_t)zero_page_buffer; + completion.status = 0; + descriptor.completion_addr = (uint64_t)&completion; + + /* + * TODO: Find a better solution. DSA device can encounter page + * fault during the memory comparison operatio. Block on page + * fault is turned off for better performance. This temporary + * solution reads the first byte of the memory buffer in order + * to cause a CPU page fault so that DSA device won't hit that + * later. + */ + test_byte = ((uint8_t *)buf)[0]; + ((uint8_t *)buf)[0] = test_byte; + + submit_wi(dsa_wq, &descriptor); + poll_completion(&completion, DSA_OPCODE_COMPARE); + + if (completion.status == DSA_COMP_SUCCESS) { + return completion.result == 0; + } + + /* + * DSA was able to partially complete the operation. Check the + * result. If we already know this is not a zero page, we can + * return now. + */ + if (completion.bytes_completed != 0 && completion.result != 0) { + return false; + } + + /* Let's fallback to use CPU to complete it. */ + return buffer_zero_fallback((uint8_t *)buf + completion.bytes_completed, + len - completion.bytes_completed); +} + +/** + * @brief Check if DSA devices are enabled in the current system + * and set DSA offloading for zero page checking operation. + * This function is called during QEMU initialization. + * + * @param dsa_path A pointer to the DSA device's work queue file path. + * @return int Zero if successful, non-zero otherwise. + */ +int configure_dsa(const char *dsa_path) +{ + dedicated_mode = false; + use_simulation = false; + max_retry_count = 3000; + total_bytes_checked = 0; + total_function_calls = 0; + total_success_count = 0; + + memset(zero_page_buffer, 0, sizeof(zero_page_buffer)); + + dsa_wq = map_dsa_device(dsa_path); + if (dsa_wq == MAP_FAILED) { + fprintf(stderr, "map_dsa_device failed MAP_FAILED, " + "using simulation.\n"); + return -1; + } + + if (use_simulation) + set_accel(buffer_zero_dsa_simulation, length_to_accel); + else { + set_accel(buffer_zero_dsa, length_to_accel); + get_fallback_accel(&buffer_zero_fallback); + } + + return 0; +} + +/** + * @brief Clean up system resources created for DSA offloading. + * This function is called during QEMU process teardown. + * + */ +void dsa_cleanup(void) +{ + if (dsa_wq != MAP_FAILED) { + munmap(dsa_wq, DSA_WQ_SIZE); + } +} + +#else + +int configure_dsa(const char *dsa_path) +{ + fprintf(stderr, "Intel Data Streaming Accelerator is not supported " + "on this platform.\n"); + return -1; +} + +void dsa_cleanup(void) {} + +#endif diff --git a/util/meson.build b/util/meson.build index 3a93071d27..f493071c91 100644 --- a/util/meson.build +++ b/util/meson.build @@ -84,6 +84,7 @@ if have_block or have_ga endif if have_block util_ss.add(files('aio-wait.c')) + util_ss.add(files('dsa.c')) util_ss.add(files('buffer.c')) util_ss.add(files('bufferiszero.c')) util_ss.add(files('hbitmap.c')) From patchwork Mon May 29 18:20:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hao Xiang X-Patchwork-Id: 13258868 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC3DFC77B7E for ; Mon, 29 May 2023 18:21:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3hU5-0007fV-4I; Mon, 29 May 2023 14:20:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3hU3-0007ex-J0 for qemu-devel@nongnu.org; Mon, 29 May 2023 14:20:43 -0400 Received: from mail-qk1-x72a.google.com ([2607:f8b0:4864:20::72a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3hU1-0001C6-Uf for qemu-devel@nongnu.org; Mon, 29 May 2023 14:20:43 -0400 Received: by mail-qk1-x72a.google.com with SMTP id af79cd13be357-75b17aa343dso199241485a.3 for ; Mon, 29 May 2023 11:20:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1685384440; x=1687976440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ditkvgARSzWzoYJqFtP0/VdEyM3sOS6PtcRTcUcchLI=; b=eWuQNrm4dGht6EAPLOgFBFWtQXqsYOFvVhdMAgTLxTYCN6zdlZOVf5SwGWDhxH6gpO JCmDzKO7yN6xheOIVCVL2RphlyoQUNBMiqyjDqDI5nmim4DIRHDhl1lzfpvK9itjJ2Mh yFuLYCOtfjdqP+QCh5RcNwSUHINMiT4f2GakZkk7BtvEBg/Hvsv2/1YMGjy9Jmn3O65j ATwCTMjsSS1fmcpuF9+qmU7KNiED5bpZ95+qHUCW0/52HEfCjJ0HfyQfN5yutx6cARyp 1K4LCXHiQjIZ7QPdzQy3tptbmoqUgWWTQKT5makOFjBfj0tH/0PR0jvrWJ4Ov/RrALfK 6waA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685384440; x=1687976440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ditkvgARSzWzoYJqFtP0/VdEyM3sOS6PtcRTcUcchLI=; b=Rn3j8RSByAR8waRoOtV7gXWeXv+tejhx49zlU0g49z8O08S67/Qy0HC4Wluvnk/wEz vuL5io1ssF4MlvXnruxJq+ALOCEt+ierf8S0vzmSD4U6GOjx+z2DVZwAonHReFmLwVeO x7WZ6j3gqAOn+ZD0Aroe+oL/tXFyt6RmuHp0RWSGR6bgfzaLkR2CIf+4/b6wgN+YxxCn YM1fmHjFBVZ/d6kQAxaXYNawNSKhKjsSdK363W2+O3Dq5LfO1eM1PHQqpLEhqw/MnhQD CedXbs3aHlbs+vfp32+E4TOiBO/XKqhIZsG8Qh6+dt6ULQ5qfQIiVMFVpM/7SXL/ki8X rppQ== X-Gm-Message-State: AC+VfDyusB4rFcqhs+PpLyo1i6Q5OsnkZkziKAgcc4xDcq+iT44JOPat xoNm5b5pGkUIUMvV5AYqEudCUA== X-Google-Smtp-Source: ACHHUZ6BWGYkuDCOOzv0A45ehuwwKyXCMSglKeIiR1qhOihyFCgZler6X7EWmWf/FQ8xfJzl/2TCdA== X-Received: by 2002:a05:620a:3c16:b0:75b:23a1:8332 with SMTP id tn22-20020a05620a3c1600b0075b23a18332mr7938039qkn.45.1685384440475; Mon, 29 May 2023 11:20:40 -0700 (PDT) Received: from n231-230-216.byted.org ([147.160.184.95]) by smtp.gmail.com with ESMTPSA id b15-20020a05620a126f00b0074e3cf3b44dsm2873314qkl.125.2023.05.29.11.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 11:20:40 -0700 (PDT) From: Hao Xiang To: pbonzini@redhat.com, quintela@redhat.com, qemu-devel@nongnu.org Cc: Hao Xiang Subject: [PATCH 4/4] Add QEMU command line argument to enable DSA offloading. Date: Mon, 29 May 2023 18:20:01 +0000 Message-Id: <20230529182001.2232069-5-hao.xiang@bytedance.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230529182001.2232069-1-hao.xiang@bytedance.com> References: <20230529182001.2232069-1-hao.xiang@bytedance.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=hao.xiang@bytedance.com; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This change adds a new argument --dsa-accelerate to qemu. Signed-off-by: Hao Xiang --- qemu-options.hx | 10 ++++++++++ softmmu/runstate.c | 4 ++++ softmmu/vl.c | 22 ++++++++++++++++++++++ storage-daemon/qemu-storage-daemon.c | 2 ++ 4 files changed, 38 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index b37eb9662b..29491ee691 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4890,6 +4890,16 @@ SRST otherwise the option is ignored. Default is off. ERST +DEF("dsa-accelerate", HAS_ARG, QEMU_OPTION_dsa, + "-dsa-accelerate \n" + " Use Intel Data Streaming Accelerator for certain QEMU\n" + " operations, eg, checkpoint.\n", + QEMU_ARCH_I386) +SRST +``-dsa-accelerate path`` + The device path to a DSA accelerator. +ERST + DEF("dump-vmstate", HAS_ARG, QEMU_OPTION_dump_vmstate, "-dump-vmstate \n" " Output vmstate information in JSON format to file.\n" diff --git a/softmmu/runstate.c b/softmmu/runstate.c index 2f2396c819..1f938e192f 100644 --- a/softmmu/runstate.c +++ b/softmmu/runstate.c @@ -41,6 +41,7 @@ #include "qapi/qapi-commands-run-state.h" #include "qapi/qapi-events-run-state.h" #include "qemu/accel.h" +#include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/job.h" #include "qemu/log.h" @@ -834,6 +835,9 @@ void qemu_cleanup(void) tpm_cleanup(); net_cleanup(); audio_cleanup(); + + dsa_cleanup(); + monitor_cleanup(); qemu_chr_cleanup(); user_creatable_cleanup(); diff --git a/softmmu/vl.c b/softmmu/vl.c index b0b96f67fa..8ace491183 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -161,6 +161,7 @@ static const char *mem_path; static const char *incoming; static const char *loadvm; static const char *accelerators; +static const char *dsa_path; static bool have_custom_ram_size; static const char *ram_memdev_id; static QDict *machine_opts_dict; @@ -373,6 +374,20 @@ static QemuOptsList qemu_msg_opts = { }, }; +static QemuOptsList qemu_dsa_opts = { + .name = "dsa-accelerate", + .head = QTAILQ_HEAD_INITIALIZER(qemu_dsa_opts.head), + .desc = { + { + .name = "device", + .type = QEMU_OPT_STRING, + .help = "The device path to DSA accelerator used for certain " + "QEMU operations, eg, checkpoint\n", + }, + { /* end of list */ } + }, +}; + static QemuOptsList qemu_name_opts = { .name = "name", .implied_opt_name = "guest", @@ -2704,6 +2719,7 @@ void qemu_init(int argc, char **argv) qemu_add_opts(&qemu_semihosting_config_opts); qemu_add_opts(&qemu_fw_cfg_opts); qemu_add_opts(&qemu_action_opts); + qemu_add_opts(&qemu_dsa_opts); module_call_init(MODULE_INIT_OPTS); error_init(argv[0]); @@ -3504,6 +3520,12 @@ void qemu_init(int argc, char **argv) } configure_msg(opts); break; + case QEMU_OPTION_dsa: + dsa_path = optarg; + if (configure_dsa(dsa_path)) { + exit(1); + } + break; case QEMU_OPTION_dump_vmstate: if (vmstate_dump_file) { error_report("only one '-dump-vmstate' " diff --git a/storage-daemon/qemu-storage-daemon.c b/storage-daemon/qemu-storage-daemon.c index 0e9354faa6..0e4375407a 100644 --- a/storage-daemon/qemu-storage-daemon.c +++ b/storage-daemon/qemu-storage-daemon.c @@ -439,6 +439,8 @@ int main(int argc, char *argv[]) job_cancel_sync_all(); bdrv_close_all(); + dsa_cleanup(); + monitor_cleanup(); qemu_chr_cleanup(); user_creatable_cleanup();