From patchwork Wed May 31 08:43:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13261736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEEC1C77B7C for ; Wed, 31 May 2023 08:44:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4HQZ-00029u-VK; Wed, 31 May 2023 04:43:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQV-00028m-Eb for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:27 -0400 Received: from mga06b.intel.com ([134.134.136.31] helo=mga06.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQP-0005fO-ED for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685522601; x=1717058601; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tCe2NK+4wo5tYFcR9V7u1zkUeKhtImrp9c2scYoxMcc=; b=chGVtOS/xmsrpyXMcKItWYV/XaSF57sVVhYWiUaYu9/PgnOlixttcfy3 ty6gaUXUA4aHwJoBDjLjM0X7FWb6PNjkaP5SNiY4PYy3S/uhNRatlQhGF 1tX7C3oOr/tQrpwqc69qwqrQZ9tQrFCqtBdlqg8i7XOv795hhnJ7nYPDy XK4n6bLWJb19aY8yGMImlUy14Rf1e+tzebnb0cDmEwpVdkfJ2GWEOvV8s je4orI+iEm5Z4oOJWPF7VggpzoFfrWR+MC8oyaX4lvIusbLIyWsEWAznG qfRdm1YAFi0mm/pIwqLHnp891P7SF6/gQ27pgLU3KHHv2A6J/v0JIZsTM Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="418669242" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="418669242" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2023 01:43:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="1036956395" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="1036956395" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga005.fm.intel.com with ESMTP; 31 May 2023 01:43:17 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chenyi Qiang , lei4.wang@intel.com Subject: [PATCH v4 1/8] target/i386: Print CPUID subleaf info for unsupported feature Date: Wed, 31 May 2023 04:43:04 -0400 Message-Id: <20230531084311.3807277-2-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com> References: <20230531084311.3807277-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=xiaoyao.li@intel.com; helo=mga06.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some CPUID leaves have meaningful subleaf index. Print the subleaf info in feature_word_description for CPUID features. Signed-off-by: Xiaoyao Li Reviewed-by: Eduardo Habkost --- target/i386/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1242bd541a53..88e90c1f7b7c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4745,8 +4745,9 @@ static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) { const char *reg = get_register_name_32(f->cpuid.reg); assert(reg); - return g_strdup_printf("CPUID.%02XH:%s", - f->cpuid.eax, reg); + return g_strdup_printf("CPUID.%02XH_%02XH:%s", + f->cpuid.eax, + f->cpuid.needs_ecx ? f->cpuid.ecx : 0, reg); } case MSR_FEATURE_WORD: return g_strdup_printf("MSR(%02XH)", From patchwork Wed May 31 08:43:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13261737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEEF7C7EE24 for ; Wed, 31 May 2023 08:44:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4HQZ-00029f-Uc; Wed, 31 May 2023 04:43:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQT-000276-Td for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:26 -0400 Received: from mga06b.intel.com ([134.134.136.31] helo=mga06.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQR-0005fZ-6c for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685522603; x=1717058603; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PUiPWRxoJu35zk6JisuELImdtxTwEvzqb0+TEiNmcuc=; b=fu8NaIJcanO3fmYdkVGMR9CeleDETskL/G+g0vIAcCzkjFLvSTAlOe2i g14oZyP0NAdnUDMfww7riKZm3XgFVItSB6Eb+s6brWgEbrhIrgSPd1wkA maKUu2L2P2FQNr9yrrAHmjwy0O7bwxeKn5/QdC9vPkoprqqSyHCEPU7rf qK3uRaxs+4tyMIbWGtJsBatVW/OZlEdMIX5/DTSrhFUbR/Dl13tbQnS64 4CsA191jq2cULihy5ULjSvxnZYSXD8C84o9a6U2N+bES0EVGz5fIDuDkP UXx0xrmBoIZOB4YTnPccCb7PYW0FDLybF9FKvRbUFiwZ9Oc+kIv9rAokd g==; X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="418669250" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="418669250" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2023 01:43:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="1036956407" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="1036956407" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga005.fm.intel.com with ESMTP; 31 May 2023 01:43:19 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chenyi Qiang , lei4.wang@intel.com Subject: [PATCH v4 2/8] target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK Date: Wed, 31 May 2023 04:43:05 -0400 Message-Id: <20230531084311.3807277-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com> References: <20230531084311.3807277-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=xiaoyao.li@intel.com; helo=mga06.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Per Intel SDM, bits 2:0 of CPUID(0x14,0x1).EAX indicate the number of address ranges for INTEL-PT. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 88e90c1f7b7c..7d2f20c84c7a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -573,7 +573,7 @@ static CPUCacheInfo legacy_l3_cache = { /* generated packets which contain IP payloads have LIP values */ #define INTEL_PT_IP_LIP (1 << 31) #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ -#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ From patchwork Wed May 31 08:43:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13261751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CAA05C7EE24 for ; Wed, 31 May 2023 08:44:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4HQx-0002Da-Nh; Wed, 31 May 2023 04:43:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQV-00028l-EF for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:27 -0400 Received: from mga06b.intel.com ([134.134.136.31] helo=mga06.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQS-0005fJ-Vh for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685522604; x=1717058604; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tdHez5vp4jS9ioxnU93LsxbiSFFkxThteRjsc69/woI=; b=Bwv7l80b+3gODY6gaOVu0qgzExGMuBy/t9fUqOcwL6R2CiN3VnpvzdJ+ 8hAKHltdwoExCU+1/0YRKor7jwyJ9sfHzyUBTxMh8iU1hKzELe4ScMCRV d29p15wj+qj+Q1Q1AWQcJqww/aWZO8b4AXuB82EPIjBldbsU1mospkBZo zf3UYVkNbzI97g5ZgEq32VR2+nBhBqmL+eSs1SL/oPzNxvwVQC3QpR/Rc THvU6vPyYV4YG6p2pYdhnDv6HUg8d7IEvgroRq5beRkbrpt8bnXfp0tkM mqoT4hW7Sn5oE+U+eTRA7ISr4yPD0u8es+QhyElpWgj2BF2+w/UXjwjcg g==; X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="418669265" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="418669265" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2023 01:43:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="1036956422" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="1036956422" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga005.fm.intel.com with ESMTP; 31 May 2023 01:43:20 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chenyi Qiang , lei4.wang@intel.com Subject: [PATCH v4 3/8] target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID leaf 0x14 Date: Wed, 31 May 2023 04:43:06 -0400 Message-Id: <20230531084311.3807277-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com> References: <20230531084311.3807277-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=xiaoyao.li@intel.com; helo=mga06.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org CPUID leaf 0x14 subleaf 0x0 and 0x1 enumerate the resource and capability of Intel PT. Introduce FeatureWord FEAT_14_0_EBX, FEAT_14_1_EAX and FEAT_14_1_EBX, and complete FEAT_14_0_ECX. Thus all the features of Intel PT can be expanded when "-cpu host/max" and can be configured in named CPU model. Signed-off-by: Xiaoyao Li --- v3: - Add bit 7 and 8 of FEAT_14_0_EBX --- target/i386/cpu.c | 138 +++++++++++++++++++++++++++++++++++++++++++--- target/i386/cpu.h | 3 + 2 files changed, 132 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7d2f20c84c7a..e735c366bc97 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1248,17 +1248,34 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { } }, + [FEAT_14_0_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [0] = "intel-pt-cr3-filter", + [1] = "intel-pt-psb", + [2] = "intel-pt-ip-filter", + [3] = "intel-pt-mtc", + [4] = "intel-pt-ptwrite", + [5] = "intel-pt-power-event", + [6] = "intel-pt-psb-pmi-preservation", + [7] = "intel-pt-event-trace", + [8] = "intel-pt-tnt-disable", + }, + .cpuid = { + .eax = 0x14, + .needs_ecx = true, .ecx = 0, + .reg = R_EBX, + }, + }, + [FEAT_14_0_ECX] = { .type = CPUID_FEATURE_WORD, .feat_names = { - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, "intel-pt-lip", + [0] = "intel-pt-topa", + [1] = "intel-pt-multi-topa-entries", + [2] = "intel-pt-single-range", + [3] = "intel-pt-trace-transport-subsystem", + [31] = "intel-pt-lip", }, .cpuid = { .eax = 0x14, @@ -1268,6 +1285,79 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .tcg_features = TCG_14_0_ECX_FEATURES, }, + [FEAT_14_1_EAX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [0] = "intel-pt-addr-range-num-bit0", + [1] = "intel-pt-addr-range-num-bit1", + [2] = "intel-pt-addr-range-num-bit2", + [16] = "intel-pt-mtc-period-encoding-0", + [17] = "intel-pt-mtc-period-encoding-1", + [18] = "intel-pt-mtc-period-encoding-2", + [19] = "intel-pt-mtc-period-encoding-3", + [20] = "intel-pt-mtc-period-encoding-4", + [21] = "intel-pt-mtc-period-encoding-5", + [22] = "intel-pt-mtc-period-encoding-6", + [23] = "intel-pt-mtc-period-encoding-7", + [24] = "intel-pt-mtc-period-encoding-8", + [25] = "intel-pt-mtc-period-encoding-9", + [26] = "intel-pt-mtc-period-encoding-10", + [27] = "intel-pt-mtc-period-encoding-11", + [28] = "intel-pt-mtc-period-encoding-12", + [29] = "intel-pt-mtc-period-encoding-13", + [30] = "intel-pt-mtc-period-encoding-14", + [31] = "intel-pt-mtc-period-encoding-15", + }, + .cpuid = { + .eax = 0x14, + .needs_ecx = true, .ecx = 1, + .reg = R_EAX, + }, + }, + + [FEAT_14_1_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { + [0] = "intel-pt-cyc-thresh-0", + [1] = "intel-pt-cyc-thresh-1", + [2] = "intel-pt-cyc-thresh-2", + [3] = "intel-pt-cyc-thresh-4", + [4] = "intel-pt-cyc-thresh-8", + [5] = "intel-pt-cyc-thresh-16", + [6] = "intel-pt-cyc-thresh-32", + [7] = "intel-pt-cyc-thresh-64", + [8] = "intel-pt-cyc-thresh-128", + [9] = "intel-pt-cyc-thresh-256", + [10] = "intel-pt-cyc-thresh-512", + [11] = "intel-pt-cyc-thresh-1024", + [12] = "intel-pt-cyc-thresh-2048", + [13] = "intel-pt-cyc-thresh-4096", + [14] = "intel-pt-cyc-thresh-8192", + [15] = "intel-pt-cyc-thresh-16384", + [16] = "intel-pt-psb-freq-2k", + [17] = "intel-pt-psb-freq-4k", + [18] = "intel-pt-psb-freq-8k", + [19] = "intel-pt-psb-freq-16k", + [20] = "intel-pt-psb-freq-32k", + [21] = "intel-pt-psb-freq-64k", + [22] = "intel-pt-psb-freq-128k", + [23] = "intel-pt-psb-freq-256k", + [24] = "intel-pt-psb-freq-512k", + [25] = "intel-pt-psb-freq-1m", + [26] = "intel-pt-psb-freq-2m", + [27] = "intel-pt-psb-freq-4m", + [28] = "intel-pt-psb-freq-8m", + [29] = "intel-pt-psb-freq-16m", + [30] = "intel-pt-psb-freq-32m", + [31] = "intel-pt-psb-freq-64m", + }, + .cpuid = { + .eax = 0x14, + .needs_ecx = true, .ecx = 1, + .reg = R_EBX, + }, + }, + [FEAT_SGX_12_0_EAX] = { .type = CPUID_FEATURE_WORD, .feat_names = { @@ -1407,10 +1497,22 @@ static FeatureDep feature_dependencies[] = { .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, }, + { + .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to = { FEAT_14_0_EBX, ~0ull }, + }, { .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, .to = { FEAT_14_0_ECX, ~0ull }, }, + { + .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to = { FEAT_14_1_EAX, ~0ull }, + }, + { + .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to = { FEAT_14_1_EBX, ~0ull }, + }, { .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, @@ -6871,7 +6973,25 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) uint64_t host_feat = x86_cpu_get_supported_feature_word(w, false); uint64_t requested_features = env->features[w]; - uint64_t unavailable_features = requested_features & ~host_feat; + uint64_t unavailable_features; + + switch (w) { + case FEAT_14_1_EAX: + /* Handling the bits except INTEL_PT_ADDR_RANGES_NUM_MASK */ + unavailable_features = (requested_features & ~host_feat) & + ~INTEL_PT_ADDR_RANGES_NUM_MASK; + /* Bits 2:0 are as a whole to represent INTEL_PT_ADDR_RANGES */ + if ((requested_features & INTEL_PT_ADDR_RANGES_NUM_MASK) > + (host_feat & INTEL_PT_ADDR_RANGES_NUM_MASK)) { + unavailable_features |= requested_features & + INTEL_PT_ADDR_RANGES_NUM_MASK; + } + break; + default: + unavailable_features = requested_features & ~host_feat; + break; + } + mark_unavailable_features(cpu, w, unavailable_features, prefix); } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7201a71de863..500693eb9847 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -621,7 +621,10 @@ typedef enum FeatureWord { FEAT_VMX_EPT_VPID_CAPS, FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, + FEAT_14_0_EBX, FEAT_14_0_ECX, + FEAT_14_1_EAX, + FEAT_14_1_EBX, FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */ FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */ FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ From patchwork Wed May 31 08:43:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13261754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DCB0C77B7C for ; Wed, 31 May 2023 08:45:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4HQy-0002Dr-5n; Wed, 31 May 2023 04:43:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQW-000296-HH for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:29 -0400 Received: from mga06b.intel.com ([134.134.136.31] helo=mga06.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQU-0005fZ-8W for qemu-devel@nongnu.org; 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a="1036956432" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="1036956432" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga005.fm.intel.com with ESMTP; 31 May 2023 01:43:22 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chenyi Qiang , lei4.wang@intel.com Subject: [PATCH v4 4/8] target/i386/intel-pt: print special message for INTEL_PT_ADDR_RANGES_NUM Date: Wed, 31 May 2023 04:43:07 -0400 Message-Id: <20230531084311.3807277-5-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com> References: <20230531084311.3807277-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=xiaoyao.li@intel.com; helo=mga06.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Bit[2:0] of CPUID.14H_01H:EAX stands as a whole for the number of INTEL PT ADDR RANGES. For unsupported value that exceeds what KVM reports, report it as a whole in mark_unavailable_features() as well. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e735c366bc97..03471efee66b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4888,7 +4888,14 @@ static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, return; } - for (i = 0; i < 64; ++i) { + if ((w == FEAT_14_1_EAX) && (mask & INTEL_PT_ADDR_RANGES_NUM_MASK)) { + warn_report("%s: CPUID.14H_01H:EAX [bit 2:0]", verbose_prefix); + i = 3; + } else { + i = 0; + } + + for (; i < 64; ++i) { if ((1ULL << i) & mask) { g_autofree char *feat_word_str = feature_word_description(f, i); warn_report("%s: %s%s%s [bit %d]", From patchwork Wed May 31 08:43:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13261755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DCD4C7EE2F for ; Wed, 31 May 2023 08:46:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4HSw-0006NY-07; Wed, 31 May 2023 04:45:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQY-00029M-Ij for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:30 -0400 Received: from mga06b.intel.com ([134.134.136.31] helo=mga06.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQV-0005fO-RA for qemu-devel@nongnu.org; Wed, 31 May 2023 04:43:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685522607; x=1717058607; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ks5EXBLJa/uaxyfMQgNRGBftxob2zbvIKcIqiQJ+JbM=; b=dpjL8swdD85j50qNVK8T/+5nIf7fOnQZ8Ensn8EKEIXMM24FbZIQtGIE 9Xtl1fm7fHFkuImdINJ1VDVyp//LMZcrg1uZwwQsNF4BDkbQo7sRXpEdc zVKDVPFa9KUY9gWHHedKVufrd4iQ20Q7n/J4loz6ij+5kYr5Uwgx+MKjx b650l2cA5TV0uWUq7igGchaMxM0+YdomqxMdS8Vjloe9CTJYfuVwLFBUd wWkqlyPUzxQow/v4v5YIl5b9Okv3NnZCwlgpb3UH42hICtAPD8OnZE2hG AapBs3rVz/VRZ1l0v3vrkYGoY9zjcfXzZum5dSMf90cdiyQK9zdwcrSE6 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="418669283" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="418669283" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2023 01:43:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="1036956444" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="1036956444" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga005.fm.intel.com with ESMTP; 31 May 2023 01:43:24 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chenyi Qiang , lei4.wang@intel.com Subject: [PATCH v4 5/8] target/i386/intel-pt: Rework/rename the default INTEL-PT feature set Date: Wed, 31 May 2023 04:43:08 -0400 Message-Id: <20230531084311.3807277-6-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com> References: <20230531084311.3807277-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=xiaoyao.li@intel.com; helo=mga06.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Historically the Intel PT feature set reported from ICX silicon was chosen as the fixed feature set for Intel PT. If want to enable and expose INTEL-PT to guest, the supported Intel PT capabilities reported by KVM must cover this fixed feature set, which are named with MINIMAL in INTEL_PT_MINIMAL_EBX and INTEL_PT_MINIMAL_ECX. However, the name is inaccurate that it's more proper as default than minimal because SPR has less capabilities regarding CPUID(0x14,1):EBX[15:0]. Rename the feature set name to avoid future confusion and opportunistically define each feature bit. No functional change intended. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 70 ++++++++++++++++++++++------------------------- target/i386/cpu.h | 34 ++++++++++++++++++++++- 2 files changed, 65 insertions(+), 39 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03471efee66b..29dd79b16f6b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -549,34 +549,29 @@ static CPUCacheInfo legacy_l3_cache = { #define L2_ITLB_4K_ASSOC 4 #define L2_ITLB_4K_ENTRIES 512 -/* CPUID Leaf 0x14 constants: */ -#define INTEL_PT_MAX_SUBLEAF 0x1 -/* - * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH - * MSR can be accessed; - * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; - * bit[02]: Support IP Filtering, TraceStop filtering, and preservation - * of Intel PT MSRs across warm reset; - * bit[03]: Support MTC timing packet and suppression of COFI-based packets; - */ -#define INTEL_PT_MINIMAL_EBX 0xf -/* - * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and - * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be - * accessed; - * bit[01]: ToPA tables can hold any number of output entries, up to the - * maximum allowed by the MaskOrTableOffset field of - * IA32_RTIT_OUTPUT_MASK_PTRS; - * bit[02]: Support Single-Range Output scheme; - */ -#define INTEL_PT_MINIMAL_ECX 0x7 -/* generated packets which contain IP payloads have LIP values */ -#define INTEL_PT_IP_LIP (1 << 31) -#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ -#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 -#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ -#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ -#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ +/* INTEL PT definitions: */ + +#define INTEL_PT_MAX_SUBLEAF 0x1 + +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 +#define INTEL_PT_DEFAULT_ADDR_RANGES_NUM 0x2 + +/* Support ART(0,3,6,9) */ +#define INTEL_PT_DEFAULT_MTC_BITMAP (0x0249 << 16) +/* Support 0,2^(0~11) */ +#define INTEL_PT_DEFAULT_CYCLE_BITMAP 0x1fff +/* Support 2K,4K,8K,16K,32K,64K */ +#define INTEL_PT_DEFAULT_PSB_BITMAP (0x003f << 16) + +#define INTEL_PT_DEFAULT_0_EBX (CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB | \ + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC) + +#define INTEL_PT_DEFAULT_0_ECX (CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES | \ + CPUID_14_0_ECX_SINGLE_RANGE) + +#define INTEL_PT_DEFAULT_1_EAX (INTEL_PT_DEFAULT_MTC_BITMAP | INTEL_PT_DEFAULT_ADDR_RANGES_NUM) + +#define INTEL_PT_DEFAULT_1_EBX (INTEL_PT_DEFAULT_PSB_BITMAP | INTEL_PT_DEFAULT_CYCLE_BITMAP) /* CPUID Leaf 0x1D constants: */ #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 @@ -6250,14 +6245,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (count == 0) { *eax = INTEL_PT_MAX_SUBLEAF; - *ebx = INTEL_PT_MINIMAL_EBX; - *ecx = INTEL_PT_MINIMAL_ECX; + *ebx = INTEL_PT_DEFAULT_0_EBX; + *ecx = INTEL_PT_DEFAULT_0_ECX; if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { *ecx |= CPUID_14_0_ECX_LIP; } } else if (count == 1) { - *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; - *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; + *eax = INTEL_PT_DEFAULT_1_EAX; + *ebx = INTEL_PT_DEFAULT_1_EBX; } break; } @@ -7012,13 +7007,12 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); if (!eax_0 || - ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || - ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || - ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || + ((ebx_0 & INTEL_PT_DEFAULT_0_EBX) != INTEL_PT_DEFAULT_0_EBX) || + ((ecx_0 & INTEL_PT_DEFAULT_0_ECX) != INTEL_PT_DEFAULT_0_ECX) || + ((eax_1 & INTEL_PT_DEFAULT_MTC_BITMAP) != INTEL_PT_DEFAULT_MTC_BITMAP) || ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < - INTEL_PT_ADDR_RANGES_NUM) || - ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != - (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || + INTEL_PT_DEFAULT_ADDR_RANGES_NUM) || + ((ebx_1 & INTEL_PT_DEFAULT_1_EBX) != INTEL_PT_DEFAULT_1_EBX) || ((ecx_0 & CPUID_14_0_ECX_LIP) != (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { /* diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 500693eb9847..71b83102b75e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -938,8 +938,40 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) +/* + * IA32_RTIT_CTL.CR3 filter can be set to 1 and + * IA32_RTIT_CR3_MATCH can be accessed + */ +#define CPUID_14_0_EBX_CR3_FILTER (1U << 0) +/* Support Configurable PSB and Cycle-Accurate Mode */ +#define CPUID_14_0_EBX_PSB (1U << 1) +/* + * Support IP Filtering, IP TraceStop, and preservation + * of Intel PT MSRs across warm reset + */ +#define CPUID_14_0_EBX_IP_FILTER (1U << 2) +/* Support MTC timing packet */ +#define CPUID_14_0_EBX_MTC (1U << 3) +/* Support PTWRITE */ +#define CPUID_14_0_EBX_PTWRITE (1U << 4) +/* Support Power Event Trace packet generation */ +#define CPUID_14_0_EBX_POWER_EVENT (1U << 5) +/* Support PSB and PMI Preservation */ +#define CPUID_14_0_EBX_PSB_PMI_PRESERVATION (1U << 6) + +/* Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 */ +#define CPUID_14_0_ECX_TOPA (1U << 0) +/* + * ToPA tables can hold any number of output entries, up to the maximum allowed + * by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS + */ +#define CPUID_14_0_ECX_MULTI_ENTRIES (1U << 1) +/* Support Single-Range Output scheme */ +#define CPUID_14_0_ECX_SINGLE_RANGE (1U << 2) +/* Support IA32_RTIT_CTL.FabricEn */ +#define CPUID_14_0_ECX_TRACE_TRANS_SUBSYSTEM (1U << 3) /* Packets which contain IP payload have LIP values */ -#define CPUID_14_0_ECX_LIP (1U << 31) +#define CPUID_14_0_ECX_LIP (1U << 31) /* CLZERO instruction */ #define CPUID_8000_0008_EBX_CLZERO (1U << 0) From patchwork Wed May 31 08:43:09 2023 Content-Type: text/plain; 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a="1036956464" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="1036956464" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga005.fm.intel.com with ESMTP; 31 May 2023 01:43:26 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chenyi Qiang , lei4.wang@intel.com Subject: [PATCH v4 6/8] target/i386/intel-pt: Enable host pass through of Intel PT Date: Wed, 31 May 2023 04:43:09 -0400 Message-Id: <20230531084311.3807277-7-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com> References: <20230531084311.3807277-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=xiaoyao.li@intel.com; helo=mga06.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support") added the support of Intel PT by making CPUID[14] of PT as fixed feature set (from ICX) for any CPU model on any host. This truly breaks the PT exposure on Intel SPR platform because SPR has less supported bitmap of CPUID(0x14,1):EBX[15:0] than ICX. To fix the problem, enable pass through of host's PT capabilities for the cases "-cpu host/max" that it won't use default fixed PT feature set of ICX but expand automatically based on get_supported_cpuid() reported by KVM. Meanwhile, it needs to ensure (old) named CPU models still have the fixed Intel PT feature set to not break the live migration case of "-cpu named_cpu_model,+intel-pt" wiht old QEMU. To achieve this, assign default Intel PT feature values to named CPU models if no value defined in CPU models explicitly. In the future, new named CPU model, e.g., Sapphire Rapids, can define its own PT feature set by providing their own FEAT_14_0_EBX, FEAT_14_0_ECX, FEAT_14_1_EAX and FEAT_14_1_EBX. Signed-off-by: Xiaoyao Li --- Changes in v4: - drop use_default_intel_pt flag and the handling of validating final env->features[FEAT_14*] matches with INTEL_PT_DEFAULT_*. It's found unnecessary because old QEMU has no ability to customize Intel PT feature set with +/-feature. --- target/i386/cpu.c | 62 ++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 33 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 29dd79b16f6b..e47629aff68e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5723,6 +5723,24 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) env->features[w] = def->features[w]; } + /* + * All (old) named CPU models have the same default values for INTEL_PT if + * the leaf values are not explicitly specified. + * + * Assign the default value here since we don't want to manually copy/paste + * it to all entries in builtin_x86_defs[]. + * + * It's safe to set values for Intel PT leaves here because they will be + * cleared due to feature_dependencies if CPUID_7_0_EBX_INTEL_PT is absent. + */ + if (!env->features[FEAT_14_0_EBX] && !env->features[FEAT_14_0_ECX] && + !env->features[FEAT_14_1_EAX] && !env->features[FEAT_14_1_EBX]) { + env->features[FEAT_14_0_EBX] = INTEL_PT_DEFAULT_0_EBX; + env->features[FEAT_14_0_ECX] = INTEL_PT_DEFAULT_0_ECX; + env->features[FEAT_14_1_EAX] = INTEL_PT_DEFAULT_1_EAX; + env->features[FEAT_14_1_EBX] = INTEL_PT_DEFAULT_1_EBX; + } + /* legacy-cache defaults to 'off' if CPU model provides cache info */ cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); @@ -6245,14 +6263,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (count == 0) { *eax = INTEL_PT_MAX_SUBLEAF; - *ebx = INTEL_PT_DEFAULT_0_EBX; - *ecx = INTEL_PT_DEFAULT_0_ECX; - if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { - *ecx |= CPUID_14_0_ECX_LIP; - } + *ebx = env->features[FEAT_14_0_EBX]; + *ecx = env->features[FEAT_14_0_ECX]; } else if (count == 1) { - *eax = INTEL_PT_DEFAULT_1_EAX; - *ebx = INTEL_PT_DEFAULT_1_EBX; + *eax = env->features[FEAT_14_1_EAX]; + *ebx = env->features[FEAT_14_1_EBX]; } break; } @@ -6964,6 +6979,7 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) CPUX86State *env = &cpu->env; FeatureWord w; const char *prefix = NULL; + uint64_t host_feat; if (verbose) { prefix = accel_uses_host_cpuid() @@ -6972,8 +6988,7 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) } for (w = 0; w < FEATURE_WORDS; w++) { - uint64_t host_feat = - x86_cpu_get_supported_feature_word(w, false); + host_feat = x86_cpu_get_supported_feature_word(w, false); uint64_t requested_features = env->features[w]; uint64_t unavailable_features; @@ -6997,30 +7012,11 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) mark_unavailable_features(cpu, w, unavailable_features, prefix); } - if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && - kvm_enabled()) { - KVMState *s = CPU(cpu)->kvm_state; - uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); - uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); - uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); - uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); - uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); - - if (!eax_0 || - ((ebx_0 & INTEL_PT_DEFAULT_0_EBX) != INTEL_PT_DEFAULT_0_EBX) || - ((ecx_0 & INTEL_PT_DEFAULT_0_ECX) != INTEL_PT_DEFAULT_0_ECX) || - ((eax_1 & INTEL_PT_DEFAULT_MTC_BITMAP) != INTEL_PT_DEFAULT_MTC_BITMAP) || - ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < - INTEL_PT_DEFAULT_ADDR_RANGES_NUM) || - ((ebx_1 & INTEL_PT_DEFAULT_1_EBX) != INTEL_PT_DEFAULT_1_EBX) || - ((ecx_0 & CPUID_14_0_ECX_LIP) != - (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { - /* - * Processor Trace capabilities aren't configurable, so if the - * host can't emulate the capabilities we report on - * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. - */ - mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { + host_feat = x86_cpu_get_supported_feature_word(FEAT_14_0_ECX, false); + if ((env->features[FEAT_14_0_ECX] ^ host_feat) & CPUID_14_0_ECX_LIP) { + warn_report("Cannot configure different Intel PT IP payload format than hardware"); + mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, NULL); } } } From patchwork Wed May 31 08:43:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13261752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1BCEC7EE2F for ; Wed, 31 May 2023 08:44:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4HQf-0002As-6s; Wed, 31 May 2023 04:43:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4HQa-0002AF-US for qemu-devel@nongnu.org; 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d="scan'208";a="418669307" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2023 01:43:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="1036956478" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="1036956478" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga005.fm.intel.com with ESMTP; 31 May 2023 01:43:28 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chenyi Qiang , lei4.wang@intel.com Subject: [PATCH v4 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server, Snowridge and SapphireRapids Date: Wed, 31 May 2023 04:43:10 -0400 Message-Id: <20230531084311.3807277-8-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com> References: <20230531084311.3807277-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=xiaoyao.li@intel.com; helo=mga06.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For IceLake-server, it's just the same as using the default PT feature set since the default one is exact taken from ICX. For Snowridge and SapphireRapids, define it according to real silicon capabilities. Signed-off-by: Xiaoyao Li --- Changes in v4: - Add Intel PT capabilities for SapphireRapids cpu model; --- target/i386/cpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e47629aff68e..182ba02e2fee 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3699,6 +3699,14 @@ static const X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ + .features[FEAT_14_0_EBX] = + CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB | + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC, + .features[FEAT_14_0_ECX] = + CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES | + CPUID_14_0_ECX_SINGLE_RANGE, + .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2, + .features[FEAT_14_1_EBX] = 0x003f << 16 | 0x1fff, .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | @@ -3869,6 +3877,15 @@ static const X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_7_1_EAX] = CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, + .features[FEAT_14_0_EBX] = + CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB | + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC | + CPUID_14_0_EBX_PTWRITE | CPUID_14_0_EBX_PSB_PMI_PRESERVATION, + .features[FEAT_14_0_ECX] = + CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES | + CPUID_14_0_ECX_SINGLE_RANGE, + .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2, + .features[FEAT_14_1_EBX] = 0x003f << 16 | 0x3f, .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, .features[FEAT_VMX_ENTRY_CTLS] = @@ -4105,6 +4122,16 @@ static const X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XGETBV1, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, + .features[FEAT_14_0_EBX] = + CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB | + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC | + CPUID_14_0_EBX_PTWRITE | CPUID_14_0_EBX_POWER_EVENT | + CPUID_14_0_EBX_PSB_PMI_PRESERVATION, + .features[FEAT_14_0_ECX] = + CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES | + CPUID_14_0_ECX_SINGLE_RANGE | CPUID_14_0_ECX_LIP, + .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2, + .features[FEAT_14_1_EBX] = 0x003f << 16 | 0xffff, .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | From patchwork Wed May 31 08:43:11 2023 Content-Type: text/plain; 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a="1036956500" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="1036956500" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga005.fm.intel.com with ESMTP; 31 May 2023 01:43:30 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chenyi Qiang , lei4.wang@intel.com Subject: [PATCH v4 8/8] target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID configuration Date: Wed, 31 May 2023 04:43:11 -0400 Message-Id: <20230531084311.3807277-9-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com> References: <20230531084311.3807277-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.31; envelope-from=xiaoyao.li@intel.com; helo=mga06.intel.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org KVM only allows userspace to access legal number of MSR_IA32_RTIT_ADDRn, which is enumrated by guest's CPUID(0x14,0x1):EAX[2:0], i.e., env->features[FEAT_14_1_EAX] & INTEL_PT_ADDR_RANGES_NUM_MASK Signed-off-by: Xiaoyao Li --- target/i386/cpu.h | 2 ++ target/i386/kvm/kvm.c | 8 ++++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 71b83102b75e..d745ba2ad77a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -973,6 +973,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 + /* CLZERO instruction */ #define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* Always save/restore FP error pointers */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index de531842f6b1..e68846100ddb 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3561,8 +3561,8 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } } if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { - int addr_num = kvm_arch_get_supported_cpuid(kvm_state, - 0x14, 1, R_EAX) & 0x7; + int addr_num = env->features[FEAT_14_1_EAX] & + INTEL_PT_ADDR_RANGES_NUM_MASK; kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, env->msr_rtit_ctrl); @@ -4004,8 +4004,8 @@ static int kvm_get_msrs(X86CPU *cpu) } if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { - int addr_num = - kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7; + int addr_num = env->features[FEAT_14_1_EAX] & + INTEL_PT_ADDR_RANGES_NUM_MASK; kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0); kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);