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Peter Anvin" , Josh Poimboeuf , Kees Cook , Andrea Arcangeli , Waiman Long , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jon Kohler , Josh Poimboeuf Subject: [PATCH v4] KVM: VMX: do not disable interception for MSR_IA32_SPEC_CTRL on eIBRS Date: Wed, 31 May 2023 10:41:28 -0400 Message-Id: <20230531144128.73814-1-jon@nutanix.com> X-Mailer: git-send-email 2.30.1 (Apple Git-130) X-ClientProxiedBy: BY5PR16CA0030.namprd16.prod.outlook.com (2603:10b6:a03:1a0::43) To BL0PR02MB4579.namprd02.prod.outlook.com (2603:10b6:208:4b::10) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL0PR02MB4579:EE_|DM8PR02MB8247:EE_ X-MS-Office365-Filtering-Correlation-Id: ed03333d-6c15-40f6-d731-08db61e526e0 x-proofpoint-crosstenant: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BV+Ne0dQqEwk1HjlBZh28GazeHpwg1kh1PwSCM4JmxbAXqcznmrs9vJL5IPwmvpSO/FUblJP87et5WFU4yOzudn9Et1Uh1onB4G+Az3Zkzo3mi++P0EcyhXpgo8mkbjclmpWJVQgadcQbY3RbS/VhATxOoBBNQ24+wR0v51/FwEA1iZbOoss/ZQDH5+IuAUnhbwZWWHAd+kqe1snbyWALlEk2snTp+TVr2CkdA6zDF2GBCxKtu2ThWv9TjpIp6YcGzX4M52RM7+R+zSFke9VJ3jf8EYqOW4mYMJ6MvgOQPYcEZhyAK6KiZPtyjiYIZJmpYRJkHteIH5wb/M8a7391DouaCqxnPx380/Ky6Tn6OiJ0lLjfNnk4c15BTvAj6BKH+vUTCYiqLuT8y/zTGO6XrQE2IFSDUfhGHUuWwwW9TYEXtit+oS9GeU1a22ZqCGuJyE7SYtnYNNGUuOIYm5z46YZfFdrIWAkQXws7CVZTv+AazpGIFGzqH67fUY055i3Vc8jzs5ycXZ/J0vC4/zHi6565M9s8wnv8rj2XN9IcG+VNLE3wlHi9sw4BeaIZyvoBI4OL0r//R2a7yGg6w8xyxADhKifsQbivNj7zKQXOeXYU7Vccyo+wE1fd/qBTES9 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BL0PR02MB4579.namprd02.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(376002)(396003)(366004)(136003)(346002)(39860400002)(451199021)(2906002)(186003)(6512007)(6506007)(921005)(5660300002)(8676002)(8936002)(38100700002)(110136005)(2616005)(54906003)(1076003)(83380400001)(966005)(6486002)(86362001)(52116002)(41300700001)(4326008)(316002)(6666004)(66946007)(7416002)(36756003)(66556008)(66476007)(478600001);DIR:OUT;SFP:1102; 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Note: this logic is only for eIBRS, as Intel's guidance has long been that eIBRS only needs to be set once, so most guests with eIBRS awareness should behave nicely. We would not want to accidentally regress misbehaving guests on pre-eIBRS systems, who might be spamming IBRS MSR without the hypervisor being able to see it today. eIBRS enabled guests using just IBRS will only write SPEC_CTRL MSR once or twice per vCPU on boot, so it is far better to take those VM exits on boot than having to read and save this msr on every single VM exit forever. This outcome was suggested on Andrea's commit 2f46993d83ff ("x86: change default to spec_store_bypass_disable=prctl spectre_v2_user=prctl") however, since interception is still unilaterally disabled, the rdmsr tax is still there even after that commit. This is a significant win for eIBRS enabled systems as this rdmsr accounts for roughly ~50% of time for vmx_vcpu_run() as observed by perf top disassembly, and is in the critical path for all VM-Exits, including fastpath exits. Opportunistically update comments for both MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD to make it clear how L1 vs L2 handling works. Fixes: 2f46993d83ff ("x86: change default to spec_store_bypass_disable=prctl spectre_v2_user=prctl") Signed-off-by: Jon Kohler Cc: Sean Christopherson Cc: Andrea Arcangeli Cc: Kees Cook Cc: Josh Poimboeuf Cc: Waiman Long Acked-by: Josh Poimboeuf --- v1 - https://lore.kernel.org/all/20220512174427.3608-1-jon@nutanix.com/ v1 -> v2: - https://lore.kernel.org/all/20220520195303.58692-1-jon@nutanix.com/ - Addressed comments on approach from Sean. v2 -> v3: - https://lore.kernel.org/kvm/20220520204115.67580-1-jon@nutanix.com/ - Addressed comments on approach from Sean. v3 -> v4: - Fixed inline code comments from Sean. arch/x86/kvm/vmx/vmx.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) -- 2.30.1 (Apple Git-130) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 44fb619803b8..5e643ac897bc 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2260,20 +2260,33 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return 1; vmx->spec_ctrl = data; - if (!data) + + /* + * Disable interception on the first non-zero write, except if + * eIBRS is advertised to the guest and the guest is enabling + * _only_ IBRS. On eIBRS systems, kernels typically set IBRS + * once at boot and never touch it post-boot. All other bits, + * and IBRS on non-eIBRS systems, are often set on a per-task + * basis, i.e. change frequently, so the benefit of avoiding + * VM-exits during guest context switches outweighs the cost of + * RDMSR on every VM-Exit to save the guest's value. + */ + if (!data || + (data == SPEC_CTRL_IBRS && + (vcpu->arch.arch_capabilities & ARCH_CAP_IBRS_ALL))) break; /* - * For non-nested: - * When it's written (to non-zero) for the first time, pass - * it through. - * - * For nested: - * The handling of the MSR bitmap for L2 guests is done in - * nested_vmx_prepare_msr_bitmap. We should not touch the - * vmcs02.msr_bitmap here since it gets completely overwritten - * in the merging. We update the vmcs01 here for L1 as well - * since it will end up touching the MSR anyway now. + * Update vmcs01.msr_bitmap even if L2 is active, i.e. disable + * interception for the vCPU on the first write regardless of + * whether the WRMSR came from L1 or L2. vmcs02's bitmap is a + * combination of vmcs01 and vmcs12 bitmaps, and will be + * recomputed by nested_vmx_prepare_msr_bitmap() on the next + * nested VM-Enter. Note, this does mean that future WRMSRs + * from L2 will be intercepted until the next nested VM-Exit if + * L2 was the first to write, but L1 exposing the MSR to L2 + * without first writing it is unlikely and not worth the + * extra bit of complexity. */ vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL,