From patchwork Fri Jun 2 17:01:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colton Lewis X-Patchwork-Id: 13265708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE28EC7EE29 for ; Fri, 2 Jun 2023 17:02:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236932AbjFBRCz (ORCPT ); Fri, 2 Jun 2023 13:02:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236912AbjFBRCx (ORCPT ); Fri, 2 Jun 2023 13:02:53 -0400 Received: from mail-io1-xd4a.google.com (mail-io1-xd4a.google.com [IPv6:2607:f8b0:4864:20::d4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 786ED1B3 for ; Fri, 2 Jun 2023 10:02:52 -0700 (PDT) Received: by mail-io1-xd4a.google.com with SMTP id ca18e2360f4ac-77751dc936eso118203539f.0 for ; Fri, 02 Jun 2023 10:02:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685725371; x=1688317371; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=DZrtPESLe1mA5daPGrUc+60GXQlGnhOLsAUJu36d7rQ=; b=Qq3RLBS2mk0SnALShNCtm+TQlg+XH/AHekNH7/7QlGAv3Kwq/6fPi6+CvfRavpIs4G RjyTeXe+0RGaZAufFJ8EvFNFa8pOjeTTjjb8sD9rItu1zRExurnNtBOtX6w1QJedD+7I afR/Bn/wNwB2NO7fNerz8ES6XgY4MyN711P03otg/ynXmiG0KHjiA/NCjGChETeqa8Sq PPIW2euhDqJ/s3oFviuWT4EcIxz18d4QuSIOimUwO4KwNQ9xdjmAWN3FZO+WhB+n8/fm Z+b1LzGrVLf99x0xH1gni5y4fL0Jf+jIx8h2sro9EeSCJDdt5AbgU5s/l97G1yjsUE5q 7IyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685725371; x=1688317371; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=DZrtPESLe1mA5daPGrUc+60GXQlGnhOLsAUJu36d7rQ=; b=OSH+5k+x2nAsFnVXayJhGNOIWZCApcbdI0QkzgysEwoclG2nYlmuGZsVs8kdPuo08q wV3Orsge9nKefe+hpRP/OoPOFRAzkEvYu9DqeNCu6V0p8GF3hRCA+GFty0PVknPQ1KVA o+7k0k6r94AAD5UJk5AyOxYM0goPjm/PbRNlON3KJ1SBhsheiX6z/nmNOPemCX48A192 5n2WV8Z5H763prkH8N+En3XMt2lnHTuVNNUfEA3hmryzgu3AWmPlFZAgkhrKwJxuORTc X1rAsybLN1VGfqCwWEbJDPnLkCvKvvvybvbq0OTz1ac5+fkKnPIUGGgDJDqXPeASsHI5 FiFg== X-Gm-Message-State: AC+VfDyUyeV3vQ5RQ6oFPzmp0qGkzL5Pb1R0g0yzDKsWLjD+LGGG9A/S B7AkIHYjAwauRgqSyd9TR/LVsWng4KcxQwmgssxgEcYVnb9SpxgS0/JgVnhSj0XCZCh+5EBAkTf snM2KghSouVOpEmHY85aCt5QNpnxDW3O/WKX/oJdgZKOSlxwVCi1f4k6QrB7PNDh+10TM2Z0= X-Google-Smtp-Source: ACHHUZ7jQlp0MVeJbVOdhempnaGESwJq6ISHR98G4dlzn8EXHZtiMaS3iQFnqJ6k1wVSGZ9JZpTQJ2Y+ISmEsdfLAw== X-Received: from coltonlewis-kvm.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:14ce]) (user=coltonlewis job=sendgmr) by 2002:a6b:5904:0:b0:766:6741:8849 with SMTP id n4-20020a6b5904000000b0076667418849mr1203200iob.3.1685725371731; Fri, 02 Jun 2023 10:02:51 -0700 (PDT) Date: Fri, 2 Jun 2023 17:01:45 +0000 In-Reply-To: <20230602170147.1541355-1-coltonlewis@google.com> Mime-Version: 1.0 References: <20230602170147.1541355-1-coltonlewis@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230602170147.1541355-2-coltonlewis@google.com> Subject: [PATCH 1/3] arm64: Add a capability for FEAT_BBM level 2 From: Colton Lewis To: kvm@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, Ricardo Koller Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Ricardo Koller Add a new capability to detect "Stage-2 Translation table break-before-make" (FEAT_BBM) level 2. Signed-off-by: Ricardo Koller --- arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 12 insertions(+) -- 2.41.0.rc0.172.g3f132b7071-goog diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c331c49a7d19c..c538060f7f66b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2455,6 +2455,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .min_field_value = 1, .matches = has_cpuid_feature, }, + { + .desc = "Stage-2 Translation table break-before-make level 2", + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .capability = ARM64_HAS_STAGE2_BBM2, + .sys_reg = SYS_ID_AA64MMFR2_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR2_EL1_BBM_SHIFT, + .field_width = 4, + .min_field_value = 2, + .matches = has_cpuid_feature, + }, { .desc = "TLB range maintenance instructions", .capability = ARM64_HAS_TLB_RANGE, diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 40ba95472594d..010aca1892642 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -41,6 +41,7 @@ HAS_PAN HAS_RAS_EXTN HAS_RNG HAS_SB +HAS_STAGE2_BBM2 HAS_STAGE2_FWB HAS_TIDCP1 HAS_TLB_RANGE From patchwork Fri Jun 2 17:01:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colton Lewis X-Patchwork-Id: 13265709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B06B5C7EE24 for ; Fri, 2 Jun 2023 17:02:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236939AbjFBRC6 (ORCPT ); Fri, 2 Jun 2023 13:02:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236919AbjFBRCy (ORCPT ); Fri, 2 Jun 2023 13:02:54 -0400 Received: from mail-il1-x14a.google.com (mail-il1-x14a.google.com [IPv6:2607:f8b0:4864:20::14a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B1031B9 for ; Fri, 2 Jun 2023 10:02:53 -0700 (PDT) Received: by mail-il1-x14a.google.com with SMTP id e9e14a558f8ab-33b59d59193so20406425ab.0 for ; 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Fri, 02 Jun 2023 10:02:52 -0700 (PDT) Date: Fri, 2 Jun 2023 17:01:46 +0000 In-Reply-To: <20230602170147.1541355-1-coltonlewis@google.com> Mime-Version: 1.0 References: <20230602170147.1541355-1-coltonlewis@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230602170147.1541355-3-coltonlewis@google.com> Subject: [PATCH 2/3] KVM: arm64: Clear possible conflict aborts From: Colton Lewis To: kvm@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, Colton Lewis Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Clear possible conflict aborts by TLB invalidation targeted to the address that caused the abort. Making use of FEAT_BBM Level 2 creates the possibility of a conflict abort when translating addresses, where multiple entries exist in the TLB for a single input address. Signed-off-by: Colton Lewis --- arch/arm64/include/asm/esr.h | 1 + arch/arm64/kvm/mmu.c | 6 ++++++ 2 files changed, 7 insertions(+) -- 2.41.0.rc0.172.g3f132b7071-goog diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 8487aec9b6587..41336cfa19ff3 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -123,6 +123,7 @@ #define ESR_ELx_FSC_SECC_TTW1 (0x1d) #define ESR_ELx_FSC_SECC_TTW2 (0x1e) #define ESR_ELx_FSC_SECC_TTW3 (0x1f) +#define ESR_ELx_FSC_CONFLICT (0x30) /* ISS field definitions for Data Aborts */ #define ESR_ELx_ISV_SHIFT (24) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 7a68398517c95..96b950f20c8d0 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1591,6 +1591,12 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) return 1; } + if (fault_status == ESR_ELx_FSC_CONFLICT) { + /* We could be at any level. 0 covers all levels. */ + __kvm_tlb_flush_vmid_ipa(vcpu->arch.hw_mmu, fault_ipa, 0); + return 1; + } + trace_kvm_guest_fault(*vcpu_pc(vcpu), kvm_vcpu_get_esr(vcpu), kvm_vcpu_get_hfar(vcpu), fault_ipa); From patchwork Fri Jun 2 17:01:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colton Lewis X-Patchwork-Id: 13265710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A095C7EE2A for ; Fri, 2 Jun 2023 17:03:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236913AbjFBRDA (ORCPT ); Fri, 2 Jun 2023 13:03:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236933AbjFBRC4 (ORCPT ); Fri, 2 Jun 2023 13:02:56 -0400 Received: from mail-io1-xd4a.google.com (mail-io1-xd4a.google.com [IPv6:2607:f8b0:4864:20::d4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FB621A5 for ; Fri, 2 Jun 2023 10:02:54 -0700 (PDT) Received: by mail-io1-xd4a.google.com with SMTP id ca18e2360f4ac-7603d830533so81079639f.1 for ; Fri, 02 Jun 2023 10:02:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685725374; x=1688317374; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=46U2EWEjxn55kWeKsj3lDgLNoam846hFcVZO+vAwdLA=; b=WAqGXaWPraSA2daImKoen5B6tdZ+WYHgTjxhUUeeZAsbrniK5QsoJdy6bnYalQom0q MTUHUxan0x428dbLSXOSDczGl+sVACZNDReIhyFVk8qGv8O19J818JqDUV+L39pYvd+O +D0peOAv5LwnSHuhbBKS4on+Spl3k1vhxR2tQ3f+hr+YwUTyNz098zCnNqlglZ99wmXF 03RZCAfLMqzIZPxHZwDc+9cJzrwA0lt7idYGl5Mr8XHmSaECCNan2CtJJnr3I5Ts2P2r magwgDPHCmtfLDNKqCKxBMgHtvBcTUMA++iZxC/lrSlB4KiCVknekWOPC0oT6ZjtI3V8 dGqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685725374; x=1688317374; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=46U2EWEjxn55kWeKsj3lDgLNoam846hFcVZO+vAwdLA=; b=Jr6y+PXXb9qPXba1j/N3dtXhfmSiM3SJ14YA8gqPvEzI+/UxI33oTIzk+wr56NLvyu ZyaVTUmbd5DA4sbgVTyqw1M49IZMollXsnl8wiHGsSrrnbvZQKGLbWeaZTLc7mCMkY8i mZy0zhkgLOwLs3N0bx/tfDpD+I2lyzTS+0mXSAfO5qjNzjjAO5huqgca0IINpDsGhG1m TJN8lnAJTMemYNnN8sEr5Wwa29tUXWdm6MQD2YIvs3UzvLAEsuJff4asBz0wT4IhGD26 kefYNmPtm3wP5vZFen6NG+G+hBnvTLaBpjGyHR5osEhB98okf+lF+tTyAp+xAIhY/WZy o/dA== X-Gm-Message-State: AC+VfDwDRtNjMn5p6NLady4fkr4fBv2ZlKcppk3sS2BQb0sa3BCkverR U62IYTmB+VeaahHNHHut5O/oBA70ZXrxIcFm8dM3a3LP98pIIUYGQ54ehXQJa2SyAMyo3iZq9qm ol4ratOOmt+ZfdCEXQ91pXyqrV5cYnvThiLiXE5y66KRlfpasFO66bm2CbgupoDs5oo3zXH8= X-Google-Smtp-Source: ACHHUZ4geDJMOIvtQH6zUtgqB8OHUq2dHYHBZAw17LyumZCyIixhJcFdC+UZZW8jvomo19VQYFFEQblUZyGsWdbTIA== X-Received: from coltonlewis-kvm.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:14ce]) (user=coltonlewis job=sendgmr) by 2002:a05:6602:1503:b0:777:2367:a7d3 with SMTP id g3-20020a056602150300b007772367a7d3mr1813249iow.0.1685725373854; Fri, 02 Jun 2023 10:02:53 -0700 (PDT) Date: Fri, 2 Jun 2023 17:01:47 +0000 In-Reply-To: <20230602170147.1541355-1-coltonlewis@google.com> Mime-Version: 1.0 References: <20230602170147.1541355-1-coltonlewis@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230602170147.1541355-4-coltonlewis@google.com> Subject: [PATCH 3/3] KVM: arm64: Skip break phase when we have FEAT_BBM level 2 From: Colton Lewis To: kvm@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, Colton Lewis Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Skip the break phase of break-before-make when the CPU has FEAT_BBM level 2. This allows skipping some expensive invalidation and serialization and should result in significant performance improvements when changing block size. The ARM manual section D5.10.1 specifically states under heading "Support levels for changing block size" that FEAT_BBM Level 2 support means changing block size does not break coherency, ordering guarantees, or uniprocessor semantics. Because a compare-and-exchange operation was used in the break phase to serialize access to the PTE, an analogous compare-and-exchange is introduced in the make phase to ensure serialization remains even if the break phase is skipped and proper handling is introduced to account for this function now having a way to fail. Considering the possibility that the new pte has different permissions than the old pte, the minimum necessary tlb invalidations are used. Signed-off-by: Colton Lewis --- arch/arm64/kvm/hyp/pgtable.c | 58 +++++++++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 7 deletions(-) -- 2.41.0.rc0.172.g3f132b7071-goog diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index 8acab89080af9..6778e3df697f7 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -643,6 +643,11 @@ static bool stage2_has_fwb(struct kvm_pgtable *pgt) return !(pgt->flags & KVM_PGTABLE_S2_NOFWB); } +static bool stage2_has_bbm_level2(void) +{ + return cpus_have_const_cap(ARM64_HAS_STAGE2_BBM2); +} + #define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt)) static int stage2_set_prot_attr(struct kvm_pgtable *pgt, enum kvm_pgtable_prot prot, @@ -730,7 +735,7 @@ static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_ * @ctx: context of the visited pte. * @mmu: stage-2 mmu * - * Returns: true if the pte was successfully broken. + * Returns: true if the pte was successfully broken or there is no need. * * If the removed pte was valid, performs the necessary serialization and TLB * invalidation for the old value. For counted ptes, drops the reference count @@ -750,6 +755,10 @@ static bool stage2_try_break_pte(const struct kvm_pgtable_visit_ctx *ctx, return false; } + /* There is no need to break the pte. */ + if (stage2_has_bbm_level2()) + return true; + if (!stage2_try_set_pte(ctx, KVM_INVALID_PTE_LOCKED)) return false; @@ -771,16 +780,45 @@ static bool stage2_try_break_pte(const struct kvm_pgtable_visit_ctx *ctx, return true; } -static void stage2_make_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) +static bool stage2_pte_perms_equal(kvm_pte_t p1, kvm_pte_t p2) +{ + u64 perms1 = p1 & KVM_PGTABLE_PROT_RWX; + u64 perms2 = p2 & KVM_PGTABLE_PROT_RWX; + + return perms1 == perms2; +} + +/** + * stage2_try_make_pte() - Attempts to install a new pte. + * + * @ctx: context of the visited pte. + * @new: new pte to install + * + * Returns: true if the pte was successfully installed + * + * If the old pte had different permissions, perform appropriate TLB + * invalidation for the old value. For counted ptes, drops the + * reference count on the containing table page. + */ +static bool stage2_try_make_pte(const struct kvm_pgtable_visit_ctx *ctx, struct kvm_s2_mmu *mmu, kvm_pte_t new) { struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops; - WARN_ON(!stage2_pte_is_locked(*ctx->ptep)); + if (!stage2_has_bbm_level2()) + WARN_ON(!stage2_pte_is_locked(*ctx->ptep)); + + if (!stage2_try_set_pte(ctx, new)) + return false; + + if (kvm_pte_table(ctx->old, ctx->level)) + kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); + else if (kvm_pte_valid(ctx->old) && !stage2_pte_perms_equal(ctx->old, new)) + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa_nsh, mmu, ctx->addr, ctx->level); if (stage2_pte_is_counted(new)) mm_ops->get_page(ctx->ptep); - smp_store_release(ctx->ptep, new); + return true; } static void stage2_put_pte(const struct kvm_pgtable_visit_ctx *ctx, struct kvm_s2_mmu *mmu, @@ -879,7 +917,8 @@ static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx, stage2_pte_executable(new)) mm_ops->icache_inval_pou(kvm_pte_follow(new, mm_ops), granule); - stage2_make_pte(ctx, new); + if (!stage2_try_make_pte(ctx, data->mmu, new)) + return -EAGAIN; return 0; } @@ -934,7 +973,9 @@ static int stage2_map_walk_leaf(const struct kvm_pgtable_visit_ctx *ctx, * will be mapped lazily. */ new = kvm_init_table_pte(childp, mm_ops); - stage2_make_pte(ctx, new); + + if (!stage2_try_make_pte(ctx, data->mmu, new)) + return -EAGAIN; return 0; } @@ -1385,7 +1426,10 @@ static int stage2_split_walker(const struct kvm_pgtable_visit_ctx *ctx, * writes the PTE using smp_store_release(). */ new = kvm_init_table_pte(childp, mm_ops); - stage2_make_pte(ctx, new); + + if (!stage2_try_make_pte(ctx, mmu, new)) + return -EAGAIN; + dsb(ishst); return 0; }