From patchwork Wed Jun 7 19:45:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13271189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0A06C77B7A for ; Wed, 7 Jun 2023 19:46:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231493AbjFGTqD (ORCPT ); Wed, 7 Jun 2023 15:46:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231458AbjFGTqC (ORCPT ); Wed, 7 Jun 2023 15:46:02 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E106D1FE0 for ; Wed, 7 Jun 2023 12:46:00 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5689bcc5f56so117021757b3.2 for ; Wed, 07 Jun 2023 12:46:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686167160; x=1688759160; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=hzxVwxnrNt+YQp7iV0J7o3+qKksOkJQBVAdrxipkKZg=; b=fMZYG2zR8/wyVaV7AOWU2176k/b30yDMKXHbC/LdYCNKxTdoLKCXlQ6JSsEJpKCovx u9u+W+rKoRyLy9Nud2MHk1nP4o/c3i4sFDaqNU5Tz18ncnoHJWBcV7YBp35rYblNSMrB Srt2tjPaFXVZin7mr/aGXsbIXt58qgfwgTEdJPUyg6mM2OwgX47KdIHSaIQqmi0eqIPL 5v2P2BX/GBKy3oqa1yCJwfGXELL6EMogyVQSIkmTzCQjg5UWFxSp21LfjJpQZem0aQR2 wMmq8AKiEtvscrwUGTY8A+yxh1qWK/2oPM6gQEZ/Tb/oHE/8BwS7FZkxI6PRefMOjJOI XiPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686167160; x=1688759160; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=hzxVwxnrNt+YQp7iV0J7o3+qKksOkJQBVAdrxipkKZg=; b=SFpqXKCnmFyM4XgkmlwWTObC9UCLtVRDsXgwdEWc2yUyqxqo1hiPaFIEd5qI0ODsjm w5t0Twq1Sb2BzuJTdKQGOYOyZU17S1ouGyOROEFt+/oMtQfdOE0vvT+tScsfnmecTlgl F9g3rxjb+zwC3x27Xru9xG1O6OHG6YU/cqVQySOQdWJzLnIuseXkfnmOCZ+KVv8KHU8a o3oNViAWc5hOwKIy5U+2R+keb0Cf4vEGoSTOWP4A2xJkjI3fzxKTSYuqkL6hFCHIfaes Vd0ST4HmN0yFToor8RnDn2bmciDpqLs5RmXUr0xpK8u0meHV6hs1kwGWOJn7jM0MpckM uEwQ== X-Gm-Message-State: AC+VfDwBDs2jvK6LATiXXdXmLotzb1PJnkgzZPnTBVW50vcq/gzKxEQV mdeY5jVpRq5oiHB3hp2u8Cmj/6GtHvq1bxL23bSsPMJpHqNTB6yTb+AYLjGMShPitSCywSyDEi4 lQP1HdKXcQSTpEIottXE8Gf3VKoKlxsU0IS7Andcbct59uo2frxBoqJJtPpfjF5qrKF+yI/0= X-Google-Smtp-Source: ACHHUZ6V41FX37D247KNGDPz31teBiVq6V+3LyWxqzaVMHNbR4cZ9zys4EkzeS1q16KMxoLnqrscogFEIf4yfE0S0w== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a81:ae17:0:b0:568:9bcc:5e16 with SMTP id m23-20020a81ae17000000b005689bcc5e16mr3400413ywh.2.1686167159720; Wed, 07 Jun 2023 12:45:59 -0700 (PDT) Date: Wed, 7 Jun 2023 19:45:51 +0000 In-Reply-To: <20230607194554.87359-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230607194554.87359-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230607194554.87359-2-jingzhangos@google.com> Subject: [PATCH v4 1/4] KVM: arm64: Enable writable for ID_AA64DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since number of context-aware breakpoints must be no more than number of supported breakpoints according to Arm ARM, return an error if userspace tries to set CTX_CMPS field to such value. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 50d4e25f42d3..a6299c796d03 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1539,9 +1539,14 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { - u8 pmuver, host_pmuver; + u8 pmuver, host_pmuver, brps, ctx_cmps; bool valid_pmu; + brps = FIELD_GET(ID_AA64DFR0_EL1_BRPs_MASK, val); + ctx_cmps = FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs_MASK, val); + if (ctx_cmps > brps) + return -EINVAL; + host_pmuver = kvm_arm_pmu_get_pmuver_limit(); /* @@ -2061,7 +2066,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, .reset = read_sanitised_id_aa64dfr0_el1, - .val = ID_AA64DFR0_EL1_PMUVer_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), ID_UNALLOCATED(5,3), From patchwork Wed Jun 7 19:45:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13271190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB521C7EE23 for ; Wed, 7 Jun 2023 19:46:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231565AbjFGTqF (ORCPT ); Wed, 7 Jun 2023 15:46:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231458AbjFGTqE (ORCPT ); Wed, 7 Jun 2023 15:46:04 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08F05101 for ; Wed, 7 Jun 2023 12:46:03 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-bad1c8dce48so10902133276.0 for ; Wed, 07 Jun 2023 12:46:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686167162; x=1688759162; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=GMvXXWaPKrwI8ANUMqyoY6XpdWuvZ2GGO8wtmAqxRv8=; b=44H05++tu/UWuqm3JuxpRf6vMLsECzczci0UyIUM3OThFWRiahAt92FfhRZhSbBwli 8/1qfxGZ/VTr91tecb7st2f1w7Mt72fLDC0mU1zCkJiAIN7Mw7S6hlj8V2HdVsEihDHA PeILBnvUmqvJ0x1+JXeJCdoAS9EAyiy4jPlmRyYm6dBlIsDjr/9Xbu4BCkGDqs2l1fAY 4wVh3IropgCq0jmNSAvgDdMkA6uKJ/X7wqGEoBknvm2MDi9mY5pYcLlv94VLhn6OjOOc ucZmGH8BIvzeugQBdnkUorBxJjwXODIhc/tDcFubiJ/6d25Kctx8gI/Xns5hEqSi7CLO RadQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686167162; x=1688759162; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=GMvXXWaPKrwI8ANUMqyoY6XpdWuvZ2GGO8wtmAqxRv8=; b=W7CBt5gQBnvyg8GMbxI8eLJJS+cual+oS2qh433g0pj/4Gj5TkGCzdV3dOEB/2y3Mv IMQV5GoyZeLfVAX4ZB9RlCLkR9+5ab4sJVrI/R9hLAD77UTNGDLfM+4vAQZhMLiE2LL+ MFL338SXI4OFiEqLHc4UAWIhM0QzYNIJ5nI4MInZcNLGrh1gqvHkkKSfiUEy4xobcNli 4r7srAyzWy32rQwt+MQoPg+ITQB9HKMb6GDb8peN/i8lz0PoeoieNKr0JuDJ74CXjTUe dvdG9zyEfXAqATKSPKjkR5PB3rxuyYRTduXm0DlZXaUBZScYDTR5TXp13YVPs6/Skxsc VkVA== X-Gm-Message-State: AC+VfDwwrSY4TNUlOmLBiVz1ZzSnioU+A7DlGrvYL6INKbJ6U1+LcSAv w4H9VYX8pGA9jAYM2Uj1n1YnYsen4dFPYJ67t95UByCc2T2LCFew1KQ8VTsGhD7z+dIlqkKaWrW C2WUHnIsB+cPtGpYi7wi/KuWKUTiV2JSvafD5FkLWaWjpigqf57Piz7OTWgVgra8FyfnOZ0Q= X-Google-Smtp-Source: ACHHUZ4KSb7sB8/bYxjIdGGm9lhaO9umaUIt7cTmZ1//R+CmbCUOZ0UJCj1y/ESSBxrH8CNkeqmF30Cs6PkVID1Mpw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a05:6902:100c:b0:ba8:4ff5:3217 with SMTP id w12-20020a056902100c00b00ba84ff53217mr2467566ybt.3.1686167162151; Wed, 07 Jun 2023 12:46:02 -0700 (PDT) Date: Wed, 7 Jun 2023 19:45:52 +0000 In-Reply-To: <20230607194554.87359-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230607194554.87359-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230607194554.87359-3-jingzhangos@google.com> Subject: [PATCH v4 2/4] KVM: arm64: Enable writable for ID_DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org All valid fields in ID_DFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a6299c796d03..3964a85a89fe 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2017,7 +2017,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .set_user = set_id_dfr0_el1, .visibility = aa32_id_visibility, .reset = read_sanitised_id_dfr0_el1, - .val = ID_DFR0_EL1_PerfMon_MASK, }, + .val = GENMASK(63, 0), }, ID_HIDDEN(ID_AFR0_EL1), AA32_ID_SANITISED(ID_MMFR0_EL1), AA32_ID_SANITISED(ID_MMFR1_EL1), From patchwork Wed Jun 7 19:45:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13271191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FC17C77B7A for ; Wed, 7 Jun 2023 19:46:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231458AbjFGTqM (ORCPT ); Wed, 7 Jun 2023 15:46:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231585AbjFGTqF (ORCPT ); Wed, 7 Jun 2023 15:46:05 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9770F1FFA for ; Wed, 7 Jun 2023 12:46:04 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-1b03f9dfd52so30861125ad.3 for ; Wed, 07 Jun 2023 12:46:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686167164; x=1688759164; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=huLg6ss0tcmHNDWws/J4wYZLAswrAiv7bwqrVCr+Www=; b=rvQpvgjutLDBUFD6re8s66cYIwgJnhk30RuWpsooLwa0/DnV1KMpLh1QKXz+AU3+EJ toULyYGPVwLcH+MSf1zAwjIgC+QmNBB84JuvtVGLm32grPQNsyGJC3yXIN+pXqUx0vmf kYkm0cPqzfksnRtP/WQ3XaIV5kyL5FExnTnvHnNEHk9QkXCUYZPtMjAyqZOwoW4K0Hq1 y35uWuI4QoY/hqnEX3uFzWlae+hnEGx6aU+9CDnIEosOHdw7Xdp/4v0Mg9VKQ9GeT0yk 980+Iqqj10VIbOSXVkqMt9C0azx+wOnrkAIodnSMgi7gX9SdshzFmuUiEcp8K2mTBDU0 eicg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686167164; x=1688759164; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=huLg6ss0tcmHNDWws/J4wYZLAswrAiv7bwqrVCr+Www=; b=caUo6xMMkt8TNXXP49uWMU3ja2L01Vr0rRRocOiP21G3ud2eua9dkuPmoMDkg/H0je cUrKOLzJSV8JwzMKmK3v2nu+lP+Rbtc3uTGzHY2wabzFm52vvu3zhIjop/rOTNeBrhEA gIGVu3Sr9h4da0Z8kLmEt8Q79bxKz77rbc+4NI2LWjnNP98KbCrHudYE0B0TPEhFhgYU Gcw2YLXRSw98TS4wdwjCVyB2WUojNV1oZDOUC1FuuzHQZDMw/5/KnULBmRuRk9keNzYN 8X6LZqHN5wo/TxcPr+nTy96FMc3uafJnVr2lVT21L4QToM6Mtj5gh9TwVXf75Ceo7RsI pWHg== X-Gm-Message-State: AC+VfDxUoEd5BOZuY+ewHH+Qrlku9u7vrZf1kal/ZJwytJ8GBP/PyoxK 4fhksqkyXx+a7wYRryxdyRuT5Gv634ScmYqZDSHmM/Xn4iPnkG/xrLYq8q07O1zFBxFPyzSr2yB ++PhCFX5B1Z8LDwG5zT15Y1h2yhVWvrvZ2rX5L5cJHFg5nV68+P8Ser2BwMCeuMHjgEhN00Q= X-Google-Smtp-Source: ACHHUZ4hJXt9tbUdkBWtP+0/4Tl+ZJnlb3E1BRZjLecrD3nbq3Co9zEpbNCwpWdnYYtl6Y/VvwJ4Y5DV8ySaS3odNA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:903:453:b0:1ae:549f:af6e with SMTP id iw19-20020a170903045300b001ae549faf6emr1907179plb.7.1686167163943; Wed, 07 Jun 2023 12:46:03 -0700 (PDT) Date: Wed, 7 Jun 2023 19:45:53 +0000 In-Reply-To: <20230607194554.87359-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230607194554.87359-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230607194554.87359-4-jingzhangos@google.com> Subject: [PATCH v4 3/4] KVM: arm64: Enable writable for ID_AA64PFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Return an error if userspace tries to set SVE field of the register to a value that conflicts with SVE configuration for the guest. SIMD/FP/SVE fields of the requested value are validated according to Arm ARM. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 3964a85a89fe..8f3ad9c12b27 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1509,9 +1509,36 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); + if (!system_supports_sve()) + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); + return val; } +static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd, + u64 val) +{ + int fp, simd; + bool has_sve = id_aa64pfr0_sve(val); + + simd = cpuid_feature_extract_signed_field(val, ID_AA64PFR0_EL1_AdvSIMD_SHIFT); + fp = cpuid_feature_extract_signed_field(val, ID_AA64PFR0_EL1_FP_SHIFT); + /* AdvSIMD field must have the same value as FP field */ + if (simd != fp) + return -EINVAL; + + /* fp must be supported when sve is supported */ + if (has_sve && (fp < 0)) + return -EINVAL; + + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */ + if (vcpu_has_sve(vcpu) ^ has_sve) + return -EPERM; + + return set_id_reg(vcpu, rd, val); +} + static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -2049,9 +2076,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, .get_user = get_id_reg, - .set_user = set_id_reg, + .set_user = set_id_aa64pfr0_el1, .reset = read_sanitised_id_aa64pfr0_el1, - .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), From patchwork Wed Jun 7 19:45:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13271192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD80BC77B7A for ; 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Wed, 07 Jun 2023 12:46:05 -0700 (PDT) Date: Wed, 7 Jun 2023 19:45:54 +0000 In-Reply-To: <20230607194554.87359-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230607194554.87359-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230607194554.87359-5-jingzhangos@google.com> Subject: [PATCH v4 4/4] KVM: arm64: Enable writable for ID_AA64MMFR{0, 1, 2}_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Enable writable from userspace for ID_AA64MMFR{0, 1, 2}_EL1. Added a macro for defining general writable idregs. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8f3ad9c12b27..54c762c95983 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1391,9 +1391,6 @@ static u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 encoding) val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), pmuver_to_perfmon(vcpu_pmuver(vcpu))); break; - case SYS_ID_AA64MMFR2_EL1: - val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; - break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -1663,6 +1660,18 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, return pmuver_update(vcpu, rd, val, perfmon_to_pmuver(perfmon), valid_pmu); } +static u64 read_sanitised_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + u64 val; + u32 id = reg_to_encoding(rd); + + val = read_sanitised_ftr_reg(id); + val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; + + return val; +} + /* * cpufeature ID register user accessors * @@ -1898,6 +1907,16 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, .val = 0, \ } +#define ID_SANITISED_WRITABLE(name) { \ + SYS_DESC(SYS_##name), \ + .access = access_id_reg, \ + .get_user = get_id_reg, \ + .set_user = set_id_reg, \ + .visibility = id_visibility, \ + .reset = general_read_kvm_sanitised_reg,\ + .val = GENMASK(63, 0), \ +} + /* sys_reg_desc initialiser for known cpufeature ID registers */ #define AA32_ID_SANITISED(name) { \ SYS_DESC(SYS_##name), \ @@ -2113,9 +2132,14 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(6,7), /* CRm=7 */ - ID_SANITISED(ID_AA64MMFR0_EL1), - ID_SANITISED(ID_AA64MMFR1_EL1), - ID_SANITISED(ID_AA64MMFR2_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR0_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR1_EL1), + { SYS_DESC(SYS_ID_AA64MMFR2_EL1), + .access = access_id_reg, + .get_user = get_id_reg, + .set_user = set_id_reg, + .reset = read_sanitised_id_aa64mmfr2_el1, + .val = GENMASK(63, 0), }, ID_UNALLOCATED(7,3), ID_UNALLOCATED(7,4), ID_UNALLOCATED(7,5),