From patchwork Fri Jun 9 11:50:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13273751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60C59C87FDE for ; Fri, 9 Jun 2023 11:51:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239078AbjFILve (ORCPT ); Fri, 9 Jun 2023 07:51:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238764AbjFILva (ORCPT ); Fri, 9 Jun 2023 07:51:30 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7580F3AA6; Fri, 9 Jun 2023 04:50:54 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 359Ax9s3025077; Fri, 9 Jun 2023 11:50:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=0EB/2bm6n63XmQQ27jSNwrVyH2tn76g7ixF/gd2TUcY=; b=HViQctsHmCgxX0SFjP2wxlEW4zJsCOrCXGHqDo8AcU+v1dsI87JqhcjKF6OM47IBRz5J I73LrsW3b9QMfOK3KyFoamS5Aar/RhJhc4BBsJM7w6Ixr4cLb2K4qfP8WHX5SuDOCjo1 XHxh6zZPuxqikk3hpv8TQA+ZFxZdgThdszfj0y/wySh1qoc4s7btvpJ9r439VT3Fkb6z /layCONYx36yjcIqi16QK9lCk9fiW7SZ80f3Ubq0AmQRF48D7bK1lVfKn4Jpc8RnzjCO WZMkrX9XMppl3SWoDrBkcG5sZWFrKZzzmEf/rgzX7FksvhhfGwBlPd66WoHc4yEmeLtq kw== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r3xyx8hen-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 09 Jun 2023 11:50:45 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 359Boed4019489; Fri, 9 Jun 2023 11:50:40 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3r2g35rh4x-1; Fri, 09 Jun 2023 11:50:40 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 359BoeOK019477; Fri, 9 Jun 2023 11:50:40 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 359BoeTi019473; Fri, 09 Jun 2023 11:50:40 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 916D05F37; Fri, 9 Jun 2023 17:20:39 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, tglx@linutronix.de, maz@kernel.org, mani@kernel.org, robimarko@gmail.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v4 1/5] dt-bindings: arm: qcom: Document SDX75 platform and boards Date: Fri, 9 Jun 2023 17:20:34 +0530 Message-Id: <1686311438-24177-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1686311438-24177-1-git-send-email-quic_rohiagar@quicinc.com> References: <1686311438-24177-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: G9wD1vYr6Tbje79tERHYDF2bwJhVMfmI X-Proofpoint-GUID: G9wD1vYr6Tbje79tERHYDF2bwJhVMfmI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_08,2023-06-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 mlxlogscore=863 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090100 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the SDX75 platform binding and also the boards using it. Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d9dd256..772f145 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -69,6 +69,7 @@ description: | sdm845 sdx55 sdx65 + sdx75 sm4250 sm6115 sm6115p @@ -821,6 +822,11 @@ properties: - items: - enum: + - qcom,sdx75-idp + - const: qcom,sdx75 + + - items: + - enum: - qcom,ipq6018-cp01 - qcom,ipq6018-cp01-c1 - const: qcom,ipq6018 @@ -1042,6 +1048,7 @@ allOf: - qcom,sdm845 - qcom,sdx55 - qcom,sdx65 + - qcom,sdx75 - qcom,sm4250 - qcom,sm6115 - qcom,sm6125 From patchwork Fri Jun 9 11:50:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13273750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32626C83003 for ; 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Fri, 09 Jun 2023 11:50:44 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 359BofZH019509; Fri, 9 Jun 2023 11:50:41 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3r2g35rh54-1; Fri, 09 Jun 2023 11:50:41 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 359BoeDE019490; Fri, 9 Jun 2023 11:50:40 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 359BoeLA019482; Fri, 09 Jun 2023 11:50:40 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id DF7AF5F39; Fri, 9 Jun 2023 17:20:39 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, tglx@linutronix.de, maz@kernel.org, mani@kernel.org, robimarko@gmail.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v4 2/5] dt-bindings: firmware: scm: Add compatible for SDX75 Date: Fri, 9 Jun 2023 17:20:35 +0530 Message-Id: <1686311438-24177-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1686311438-24177-1-git-send-email-quic_rohiagar@quicinc.com> References: <1686311438-24177-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: OaMsxHozncvRGTnqcUu4I_fVna41KoI- X-Proofpoint-GUID: OaMsxHozncvRGTnqcUu4I_fVna41KoI- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_08,2023-06-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 suspectscore=0 clxscore=1015 mlxlogscore=932 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090099 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree compatible for SCM present in SDX75 platform. Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 367d04a..09073e1 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -51,6 +51,7 @@ properties: - qcom,scm-sdm845 - qcom,scm-sdx55 - qcom,scm-sdx65 + - qcom,scm-sdx75 - qcom,scm-sm6115 - qcom,scm-sm6125 - qcom,scm-sm6350 From patchwork Fri Jun 9 11:50:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13273754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76E0AC7EE29 for ; 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Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index a106ba6..24ec69a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -34,6 +34,7 @@ properties: - qcom,sdm845-pdc - qcom,sdx55-pdc - qcom,sdx65-pdc + - qcom,sdx75-pdc - qcom,sm6350-pdc - qcom,sm8150-pdc - qcom,sm8250-pdc From patchwork Fri Jun 9 11:50:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13273753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33769C87FF1 for ; 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Fri, 09 Jun 2023 11:50:45 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 359BoeuQ019488; Fri, 9 Jun 2023 11:50:42 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3r2g35rh5e-1; Fri, 09 Jun 2023 11:50:41 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 359Bof5T019533; Fri, 9 Jun 2023 11:50:41 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 359Bof8i019519; Fri, 09 Jun 2023 11:50:41 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id C32535F1A; Fri, 9 Jun 2023 17:20:40 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, tglx@linutronix.de, maz@kernel.org, mani@kernel.org, robimarko@gmail.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v4 4/5] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SDX75 compatible Date: Fri, 9 Jun 2023 17:20:37 +0530 Message-Id: <1686311438-24177-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1686311438-24177-1-git-send-email-quic_rohiagar@quicinc.com> References: <1686311438-24177-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VwO9MEGDf6i-2rD4ikGsO0jTzMEVu9gJ X-Proofpoint-ORIG-GUID: VwO9MEGDf6i-2rD4ikGsO0jTzMEVu9gJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_08,2023-06-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=872 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090100 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add compatible for EPSS CPUFREQ-HW on SDX75. Signed-off-by: Rohit Agarwal Acked-by: Viresh Kumar Acked-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index a6b3bb8..866ed2d 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -36,6 +36,7 @@ properties: - qcom,sa8775p-cpufreq-epss - qcom,sc7280-cpufreq-epss - qcom,sc8280xp-cpufreq-epss + - qcom,sdx75-cpufreq-epss - qcom,sm6375-cpufreq-epss - qcom,sm8250-cpufreq-epss - qcom,sm8350-cpufreq-epss From patchwork Fri Jun 9 11:50:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13273755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4302FC88C84 for ; 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Fri, 09 Jun 2023 11:50:46 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 359BogEB019592; Fri, 9 Jun 2023 11:50:42 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3r2g35rh5g-1; Fri, 09 Jun 2023 11:50:42 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 359Bof5V019533; Fri, 9 Jun 2023 11:50:42 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 359Bof8k019519; Fri, 09 Jun 2023 11:50:42 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 87C375F37; Fri, 9 Jun 2023 17:20:41 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, tglx@linutronix.de, maz@kernel.org, mani@kernel.org, robimarko@gmail.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v4 5/5] arm64: dts: qcom: Add SDX75 platform and IDP board support Date: Fri, 9 Jun 2023 17:20:38 +0530 Message-Id: <1686311438-24177-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1686311438-24177-1-git-send-email-quic_rohiagar@quicinc.com> References: <1686311438-24177-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: CTKlxNYqcPpCZnKxmAtRlVVkF7bUyZkI X-Proofpoint-GUID: CTKlxNYqcPpCZnKxmAtRlVVkF7bUyZkI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_08,2023-06-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090100 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add basic devicetree support for SDX75 platform and IDP board from Qualcomm. The SDX75 platform features an ARM Cortex A55 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, UART, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. Signed-off-by: Rohit Agarwal --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdx75-idp.dts | 33 ++ arch/arm64/boot/dts/qcom/sdx75.dtsi | 670 +++++++++++++++++++++++++++++++++ 3 files changed, 704 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d42c595..4fd5a18 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts new file mode 100644 index 0000000..cbe5cdf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sdx75.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX75 IDP"; + compatible = "qcom,sdx75-idp", "qcom,sdx75"; + + aliases { + serial0 = &uart1; + }; +}; + +&chosen { + stdout-path = "serial0:115200n8"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <110 6>; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi new file mode 100644 index 0000000..21d5d55 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX75 SoC device tree source + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + chosen: chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_100>; + + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_200>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_300>; + + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_OFF: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <235>; + exit-latency-us = <428>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + CPU_RAIL_OFF: cpu-rail-sleep-1 { + compatible = "arm,idle-state"; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001344>; + entry-latency-us = <2761>; + exit-latency-us = <3964>; + min-residency-us = <8467>; + }; + + CLUSTER_SLEEP_2: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b344>; + entry-latency-us = <2793>; + exit-latency-us = <4023>; + min-residency-us = <9826>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sdx75", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x800000>; + no-map; + }; + + hyp_elf_package_mem: hyp-elf-package@80800000 { + reg = <0x0 0x80800000 0x0 0x200000>; + no-map; + }; + + access_control_db_mem: access-control-db@81380000 { + reg = <0x0 0x81380000 0x0 0x80000>; + no-map; + }; + + qteetz_mem: qteetz@814e0000 { + reg = <0x0 0x814e0000 0x0 0x2a0000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@81780000 { + reg = <0x0 0x81780000 0x0 0xa00000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump@87a00000 { + reg = <0x0 0x87a00000 0x0 0x1c0000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@87c00000 { + reg = <0x0 0x87c00000 0x0 0x100000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog@87d00000 { + reg = <0x0 0x87d00000 0x0 0x40000>; + no-map; + }; + + xbl_sc_mem: xbl-sc@87d40000 { + reg = <0x0 0x87d40000 0x0 0x40000>; + no-map; + }; + + modem_efs_shared_mem: modem-efs-shared@87d80000 { + reg = <0x0 0x87d80000 0x0 0x10000>; + no-map; + }; + + aop_image_mem: aop-image@87e00000 { + reg = <0x0 0x87e00000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@87e20000 { + reg = <0x0 0x87e20000 0x0 0xc0000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@87ee0000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x87ee0000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config@87f00000 { + reg = <0x0 0x87f00000 0x0 0x20000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@87f20000 { + reg = <0x0 0x87f20000 0x0 0x10000>; + no-map; + }; + + secdata_mem: secdata@87f30000 { + reg = <0x0 0x87f30000 0x0 0x1000>; + no-map; + }; + + tme_crashdump_mem: tme-crashdump@87f31000 { + reg = <0x0 0x87f31000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log@87f71000 { + reg = <0x0 0x87f71000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log@87f75000 { + reg = <0x0 0x87f75000 0x0 0x10000>; + no-map; + }; + + qdss_mem: qdss@88800000 { + reg = <0x0 0x88800000 0x0 0x300000>; + no-map; + }; + + audio_heap_mem: audio-heap@88b00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x88b00000 0x0 0x400000>; + no-map; + }; + + mpss_dsmharq_mem: mpss-dsmharq@88f00000 { + reg = <0x0 0x88f00000 0x0 0x5080000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 { + reg = <0x0 0x8df80000 0x0 0x80000>; + no-map; + }; + + mpssadsp_mem: mpssadsp@8e000000 { + reg = <0x0 0x8e000000 0x0 0xf400000>; + no-map; + }; + + gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 { + reg = <0x0 0xbdb00000 0x0 0x2000000>; + no-map; + }; + + smmu_debug_buf_mem: smmu-debug-buf@bfb00000 { + reg = <0x0 0xbfb00000 0x0 0x100000>; + no-map; + }; + + hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 { + reg = <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x0 0x0080000 0x0 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart1: serial@984000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + pinctrl-0 = <&qupv3_se1_2uart_active>; + pinctrl-1 = <&qupv3_se1_2uart_sleep>; + pinctrl-names = "default", + "sleep"; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdx75-pdc", "qcom,pdc"; + reg = <0x0 0xb220000 0x0 0x30000>, + <0x0 0x174000f0 0x0 0x64>; + qcom,pdc-ranges = <0 147 52>, + <52 266 32>, + <84 500 59>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sdx75-tlmm"; + reg = <0x0 0x0f000000 0x0 0x400000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { + tx-pins { + pins = "gpio12"; + function = "qup_se1_l2_mira"; + drive-strength= <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio13"; + function = "qup_se1_l3_mira"; + drive-strength= <2>; + bias-disable; + }; + }; + + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x0 0x17200000 0x0 0x10000>, + <0x0 0x17260000 0x0 0x80000>; + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + + power-domains = <&CLUSTER_PD>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sdx75-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>; + reg-names = "freq-domain0"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + clock-names = "xo", + "alternate"; + interrupts = ; + interrupt-names = "dcvsh-irq-0"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};