From patchwork Tue Jun 13 13:23:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13278736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D42C9C88CB4 for ; Tue, 13 Jun 2023 13:23:56 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.12898.1686662626826205243 for ; Tue, 13 Jun 2023 06:23:47 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.00,239,1681138800"; d="scan'208";a="166947015" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jun 2023 22:23:45 +0900 Received: from localhost.localdomain (unknown [10.226.92.247]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DC817426DCCE; Tue, 13 Jun 2023 22:23:43 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Fabrizio Castro Subject: [PATCH 5.10.y-cip 1/7] serial: 8250_em: Simplify probe() Date: Tue, 13 Jun 2023 14:23:33 +0100 Message-Id: <20230613132339.150671-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> References: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 13 Jun 2023 13:23:56 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/11981 commit 6b5f1e2e22ffd562075eaf6e018607e7dffe154d upstream. Simplify probe() by using dev_err_probe() instead of dev_err() and add a local variable 'dev' to replace '&pdev->dev'. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230227114152.22265-3-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Biju Das --- drivers/tty/serial/8250/8250_em.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index d94c3811a8f7..17c0aa424df8 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -79,6 +79,7 @@ static void serial8250_em_serial_dl_write(struct uart_8250_port *up, int value) static int serial8250_em_probe(struct platform_device *pdev) { struct serial8250_em_priv *priv; + struct device *dev = &pdev->dev; struct uart_8250_port up; struct resource *regs; int irq, ret; @@ -88,27 +89,23 @@ static int serial8250_em_probe(struct platform_device *pdev) return irq; regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!regs) { - dev_err(&pdev->dev, "missing registers\n"); - return -EINVAL; - } + if (!regs) + return dev_err_probe(dev, -EINVAL, "missing registers\n"); - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - priv->sclk = devm_clk_get(&pdev->dev, "sclk"); - if (IS_ERR(priv->sclk)) { - dev_err(&pdev->dev, "unable to get clock\n"); - return PTR_ERR(priv->sclk); - } + priv->sclk = devm_clk_get(dev, "sclk"); + if (IS_ERR(priv->sclk)) + return dev_err_probe(dev, PTR_ERR(priv->sclk), "unable to get clock\n"); memset(&up, 0, sizeof(up)); up.port.mapbase = regs->start; up.port.irq = irq; up.port.type = PORT_16750; up.port.flags = UPF_FIXED_PORT | UPF_IOREMAP | UPF_FIXED_TYPE; - up.port.dev = &pdev->dev; + up.port.dev = dev; up.port.private_data = priv; clk_prepare_enable(priv->sclk); @@ -122,9 +119,8 @@ static int serial8250_em_probe(struct platform_device *pdev) ret = serial8250_register_8250_port(&up); if (ret < 0) { - dev_err(&pdev->dev, "unable to register 8250 port\n"); clk_disable_unprepare(priv->sclk); - return ret; + return dev_err_probe(dev, ret, "unable to register 8250 port\n"); } priv->line = ret; From patchwork Tue Jun 13 13:23:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13278738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E2AC88CB7 for ; Tue, 13 Jun 2023 13:23:56 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.12898.1686662626826205243 for ; Tue, 13 Jun 2023 06:23:48 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.00,239,1681138800"; d="scan'208";a="166947020" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jun 2023 22:23:48 +0900 Received: from localhost.localdomain (unknown [10.226.92.247]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 80E6E426DCD0; Tue, 13 Jun 2023 22:23:46 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Fabrizio Castro Subject: [PATCH 5.10.y-cip 2/7] serial: 8250_em: Drop unused header file Date: Tue, 13 Jun 2023 14:23:34 +0100 Message-Id: <20230613132339.150671-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> References: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 13 Jun 2023 13:23:56 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/11982 commit e335354d2348ce2ea0d3e978b2f49c64354ca189 upstream. Drop unused header file slab.h from the driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230227114152.22265-4-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Biju Das --- drivers/tty/serial/8250/8250_em.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index 17c0aa424df8..045a2110b5c5 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -13,7 +13,6 @@ #include #include #include -#include #include "8250.h" From patchwork Tue Jun 13 13:23:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13278740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0A83C7EE29 for ; Tue, 13 Jun 2023 13:23:56 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.12898.1686662626826205243 for ; Tue, 13 Jun 2023 06:23:51 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.00,239,1681138800"; d="scan'208";a="166947027" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jun 2023 22:23:50 +0900 Received: from localhost.localdomain (unknown [10.226.92.247]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0375A426DCD0; Tue, 13 Jun 2023 22:23:48 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Fabrizio Castro Subject: [PATCH 5.10.y-cip 3/7] serial: 8250_em: Add missing break statement Date: Tue, 13 Jun 2023 14:23:35 +0100 Message-Id: <20230613132339.150671-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> References: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 13 Jun 2023 13:23:56 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/11983 commit 54769d865683e96eeca32e325f586978c11fbbb7 upstream. Add missing break statement in serial8250_em_serial_out(). Suggested-by: Andy Shevchenko Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230227114152.22265-5-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Biju Das --- drivers/tty/serial/8250/8250_em.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index 045a2110b5c5..621abca93694 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -42,6 +42,7 @@ static void serial8250_em_serial_out(struct uart_port *p, int offset, int value) case UART_DLL_EM: /* DLL @ 0x24 (+9) */ case UART_DLM_EM: /* DLM @ 0x28 (+9) */ writel(value, p->membase + (offset << 2)); + break; } } From patchwork Tue Jun 13 13:23:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13278739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D18C9C77B7A for ; Tue, 13 Jun 2023 13:23:56 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.12904.1686662634065855313 for ; Tue, 13 Jun 2023 06:23:54 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.00,239,1681138800"; d="scan'208";a="163405946" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Jun 2023 22:23:53 +0900 Received: from localhost.localdomain (unknown [10.226.92.247]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 793AA426DCD0; Tue, 13 Jun 2023 22:23:51 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Fabrizio Castro Subject: [PATCH 5.10.y-cip 4/7] serial: 8250_em: Use devm_clk_get_enabled() Date: Tue, 13 Jun 2023 14:23:36 +0100 Message-Id: <20230613132339.150671-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> References: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 13 Jun 2023 13:23:56 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/11984 commit 7eada8a122a2683ec63ad43982a4552b054d59ca upstream. Simplify clk handling in probe() by replacing devm_clk_get()->devm_ clk_get_enabled(). This replaces the usage of clk_prepare_enable/clk_ disable_unprepare() in probe()/remove(). After that sclk is no longer required in struct serial8250_em_priv and is replaced by a local variable sclk in probe(). Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230227114152.22265-6-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Biju Das --- drivers/tty/serial/8250/8250_em.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index 621abca93694..dcf1761e8ef5 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -20,7 +20,6 @@ #define UART_DLM_EM 10 struct serial8250_em_priv { - struct clk *sclk; int line; }; @@ -82,6 +81,7 @@ static int serial8250_em_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct uart_8250_port up; struct resource *regs; + struct clk *sclk; int irq, ret; irq = platform_get_irq(pdev, 0); @@ -96,9 +96,9 @@ static int serial8250_em_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - priv->sclk = devm_clk_get(dev, "sclk"); - if (IS_ERR(priv->sclk)) - return dev_err_probe(dev, PTR_ERR(priv->sclk), "unable to get clock\n"); + sclk = devm_clk_get_enabled(dev, "sclk"); + if (IS_ERR(sclk)) + return dev_err_probe(dev, PTR_ERR(sclk), "unable to get clock\n"); memset(&up, 0, sizeof(up)); up.port.mapbase = regs->start; @@ -108,8 +108,7 @@ static int serial8250_em_probe(struct platform_device *pdev) up.port.dev = dev; up.port.private_data = priv; - clk_prepare_enable(priv->sclk); - up.port.uartclk = clk_get_rate(priv->sclk); + up.port.uartclk = clk_get_rate(sclk); up.port.iotype = UPIO_MEM32; up.port.serial_in = serial8250_em_serial_in; @@ -118,10 +117,8 @@ static int serial8250_em_probe(struct platform_device *pdev) up.dl_write = serial8250_em_serial_dl_write; ret = serial8250_register_8250_port(&up); - if (ret < 0) { - clk_disable_unprepare(priv->sclk); + if (ret < 0) return dev_err_probe(dev, ret, "unable to register 8250 port\n"); - } priv->line = ret; platform_set_drvdata(pdev, priv); @@ -133,7 +130,6 @@ static int serial8250_em_remove(struct platform_device *pdev) struct serial8250_em_priv *priv = platform_get_drvdata(pdev); serial8250_unregister_port(priv->line); - clk_disable_unprepare(priv->sclk); return 0; } From patchwork Tue Jun 13 13:23:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13278737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D29BFC83003 for ; Tue, 13 Jun 2023 13:23:56 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.12898.1686662626826205243 for ; Tue, 13 Jun 2023 06:23:56 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.00,239,1681138800"; d="scan'208";a="166947033" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jun 2023 22:23:56 +0900 Received: from localhost.localdomain (unknown [10.226.92.247]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 17533426DCCE; Tue, 13 Jun 2023 22:23:53 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Fabrizio Castro Subject: [PATCH 5.10.y-cip 5/7] serial: 8250_em: Use pseudo offset for UART_FCR Date: Tue, 13 Jun 2023 14:23:37 +0100 Message-Id: <20230613132339.150671-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> References: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 13 Jun 2023 13:23:56 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/11985 commit 59d6558fb5fd750777edfde028ea1f9e7eed8a46 upstream. UART_FCR shares the same offset with UART_IIR. We cannot use UART_FCR in serial8250_em_serial_in() as it overlaps with UART_IIR. Define UART_FCR_EM macro with a high value to avoid overlapping with existing UART_* register defines and define another macro UART_FCR_EM_HW for the real offset. Use these macros in serial8250_em_serial{_in/_out} function to read/write FCR register. Suggested-by: Ilpo Järvinen Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230227114152.22265-7-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Biju Das --- drivers/tty/serial/8250/8250_em.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index dcf1761e8ef5..7614ced9377e 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -19,6 +19,13 @@ #define UART_DLL_EM 9 #define UART_DLM_EM 10 +/* + * A high value for UART_FCR_EM avoids overlapping with existing UART_* + * register defines. UART_FCR_EM_HW is the real HW register offset. + */ +#define UART_FCR_EM 0x10003 +#define UART_FCR_EM_HW 3 + struct serial8250_em_priv { int line; }; @@ -29,12 +36,15 @@ static void serial8250_em_serial_out(struct uart_port *p, int offset, int value) case UART_TX: /* TX @ 0x00 */ writeb(value, p->membase); break; - case UART_FCR: /* FCR @ 0x0c (+1) */ case UART_LCR: /* LCR @ 0x10 (+1) */ case UART_MCR: /* MCR @ 0x14 (+1) */ case UART_SCR: /* SCR @ 0x20 (+1) */ writel(value, p->membase + ((offset + 1) << 2)); break; + case UART_FCR: + case UART_FCR_EM: + writel(value, p->membase + (UART_FCR_EM_HW << 2)); + break; case UART_IER: /* IER @ 0x04 */ value &= 0x0f; /* only 4 valid bits - not Xscale */ fallthrough; @@ -55,6 +65,8 @@ static unsigned int serial8250_em_serial_in(struct uart_port *p, int offset) case UART_MSR: /* MSR @ 0x1c (+1) */ case UART_SCR: /* SCR @ 0x20 (+1) */ return readl(p->membase + ((offset + 1) << 2)); + case UART_FCR_EM: + return readl(p->membase + (UART_FCR_EM_HW << 2)); case UART_IER: /* IER @ 0x04 */ case UART_IIR: /* IIR @ 0x08 */ case UART_DLL_EM: /* DLL @ 0x24 (+9) */ From patchwork Tue Jun 13 13:23:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13278742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D213DC77B7A for ; Tue, 13 Jun 2023 13:24:06 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.12898.1686662626826205243 for ; Tue, 13 Jun 2023 06:23:59 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.00,239,1681138800"; d="scan'208";a="166947040" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jun 2023 22:23:58 +0900 Received: from localhost.localdomain (unknown [10.226.92.247]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8C9C6426DCD0; Tue, 13 Jun 2023 22:23:56 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Fabrizio Castro Subject: [PATCH 5.10.y-cip 6/7] serial: 8250_em: Add serial8250_em_{reg_update(),out_helper()} Date: Tue, 13 Jun 2023 14:23:38 +0100 Message-Id: <20230613132339.150671-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> References: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 13 Jun 2023 13:24:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/11986 commit b22ea7df56b2ee1f9a0212210b51f83a3c2c75c6 upstream. As per RZ/V2M hardware manual(Rev.1.30 Jun, 2022), UART IP has a restriction as mentioned below. 40.6.1 Point for Caution when Changing the Register Settings: When changing the settings of the following registers, a PRESETn master reset or FIFO reset + SW reset (FCR[2],FCR[1], HCR0[7]) must be input to re-initialize them. Target Registers: FCR, LCR, MCR, DLL, DLM, HCR0. Add serial8250_em_reg_update() and serial8250_em_serial_out_helper() to handle this restriction. serial8250_em_serial_out_helper() is identical to previous serial8250_em_serial_out() except that UART_FCR macro is removed from serial8250_em_serial_out_helper() as it is now handled by serial8250_ em_serial_out(). DLL/DLM register can be updated only by setting LCR[7]. So the updation of LCR[7] will perform reset for DLL/DLM register changes. EMMA mobile has the same register set as RZ/V2M and this patch is tested on EMEV2 board. So, there is no harm in applying the same restriction here as well as the HW manual for EMMA mobile is not updated for a long time. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230227114152.22265-8-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Biju Das --- drivers/tty/serial/8250/8250_em.c | 67 ++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index 7614ced9377e..25a9ecf26be6 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -18,6 +18,7 @@ #define UART_DLL_EM 9 #define UART_DLM_EM 10 +#define UART_HCR0_EM 11 /* * A high value for UART_FCR_EM avoids overlapping with existing UART_* @@ -26,11 +27,14 @@ #define UART_FCR_EM 0x10003 #define UART_FCR_EM_HW 3 +#define UART_HCR0_EM_SW_RESET BIT(7) /* SW Reset */ + struct serial8250_em_priv { int line; }; -static void serial8250_em_serial_out(struct uart_port *p, int offset, int value) +static void serial8250_em_serial_out_helper(struct uart_port *p, int offset, + int value) { switch (offset) { case UART_TX: /* TX @ 0x00 */ @@ -41,7 +45,6 @@ static void serial8250_em_serial_out(struct uart_port *p, int offset, int value) case UART_SCR: /* SCR @ 0x20 (+1) */ writel(value, p->membase + ((offset + 1) << 2)); break; - case UART_FCR: case UART_FCR_EM: writel(value, p->membase + (UART_FCR_EM_HW << 2)); break; @@ -50,6 +53,7 @@ static void serial8250_em_serial_out(struct uart_port *p, int offset, int value) fallthrough; case UART_DLL_EM: /* DLL @ 0x24 (+9) */ case UART_DLM_EM: /* DLM @ 0x28 (+9) */ + case UART_HCR0_EM: /* HCR0 @ 0x2c */ writel(value, p->membase + (offset << 2)); break; } @@ -60,6 +64,7 @@ static unsigned int serial8250_em_serial_in(struct uart_port *p, int offset) switch (offset) { case UART_RX: /* RX @ 0x00 */ return readb(p->membase); + case UART_LCR: /* LCR @ 0x10 (+1) */ case UART_MCR: /* MCR @ 0x14 (+1) */ case UART_LSR: /* LSR @ 0x18 (+1) */ case UART_MSR: /* MSR @ 0x1c (+1) */ @@ -71,11 +76,69 @@ static unsigned int serial8250_em_serial_in(struct uart_port *p, int offset) case UART_IIR: /* IIR @ 0x08 */ case UART_DLL_EM: /* DLL @ 0x24 (+9) */ case UART_DLM_EM: /* DLM @ 0x28 (+9) */ + case UART_HCR0_EM: /* HCR0 @ 0x2c */ return readl(p->membase + (offset << 2)); } return 0; } +static void serial8250_em_reg_update(struct uart_port *p, int off, int value) +{ + unsigned int ier, fcr, lcr, mcr, hcr0; + + ier = serial8250_em_serial_in(p, UART_IER); + fcr = serial8250_em_serial_in(p, UART_FCR_EM); + lcr = serial8250_em_serial_in(p, UART_LCR); + mcr = serial8250_em_serial_in(p, UART_MCR); + hcr0 = serial8250_em_serial_in(p, UART_HCR0_EM); + + serial8250_em_serial_out_helper(p, UART_FCR_EM, fcr | + UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT); + serial8250_em_serial_out_helper(p, UART_HCR0_EM, hcr0 | + UART_HCR0_EM_SW_RESET); + serial8250_em_serial_out_helper(p, UART_HCR0_EM, hcr0 & + ~UART_HCR0_EM_SW_RESET); + + switch (off) { + case UART_FCR_EM: + fcr = value; + break; + case UART_LCR: + lcr = value; + break; + case UART_MCR: + mcr = value; + break; + } + + serial8250_em_serial_out_helper(p, UART_IER, ier); + serial8250_em_serial_out_helper(p, UART_FCR_EM, fcr); + serial8250_em_serial_out_helper(p, UART_MCR, mcr); + serial8250_em_serial_out_helper(p, UART_LCR, lcr); + serial8250_em_serial_out_helper(p, UART_HCR0_EM, hcr0); +} + +static void serial8250_em_serial_out(struct uart_port *p, int offset, int value) +{ + switch (offset) { + case UART_TX: + case UART_SCR: + case UART_IER: + case UART_DLL_EM: + case UART_DLM_EM: + serial8250_em_serial_out_helper(p, offset, value); + break; + case UART_FCR: + serial8250_em_reg_update(p, UART_FCR_EM, value); + break; + case UART_LCR: + case UART_MCR: + serial8250_em_reg_update(p, offset, value); + break; + } +} + static int serial8250_em_serial_dl_read(struct uart_8250_port *up) { return serial_in(up, UART_DLL_EM) | serial_in(up, UART_DLM_EM) << 8; From patchwork Tue Jun 13 13:23:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13278741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC4D0C7EE29 for ; Tue, 13 Jun 2023 13:24:06 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.13027.1686662641799362894 for ; Tue, 13 Jun 2023 06:24:02 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.00,239,1681138800"; d="scan'208";a="163405959" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Jun 2023 22:24:01 +0900 Received: from localhost.localdomain (unknown [10.226.92.247]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1E6C2426DCD0; Tue, 13 Jun 2023 22:23:58 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Fabrizio Castro Subject: [PATCH 5.10.y-cip 7/7] arm64: dts: renesas: rzv2mevk2: Add uart0 pins Date: Tue, 13 Jun 2023 14:23:39 +0100 Message-Id: <20230613132339.150671-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> References: <20230613132339.150671-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 13 Jun 2023 13:24:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/11987 commit 6ec5791375954411640871fec6a7df2cb5365a86 upstream. Add uart0 pins in pinctrl node and update the uart0 node to include pinctrl and uart-has-rtscts properties. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230209131422.192941-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index 78f5af4646ce..0f170fd4227b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -127,9 +127,20 @@ i2c2_pins: i2c2 { pinmux = , /* SDA */ ; /* SCL */ }; + + uart0_pins: uart0 { + pinmux = , /* UATX0 */ + , /* UARX0 */ + , /* UACTS0N */ + ; /* UARTS0N */ + }; }; &uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; status = "okay"; };