From patchwork Thu Jun 15 12:17:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 13281218 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0550EB64D9 for ; Thu, 15 Jun 2023 12:18:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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bh=otBODeYk5ye/nH0jryDazGW/q5zUXnsvKnO/9SlKRgg=; b=bYlNzcAlp9dyjyXWCqKXkRk/FK+WUNRzhwkQuQ+n6aKr78l4dYuDeO5dnJAf8ThJ RLFfDSMslfZIVbDmIMzZBFqM4uQQYmShGi3K8/YdxvHuJhj5cToaQ8gNQ+QvKbKe 0aQbo7CgjJJbHm9dpj0wlJtImJZtQzi9PyYrZl93uSI=; X-AuditID: ac14000a-923ff70000007ecb-3e-648b01690190 Received: from berlix.phytec.de (Unknown_Domain [172.25.0.12]) (using TLS with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 67.FF.32459.9610B846; Thu, 15 Jun 2023 14:17:45 +0200 (CEST) Received: from augenblix2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 15 Jun 2023 14:17:44 +0200 From: Teresa Remmet To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team CC: , Subject: [PATCH 1/7] arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt Date: Thu, 15 Jun 2023 14:17:29 +0200 Message-ID: <20230615121735.614024-2-t.remmet@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615121735.614024-1-t.remmet@phytec.de> References: <20230615121735.614024-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWyRpKBRzeTsTvF4P0GLos1e88xWTy86m+x aupOFou+Fw+ZLTY9vsZq0fVrJbNF694j7BZ/t29isXixRdyi+526A5fHzll32T02repk87hz bQ+bx+Yl9R793S2sHhvf7WDy6P9rEMAexWWTkpqTWZZapG+XwJWxv/M9a8E77ooN244xNzA2 cnUxcnBICJhInDgo38XIxSEksIRJ4sOlqywQzhNGic8H37J3MXJysAloSDxdcZoJJCEicIpJ YvWJGcwgCWYBN4l/G+eDFQkL+Ep8WnyfEcRmEVCVWPpqDwuIzStgIfF98TdWEFtCQF5i5qXv YPWcApYSm1qPgc0RAqrp/LiUCaJeUOLkzCcsEPPlJZq3zobaJSFx8MULqHp5iV2XTjLCzJx2 7jUzhB0qsfXLdqYJjEKzkIyahWTULCSjFjAyr2IUys1Mzk4tyszWK8ioLElN1ktJ3cQIih0R Bq4djH1zPA4xMnEwHmKU4GBWEuFddqIrRYg3JbGyKrUoP76oNCe1+BCjNAeLkjjv/R6mRCGB 9MSS1OzU1ILUIpgsEwenVANjzu8XG5+rVZ6Rvxa6wU+/SrDLLOXdtwdcPzr8Ez8+3/JSxaD1 cHKM5oo9L88bHLFYs71KO3wBz7mPJwL6vD8pzN3NI5txVNc1tHtB36Mjcya1ZU3Sn7nxV3XC qht1j/RS3nbv08nyEHI/nP9392ZL0Q/GG2o6Vn01Ko6KNH2isaMuPeve/iuSSizFGYmGWsxF xYkAEFWsYYsCAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230615_051753_496935_EC4CD19B X-CRM114-Status: GOOD ( 10.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Christian Hemp In some occasions the ethernet phy IRQ can not be detected correctly by the SoC. This leads to a non detected link in Linux. The problem is caused by the buffer that adjusts the voltage between ethernet phy and SoC. To workaround this, remove the IRQ support for the ethernet phy and use polling instead. Signed-off-by: Christian Hemp Signed-off-by: Teresa Remmet --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index ecc4bce6db97..e73f1711ec89 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -54,8 +54,6 @@ mdio { ethphy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; @@ -222,7 +220,6 @@ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 >; }; From patchwork Thu Jun 15 12:17:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 13281224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FC99EB64D9 for ; Thu, 15 Jun 2023 12:18:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g769ZfyO8+3wuCqSa5EaGwYjwfzcPxjeUNepOwz8Kgg=; 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Signed-off-by: Teresa Remmet --- .../dts/freescale/imx8mp-phycore-som.dtsi | 132 +++++++++--------- 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index e73f1711ec89..7970fa6f2a28 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -40,11 +40,11 @@ &A53_3 { /* ethernet 1 */ &fec { + fsl,magic-packet; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; status = "okay"; mdio { @@ -53,13 +53,13 @@ mdio { ethphy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; + enet-phy-lane-no-swap; reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; ti,clk-output-sel = ; + ti,fifo-depth = ; ti,min-output-impedance; - enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; }; }; }; @@ -73,8 +73,8 @@ som_flash: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; }; }; @@ -83,97 +83,97 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic: pmic@25 { - reg = <0x25>; compatible = "nxp,pca9450c"; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + reg = <0x25>; regulators { buck1: BUCK1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; regulator-ramp-delay = <3125>; }; buck2: BUCK2 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; nxp,dvs-run-voltage = <950000>; nxp,dvs-standby-voltage = <850000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-ramp-delay = <3125>; }; buck4: BUCK4 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; }; buck5: BUCK5 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; }; buck6: BUCK6 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; }; ldo1: LDO1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; }; ldo2: LDO2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; }; ldo3: LDO3 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; }; ldo4: LDO4 { - regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; }; ldo5: LDO5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; }; }; eeprom@51 { compatible = "atmel,24c32"; - reg = <0x51>; pagesize = <32>; + reg = <0x51>; }; rv3028: rtc@52 { @@ -187,19 +187,19 @@ rv3028: rtc@52 { &usdhc3 { assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; status = "okay"; }; &wdog1 { + fsl,ext-reset-output; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; status = "okay"; }; @@ -213,13 +213,13 @@ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 >; }; @@ -236,8 +236,8 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 >; }; @@ -256,49 +256,49 @@ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 >; }; From patchwork Thu Jun 15 12:17:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 13281221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C548EB64DD for ; Thu, 15 Jun 2023 12:18:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Do not set reserved bits 0 and 3 in pad configuration. Signed-off-by: Teresa Remmet --- .../dts/freescale/imx8mp-phycore-som.dtsi | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 7970fa6f2a28..8e06cb6f522b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -206,20 +206,20 @@ &wdog1 { &iomuxc { pinctrl_fec: fecgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 >; }; @@ -236,21 +236,21 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 >; }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 >; }; pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 >; }; From patchwork Thu Jun 15 12:17:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 13281220 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BE30EB64D9 for ; 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Thu, 15 Jun 2023 14:17:45 +0200 (CEST) Received: from augenblix2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 15 Jun 2023 14:17:45 +0200 From: Teresa Remmet To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team CC: , Subject: [PATCH 4/7] arm64: dts: imx8mp-phycore-som: Remove LDO2 and LDO4 pmic nodes Date: Thu, 15 Jun 2023 14:17:32 +0200 Message-ID: <20230615121735.614024-5-t.remmet@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615121735.614024-1-t.remmet@phytec.de> References: <20230615121735.614024-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsWyRpKBRzeTsTvF4NkTVYs1e88xWTy86m+x aupOFou+Fw+ZLTY9vsZq0fVrJbNF694j7BZ/t29isXixRdyi+526A5fHzll32T02repk87hz bQ+bx+Yl9R793S2sHhvf7WDy6P9rEMAexWWTkpqTWZZapG+XwJXRP30ta8FUzoru+T+YGhhX sncxcnJICJhIPJizmq2LkYtDSGAJk8Tb6e+YQRJCAk8YJbZfqgCx2QQ0JJ6uOM0EUiQicIpJ YvWJGWBFzAJuEv82zgeaxMEhLBAiseV/NojJIqAq0T3JCqSCV8BCouvvZ2aIXfISMy99B9vL KWApsan1GNQqC4nOj0uZIOoFJU7OfMICMV1eonnrbKhNEhIHX7yAqpeX2HXpJCPMzGnnXkPN D5XY+mU70wRGoVlIRs1CMmoWklELGJlXMQrlZiZnpxZlZusVZFSWpCbrpaRuYgTFjQgD1w7G vjkehxiZOBgPMUpwMCuJ8C470ZUixJuSWFmVWpQfX1Sak1p8iFGag0VJnPd+D1OikEB6Yklq dmpqQWoRTJaJg1OqgXGb4e+LpyoNpO73bEleXP6mgYX1k2XgWfPgiqVFySsOxqjGHxG7sUpX lC1wlVtDaJZ8U9pas/V9VY/ERV3Sz0UENjof/LV7/b/5kjsU7z0oNH6guu5ze90cTw5FrrQV dlyGM2YueCCadKLp+bOQY1wMm8ud11dzc+iH/uDg0wx9c2L3+60aNkosxRmJhlrMRcWJADln HimJAgAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230615_051757_548098_8A431ABE X-CRM114-Status: GOOD ( 10.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We do not touch LDO2 and LDO4 in linux as they are bypassed. So remove them completely from device tree. Signed-off-by: Teresa Remmet --- .../arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 8e06cb6f522b..ef86f2071d5b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -142,13 +142,6 @@ ldo1: LDO1 { regulator-min-microvolt = <1600000>; }; - ldo2: LDO2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1150000>; - regulator-min-microvolt = <800000>; - }; - ldo3: LDO3 { regulator-always-on; regulator-boot-on; @@ -156,11 +149,6 @@ ldo3: LDO3 { regulator-min-microvolt = <800000>; }; - ldo4: LDO4 { - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <800000>; - }; - ldo5: LDO5 { regulator-always-on; regulator-boot-on; From patchwork Thu Jun 15 12:17:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 13281223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB08FEB64DB for ; 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Signed-off-by: Teresa Remmet --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index ef86f2071d5b..ad7a3e0b9089 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -101,6 +101,7 @@ buck1: BUCK1 { regulator-boot-on; regulator-max-microvolt = <2187500>; regulator-min-microvolt = <600000>; + regulator-name = "VDD_SOC (BUCK1)"; regulator-ramp-delay = <3125>; }; @@ -111,6 +112,7 @@ buck2: BUCK2 { regulator-boot-on; regulator-max-microvolt = <2187500>; regulator-min-microvolt = <600000>; + regulator-name = "VDD_ARM (BUCK2)"; regulator-ramp-delay = <3125>; }; @@ -119,6 +121,7 @@ buck4: BUCK4 { regulator-boot-on; regulator-max-microvolt = <3400000>; regulator-min-microvolt = <600000>; + regulator-name = "VDD_3V3 (BUCK4)"; }; buck5: BUCK5 { @@ -126,6 +129,7 @@ buck5: BUCK5 { regulator-boot-on; regulator-max-microvolt = <3400000>; regulator-min-microvolt = <600000>; + regulator-name = "VDD_1V8 (BUCK5)"; }; buck6: BUCK6 { @@ -133,6 +137,7 @@ buck6: BUCK6 { regulator-boot-on; regulator-max-microvolt = <3400000>; regulator-min-microvolt = <600000>; + regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; }; ldo1: LDO1 { @@ -140,6 +145,7 @@ ldo1: LDO1 { regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <1600000>; + regulator-name = "NVCC_SNVS_1V8 (LDO1)"; }; ldo3: LDO3 { @@ -147,6 +153,7 @@ ldo3: LDO3 { regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <800000>; + regulator-name = "VDDA_1V8 (LDO3)"; }; ldo5: LDO5 { @@ -154,6 +161,7 @@ ldo5: LDO5 { regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO5)"; }; }; }; From patchwork Thu Jun 15 12:17:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 13281219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F9D6EB64DB for ; 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Thu, 15 Jun 2023 14:17:45 +0200 (CEST) Received: from augenblix2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 15 Jun 2023 14:17:45 +0200 From: Teresa Remmet To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team CC: , Subject: [PATCH 6/7] arm64: dts: imx8mp-phycore-som: Update regulator output voltages Date: Thu, 15 Jun 2023 14:17:34 +0200 Message-ID: <20230615121735.614024-7-t.remmet@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615121735.614024-1-t.remmet@phytec.de> References: <20230615121735.614024-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWyRpKBRzeTsTvF4OQ7K4s1e88xWTy86m+x aupOFou+Fw+ZLTY9vsZq0fVrJbNF694j7BZ/t29isXixRdyi+526A5fHzll32T02repk87hz bQ+bx+Yl9R793S2sHhvf7WDy6P9rEMAexWWTkpqTWZZapG+XwJUxqeENS8FWsYrpf38zNzCe FOxi5OSQEDCRuPakibWLkYtDSGAJk8TK5tNsIAkhgSeMEtsvVYDYbAIaEk9XnGYCKRIROMUk sfrEDGaQBLOAm8S/jfPZQWxhgVCJ73deMoLYLAKqEr2XX4EN4hWwkDi6YA8rxDZ5iZmXvoPV cwpYSmxqPcYMscxCovPjUiaIekGJkzOfsEDMl5do3jobapeExMEXL6Dq5SV2XTrJCDNz2rnX zBB2qMTWL9uZJjAKzUIyahaSUbOQjFrAyLyKUSg3Mzk7tSgzW68go7IkNVkvJXUTIyh2RBi4 djD2zfE4xMjEwXiIUYKDWUmEd9mJrhQh3pTEyqrUovz4otKc1OJDjNIcLErivPd7mBKFBNIT S1KzU1MLUotgskwcnFINjCGKB2O1UrJadsd6dF0X27/gnt5+gwq7i69M0xdHe9/2Z5+54FdN lHDpFA+9HLej33fe/vLRMJJt+aMbF47FFa1833qkM7NK0ur8kyNX84LXd/+bKdp0ys/uTMRL taUpTXOMGN6uEzf6ybPLSPbIZOfwwtNG15gtQ9lmvv57rmby7id7ii+9llJiKc5INNRiLipO BAA1P60QiwIAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230615_051759_305904_2BC8EE23 X-CRM114-Status: GOOD ( 10.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Set the regulator voltages to the min and max values the i.MX8MP requires and not what the PMIC provides. Signed-off-by: Teresa Remmet --- .../dts/freescale/imx8mp-phycore-som.dtsi | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index ad7a3e0b9089..d3e7d3087ec1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -99,8 +99,8 @@ regulators { buck1: BUCK1 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <2187500>; - regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <805000>; regulator-name = "VDD_SOC (BUCK1)"; regulator-ramp-delay = <3125>; }; @@ -110,8 +110,8 @@ buck2: BUCK2 { nxp,dvs-standby-voltage = <850000>; regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <2187500>; - regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <805000>; regulator-name = "VDD_ARM (BUCK2)"; regulator-ramp-delay = <3125>; }; @@ -119,40 +119,40 @@ buck2: BUCK2 { buck4: BUCK4 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; regulator-name = "VDD_3V3 (BUCK4)"; }; buck5: BUCK5 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; regulator-name = "VDD_1V8 (BUCK5)"; }; buck6: BUCK6 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; }; ldo1: LDO1 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1710000>; regulator-name = "NVCC_SNVS_1V8 (LDO1)"; }; ldo3: LDO3 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; regulator-name = "VDDA_1V8 (LDO3)"; }; From patchwork Thu Jun 15 12:17:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teresa Remmet X-Patchwork-Id: 13281222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D902EB64DC for ; Thu, 15 Jun 2023 12:18:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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Thu, 15 Jun 2023 14:17:46 +0200 (CEST) Received: from augenblix2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 15 Jun 2023 14:17:45 +0200 From: Teresa Remmet To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team CC: , Subject: [PATCH 7/7] arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks assignment Date: Thu, 15 Jun 2023 14:17:35 +0200 Message-ID: <20230615121735.614024-8-t.remmet@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230615121735.614024-1-t.remmet@phytec.de> References: <20230615121735.614024-1-t.remmet@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsWyRpKBRzeLsTvFYPUENos1e88xWTy86m+x aupOFou+Fw+ZLTY9vsZq0fVrJbNF694j7BZ/t29isXixRdyi+526A5fHzll32T02repk87hz bQ+bx+Yl9R793S2sHhvf7WDy6P9rEMAexWWTkpqTWZZapG+XwJUxfcpU9oLZHBVT3zUxNjDO YO9i5OSQEDCRaNrRw9rFyMUhJLCESaLldDcrSEJI4AmjxPZLFSA2m4CGxNMVp5lAikQETjFJ rD4xgxkkwSzgJvFv43ywScICMRKH3/aA2SwCqhLr3z9k6WLk4OAVsJB48zYHYpm8xMxL38FK OAUsJTa1HmOG2GUh0flxKROIzSsgKHFy5hMWiPHyEs1bZ0OtkpA4+OIFVL28xK5LJxlhZk47 95oZwg6V2PplO9MERqFZSEbNQjJqFpJRCxiZVzEK5WYmZ6cWZWbrFWRUlqQm66WkbmIERY4I A9cOxr45HocYmTgYDzFKcDArifAuO9GVIsSbklhZlVqUH19UmpNafIhRmoNFSZz3fg9TopBA emJJanZqakFqEUyWiYNTqoHR7JrNrd49uw+kNh4uY/zR99fQVjdWd2+57dnTfbu2rFmzRHX+ NY+zL/LKz8//Jv3hs8YfmQ/xKroPZXwzdolc/hjEG+Ri0NA1Ncxo/WJNixUSK7eXyJ42SDxc fKU9aD2nRV6uAhfnycRXMeJfBPeadmsKXrH0KlsQX77Jvc2y9+GiWcvqGRYrsRRnJBpqMRcV JwIAU9BdQYoCAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230615_051800_570509_11CBA809 X-CRM114-Status: GOOD ( 11.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jonas Kuenstler Add the missing usdhc2 root clock to 200MHz to be able to support SDR104 mode for SD-Card on phyBOARD-Pollux-i.MX8MP. Signed-off-by: Jonas Kuenstler Signed-off-by: Teresa Remmet --- arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 6aa720bafe28..0a51ddbc62df 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -103,6 +103,8 @@ &uart1 { /* SD-Card */ &usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <200000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;