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Sun, 18 Jun 2023 05:38:58 -0500 From: Alan Liu To: Subject: [PATCH v2 1/3] drm: Introduce CRTC checksum region and CRC properties Date: Sun, 18 Jun 2023 18:38:45 +0800 Message-ID: <20230618103847.614721-2-HaoPing.Liu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230618103847.614721-1-HaoPing.Liu@amd.com> References: <20230618103847.614721-1-HaoPing.Liu@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|SJ0PR12MB6805:EE_ X-MS-Office365-Filtering-Correlation-Id: 363169f1-2d75-47e8-ca55-08db6fe83d78 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: P74EU5fW5itSETo3Tg8ECgdHP3Uffp2oc8fu5Qsqz0JZrvc4ahsOxXSDc28AWl/yJUobA8226/ZJJnJQMbbygE0ZXpuEAH6gBHMKu8khovi0c1qY5UYqCqBLlEuU4nd6fSsHYKu+bMXE8cnDSpbypchaZqdZLsShARbw+uPg130cTE+ObdclqKrSa/8oVw6uab0h58oWaYoylsKlXIiaC5MMpSer86xFMzqMAAdrxH7gN3u/zbLMghS6tdJ/nlvwVrNgx621sIbGJKNI8tGLXswB7J18X/xuu8GYK++OFYjTXTez4qXwVABpKboKYQobFyWS69oDV5Mrfl2lZfbD89yuIWj01N51vqWi+b76pZmGRt6AAxmgmWbilU2Mh/ncXxqjeaM2zfGmKb7K1R72USfpSjFkq3Mbfdp8AgPRk5N4J8zr0Va5Qdy/J1Tpc5SLBP5NlsdcgGI9edKyf7mBJqkO35hNyRxbxMdRR1Yzo7Q3HaNULeQWOeo0S7xqz9gGSNiWtSMw8Y87ihhITSjZxj+hx/WzSIxlnuZCWktVlmkAjPEpRwHx2M6QqkXbpLxloC7/UD/SjhzXZL+BZr001G0PUNQDw9ZUUF4eCdI0qsCijXHDYq520wOyQjWbtt3TEm1H/2l86Jzg5zuqsOMWumgH+/mugWA16+cmc9vtDZY6ZPIdak2nP2MeVRPQBz4InMz+Q3Z6gkXsUL7Ze2qXNT7zTdlfzy769+4FOFKYZku+cHPOnAJmTgCb8H21BYsDB9m9JruGVEF+FFD3v0NGzQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(346002)(39860400002)(376002)(396003)(136003)(451199021)(36840700001)(40470700004)(46966006)(70586007)(186003)(8676002)(70206006)(8936002)(82740400003)(5660300002)(54906003)(40460700003)(4326008)(6666004)(7696005)(82310400005)(316002)(478600001)(41300700001)(36756003)(26005)(1076003)(6916009)(40480700001)(426003)(336012)(81166007)(356005)(47076005)(86362001)(83380400001)(2906002)(36860700001)(2616005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2023 10:39:05.6385 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 363169f1-2d75-47e8-ca55-08db6fe83d78 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6805 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , Wayne.Lin@amd.com, Lili.Gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduce per-CRTC properties: CHECKSUM_REGION and CHECKSUM_CRC. Userspace can configure a region by setting the region property and retrieve the CRC values from the CRC property to validate the content of the region. Apon userspace submits the 4 coordinate values with checksum_region_enable true, kernel instructs DC hardware to calculate the CRC value accordingly as frames scanned out. The result CRC value of RGB colors are then stored in CHECKSUM_CRC property, with a reference frame count for userspace to know which frame the CRCs are calculated at. Driver can set up these properties for a CRTC by calling drm_crtc_create_checksum_region_properties() and hook its own implementation on new CRTC function update_chechsum_region_crc() to update the values of the CRC property for the incoming userspace request. Signed-off-by: Alan Liu --- drivers/gpu/drm/drm_atomic_state_helper.c | 7 ++++ drivers/gpu/drm/drm_atomic_uapi.c | 21 ++++++++++- drivers/gpu/drm/drm_crtc.c | 44 +++++++++++++++++++++++ include/drm/drm_crtc.h | 43 ++++++++++++++++++++++ include/uapi/drm/drm_mode.h | 42 ++++++++++++++++++++++ 5 files changed, 156 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index dfb57217253b..a8f25575edef 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -143,6 +143,11 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, drm_property_blob_get(state->ctm); if (state->gamma_lut) drm_property_blob_get(state->gamma_lut); + if (state->checksum_region.region_blob) + drm_property_blob_get(state->checksum_region.region_blob); + if (state->checksum_region.crc_blob) + drm_property_blob_get(state->checksum_region.crc_blob); + state->mode_changed = false; state->active_changed = false; state->planes_changed = false; @@ -215,6 +220,8 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state) drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); drm_property_blob_put(state->gamma_lut); + drm_property_blob_put(state->checksum_region.region_blob); + drm_property_blob_put(state->checksum_region.crc_blob); } EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index c06d0639d552..5a934f191940 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -450,6 +450,17 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, set_out_fence_for_crtc(state->state, crtc, fence_ptr); } else if (property == crtc->scaling_filter_property) { state->scaling_filter = val; + } else if (property == crtc->checksum_region_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->checksum_region.region_blob, + val, + -1, sizeof(struct drm_checksum_region), + &replaced); + state->checksum_region.region_changed |= replaced; + return ret; + } else if (property == crtc->checksum_crc_property) { + /* don't let user set CRC data */ + return -EPERM; } else if (crtc->funcs->atomic_set_property) { return crtc->funcs->atomic_set_property(crtc, state, property, val); } else { @@ -487,7 +498,15 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = 0; else if (property == crtc->scaling_filter_property) *val = state->scaling_filter; - else if (crtc->funcs->atomic_get_property) + else if (property == crtc->checksum_region_property) + *val = (state->checksum_region.region_blob) + ? state->checksum_region.region_blob->base.id : 0; + else if (property == crtc->checksum_crc_property) { + if (crtc->funcs->update_checksum_region_crc) + crtc->funcs->update_checksum_region_crc(crtc); + *val = (state->checksum_region.crc_blob) + ? state->checksum_region.crc_blob->base.id : 0; + } else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else return -EINVAL; diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index df9bf3c9206e..07186cb8bfd4 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -955,3 +955,47 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, return 0; } EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property); + +/** + * drm_crtc_create_checksum_region_properties - create new checksum_region + * properties + * + * @crtc: drm CRTC + * + * This function creates and attaches CHECKSUM_REGION and CHECKSUM_CRC blob + * properties for the given CRTC. + * + * RETURNS: + * Zero for success or -ENOMEM + */ +int drm_crtc_create_checksum_region_properties(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_property *region_prop, *crc_prop; + + region_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "CHECKSUM_REGION", 0); + crc_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "CHECKSUM_CRC", 0); + + if (!region_prop || !crc_prop) + goto fail; + + drm_object_attach_property(&crtc->base, region_prop, 0); + drm_object_attach_property(&crtc->base, crc_prop, 0); + + crtc->checksum_region_property = region_prop; + crtc->checksum_crc_property = crc_prop; + + return 0; + +fail: + if (region_prop) + drm_property_destroy(dev, region_prop); + + if (crc_prop) + drm_property_destroy(dev, crc_prop); + + return -ENOMEM; +} +EXPORT_SYMBOL(drm_crtc_create_checksum_region_properties); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 8e1cbc75143e..e588c321eb7a 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -322,6 +322,21 @@ struct drm_crtc_state { */ enum drm_scaling_filter scaling_filter; + /** + * @checksum_region: + * + * Checksum_region properties for configuring the region and retrieving the + * CRC checksum values of the region content. The region_changed is set when + * a new region is set by the userspace. If not NULL, the region_blob is of + * type struct drm_checksum_region and the crc_blob is of type struct + * drm_checksum_crc. + */ + struct { + struct drm_property_blob *region_blob; + struct drm_property_blob *crc_blob; + bool region_changed: 1; + } checksum_region; + /** * @event: * @@ -926,6 +941,22 @@ struct drm_crtc_funcs { int *max_error, ktime_t *vblank_time, bool in_vblank_irq); + + /** + * @update_checksum_region_crc: + * + * Driver callback to update the content of CRTC CHECKSUM_CRC property. + * This function fetches the latest checksum CRC values and replaces the + * old crc_blob in struct drm_crtc_state. + * + * This callback is optional if the driver does not support any CRC + * generation functionality. + * + * RETURNS: + * + * True on success, false on failure. + */ + bool (*update_checksum_region_crc) (struct drm_crtc *crtc); }; /** @@ -1180,6 +1211,17 @@ struct drm_crtc { * Initialized via drm_self_refresh_helper_init(). */ struct drm_self_refresh_data *self_refresh_data; + + /** + * @checksum_region_property: property for checksum region configuration. + */ + struct drm_property *checksum_region_property; + + /** + * @checksum_crc_property: property for retrieving the CRC checksum + * values of the content of checksum region. + */ + struct drm_property *checksum_crc_property; }; /** @@ -1329,4 +1371,5 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, unsigned int supported_filters); +int drm_crtc_create_checksum_region_properties(struct drm_crtc *crtc); #endif /* __DRM_CRTC_H__ */ diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 46becedf5b2f..a2b7d2be94d3 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1303,6 +1303,48 @@ struct drm_mode_rect { __s32 y2; }; +/** + * struct drm_checksum_region - The enablement and region of checksum_region + * @x_start: Horizontal starting coordinate of the region. + * @y_start: Vertical starting coordinate of the region. + * @x_end: Horizontal ending coordinate of the region. + * @y_end: Vertical ending coordinate of the region. + * @checksum_region_enable: To enable or disable checksum_region. + * + * Userspace uses this structure to configure the region and enablement for + * checksum_region. Userspace should not submit a region out of the displayable + * region because there is nothing to display and need protection. + */ +struct drm_checksum_region { + __u32 x_start; + __u32 y_start; + __u32 x_end; + __u32 y_end; + __u8 checksum_region_enable; + __u8 pad[7]; +}; + +/** + * struct drm_checksum_crc - The CRC value of the corresponding checksum region. + * @crc_r: CRC value of red color. + * @crc_g: CRC value of green color. + * @crc_b: CRC value of blue color. + * @frame_count: a referenced frame count to indicate which frame the CRC values + * are generated at. + * + * Userspace uses this structure to retrieve the CRC values of the current + * checksum region. @frame_count will be reset once a new region is updated or + * it reaches a maximum value. Currently these CRC values are designed to + * be validated with pre-saved CRC values, so userspace doesn't need to concern + * about the algorithm used to compute the CRC. + */ +struct drm_checksum_crc { + __u32 crc_r; + __u32 crc_g; + __u32 crc_b; + __u32 frame_count; +}; + #if defined(__cplusplus) } #endif From patchwork Sun Jun 18 10:38:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, HaoPing (Alan)" X-Patchwork-Id: 13283797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CBC0EB64D7 for ; Sun, 18 Jun 2023 10:39:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A46910E061; 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Sun, 18 Jun 2023 05:39:12 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Sun, 18 Jun 2023 03:39:12 -0700 Received: from alan-new-dev.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Sun, 18 Jun 2023 05:39:05 -0500 From: Alan Liu To: Subject: [PATCH v2 2/3] drm/amd/display: Create checksum_region properties and handle new region update Date: Sun, 18 Jun 2023 18:38:46 +0800 Message-ID: <20230618103847.614721-3-HaoPing.Liu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230618103847.614721-1-HaoPing.Liu@amd.com> References: <20230618103847.614721-1-HaoPing.Liu@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FA:EE_|MW6PR12MB8999:EE_ X-MS-Office365-Filtering-Correlation-Id: 389513a8-b1e8-4fc5-ccf9-08db6fe841ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2023 10:39:13.1717 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 389513a8-b1e8-4fc5-ccf9-08db6fe841ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8999 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , Wayne.Lin@amd.com, Lili.Gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This commit creates checksum_region properties at CRTC initialization, and update the new region during the atomic atomic. A new function amdgpu_dm_crtc_set_secure_display_crc_source() is implemented to control the state of CRC engine of DC hardware. Signed-off-by: Alan Liu --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 38 +++++++++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 57 +++++++++++++++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 + .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 5 ++ 4 files changed, 103 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 90de0d37f1d2..26da07a25085 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8870,6 +8870,44 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } } #endif + +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + if (new_crtc_state->active && new_crtc_state->checksum_region.region_changed) { + struct drm_checksum_region *region_data = + (struct drm_checksum_region *)new_crtc_state->checksum_region.region_blob->data; + + if (region_data->checksum_region_enable) { + if (!amdgpu_dm_crc_window_is_activated(crtc)) { + /* Enable secure display: set crc source to "crtc" */ + amdgpu_dm_crtc_set_secure_display_crc_source(crtc, "crtc"); + + /* wait 1 more frame for CRC engine to start */ + acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; + + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + acrtc->dm_irq_params.window_param.activated = true; + spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); + } + + /* Update ROI: copy ROI from crtc_state to dm_irq_params */ + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + acrtc->dm_irq_params.window_param.x_start = region_data->x_start; + acrtc->dm_irq_params.window_param.y_start = region_data->y_start; + acrtc->dm_irq_params.window_param.x_end = region_data->x_end; + acrtc->dm_irq_params.window_param.y_end = region_data->y_end; + acrtc->dm_irq_params.window_param.update_win = true; + spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); + + } else { + if (amdgpu_dm_crc_window_is_activated(crtc)) { + /* Disable secure display: set crc source to "none" */ + amdgpu_dm_crtc_set_secure_display_crc_source(crtc, "none"); + } + } + + new_crtc_state->checksum_region.region_changed = false; + } +#endif } for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 0802f8e8fac5..26017e9fbc4a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -465,6 +465,63 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) } #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) +int amdgpu_dm_crtc_set_secure_display_crc_source(struct drm_crtc *crtc, const char *src_name) +{ + enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); + enum amdgpu_dm_pipe_crc_source cur_crc_src; + struct dm_crtc_state *crtc_state; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + bool enable = false; + bool enabled = false; + int ret = 0; + unsigned long flag; + + if (source < 0) { + DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", + src_name, crtc->index); + return -EINVAL; + } + + enable = amdgpu_dm_is_valid_crc_source(source); + crtc_state = to_dm_crtc_state(crtc->state); + spin_lock_irqsave(&drm_dev->event_lock, flag); + cur_crc_src = acrtc->dm_irq_params.crc_src; + spin_unlock_irqrestore(&drm_dev->event_lock, flag); + + /* Reset secure_display when we change crc source */ + amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream); + + if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { + ret = -EINVAL; + goto cleanup; + } + + /* + * Reading the CRC requires the vblank interrupt handler to be + * enabled. Keep a reference until CRC capture stops. + */ + enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); + if (!enabled && enable) { + ret = drm_crtc_vblank_get(crtc); + if (ret) + goto cleanup; + + } else if (enabled && !enable) { + drm_crtc_vblank_put(crtc); + } + + spin_lock_irqsave(&drm_dev->event_lock, flag); + acrtc->dm_irq_params.crc_src = source; + spin_unlock_irqrestore(&drm_dev->event_lock, flag); + + /* Reset crc_skipped on dm state */ + crtc_state->crc_skip_count = 0; + +cleanup: + return ret; +} + void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) { struct drm_device *drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 748e80ef40d0..f4765bcae840 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -97,10 +97,13 @@ bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc); void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc); struct secure_display_context *amdgpu_dm_crtc_secure_display_create_contexts( struct amdgpu_device *adev); +int amdgpu_dm_crtc_set_secure_display_crc_source(struct drm_crtc *crtc, + const char *src_name); #else #define amdgpu_dm_crc_window_is_activated(x) #define amdgpu_dm_crtc_handle_crc_window_irq(x) #define amdgpu_dm_crtc_secure_display_create_contexts(x) +#define amdgpu_dm_crtc_set_secure_display_crc_source(x) #endif #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 440fc0869a34..e94fe4a7e492 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -461,6 +461,11 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, dm->adev->mode_info.crtcs[crtc_index] = acrtc; +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + if (drm_crtc_create_checksum_region_properties(&acrtc->base)) + DRM_ERROR("amdgpu: failed to create checksum region properties.\n"); +#endif + /* Don't enable DRM CRTC degamma property for DCE since it doesn't * support programmable degamma anywhere. */ From patchwork Sun Jun 18 10:38:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, HaoPing (Alan)" X-Patchwork-Id: 13283798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55698EB64D8 for ; Sun, 18 Jun 2023 10:39:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC20210E06C; Sun, 18 Jun 2023 10:39:26 +0000 (UTC) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2056.outbound.protection.outlook.com [40.107.220.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id D37B410E06C for ; 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Sun, 18 Jun 2023 03:39:19 -0700 Received: from alan-new-dev.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Sun, 18 Jun 2023 05:39:12 -0500 From: Alan Liu To: Subject: [PATCH v2 3/3] drm/amd/display: Implement the retrieval of checksum_region's CRC data Date: Sun, 18 Jun 2023 18:38:47 +0800 Message-ID: <20230618103847.614721-4-HaoPing.Liu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230618103847.614721-1-HaoPing.Liu@amd.com> References: <20230618103847.614721-1-HaoPing.Liu@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|PH0PR12MB7485:EE_ X-MS-Office365-Filtering-Correlation-Id: a29d26fe-9662-4f07-ca18-08db6fe84613 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m+R3S7i/WRm+utOBif1bmqhGWqQ7V0XJW8+9XjANcQNJjcbpGyi9xhczYRRRBZ7jxWIkp+sa4OQZ7sGJFPMy7meBIHkc4NYC62tauhmO2RMTcySoK/8XSbEBYvoS1ILv9TxNzIdQmKNGLBoFQzn6hE+sAJTB0FFJUo3HTFTip2xFldCaOmus96+7gdi+i2z6xWuDcD6i+JG0k2cOpT7yEV4QEf8N9KHmF9c4r0OfSQbggyN4ru2efM2myx0bKR7+EKnVkZekT5HvyM7wixRy/rLyHerBMpA/Gk3PSNsoFvWYs/OZvI7WJT2Zw7HLRn5idKITO8UOJ2OD0duyImFI/cRnA/2d4StjNLo1vlR0abLG0AvKDz+/Hrd+kAyGIUunJgB/n9o3jaZJ1W+SMDem2GxQW9f6qYnB5w9t/7dt1R/3JAc31FPHYXVQX9QMsUpRbHLRiEtJ2lJFrHJulHz//blUqPFFOon4dpv13+ZpmQWMUHUcwqni1c2vmC5hrsPCr6MkzwAA9hEuh1xnxCVfof8eSYXqP7ed0dksMCARly4/2voRsk/UUbo08jqAQ4zGkcOs8n7548cv4swPNOGceZQ7Qu8FeM2oG3me4TRhNcbQ0Qy3BsPphxHxPc8mpO2aDa5w0rZALhDRPZRxsHUeEiPXIq/lD42IvFWHThvlaX4w2j55Ns30R/13TssOPFKqTZosOtiCEuEFHftiCfBDUXByOcDXxKfjjcOZNqlMLpcsICgqG2/hZosEyxVk+9ArJspALhxsTajUP60qGTGeTw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(396003)(39860400002)(136003)(346002)(376002)(451199021)(36840700001)(40470700004)(46966006)(40480700001)(36860700001)(426003)(336012)(47076005)(83380400001)(6916009)(70206006)(70586007)(1076003)(26005)(7696005)(6666004)(4326008)(478600001)(2616005)(54906003)(186003)(86362001)(2906002)(8676002)(8936002)(5660300002)(36756003)(40460700003)(82740400003)(81166007)(356005)(41300700001)(316002)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2023 10:39:20.0917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a29d26fe-9662-4f07-ca18-08db6fe84613 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7485 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Liu , Wayne.Lin@amd.com, Lili.Gong@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Retrieve and store checksum_region's CRC data from the DC hardware in vline0 irq handler. A new function amdgpu_dm_crtc_update_checksum_region_crc() is implemented and hooked to CRTC callback for updating the latest CRC values to the checksum CRC blob. Signed-off-by: Alan Liu --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 55 +++++++++++++++---- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 11 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 47 ++++++++++++++++ 4 files changed, 110 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 26da07a25085..9fd08281fe27 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8877,7 +8877,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) (struct drm_checksum_region *)new_crtc_state->checksum_region.region_blob->data; if (region_data->checksum_region_enable) { + struct secure_display_context *secure_display_ctx = + &dm->secure_display_ctxs[acrtc->crtc_id]; + if (!amdgpu_dm_crc_window_is_activated(crtc)) { + init_completion(&secure_display_ctx->crc.completion); + /* Enable secure display: set crc source to "crtc" */ amdgpu_dm_crtc_set_secure_display_crc_source(crtc, "crtc"); @@ -8887,7 +8892,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); acrtc->dm_irq_params.window_param.activated = true; spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); - } + } else + reinit_completion(&secure_display_ctx->crc.completion); /* Update ROI: copy ROI from crtc_state to dm_irq_params */ spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 26017e9fbc4a..f881ccd93a25 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -529,6 +529,8 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) struct amdgpu_crtc *acrtc = NULL; struct amdgpu_device *adev = NULL; struct secure_display_context *secure_display_ctx = NULL; + bool reset_crc_frame_count = false, crc_is_updated = false; + uint32_t crc[3] = {0}; unsigned long flags1; if (crtc == NULL) @@ -543,15 +545,14 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) /* Early return if CRC capture is not enabled. */ if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) || - !dm_is_crc_source_crtc(cur_crc_src)) - goto cleanup; - - if (!acrtc->dm_irq_params.window_param.activated) - goto cleanup; + !dm_is_crc_source_crtc(cur_crc_src)) { + spin_unlock_irqrestore(&drm_dev->event_lock, flags1); + return; + } - if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { - acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; - goto cleanup; + if (!acrtc->dm_irq_params.window_param.activated) { + spin_unlock_irqrestore(&drm_dev->event_lock, flags1); + return; } secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id]; @@ -562,16 +563,23 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) secure_display_ctx->crtc = crtc; } + if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { + acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; + goto cleanup; + } + if (acrtc->dm_irq_params.window_param.update_win) { /* prepare work for dmub to update ROI */ secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start; secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start; secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end - - acrtc->dm_irq_params.window_param.x_start; + acrtc->dm_irq_params.window_param.x_start; secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end - - acrtc->dm_irq_params.window_param.y_start; + acrtc->dm_irq_params.window_param.y_start; schedule_work(&secure_display_ctx->forward_roi_work); + reset_crc_frame_count = true; + acrtc->dm_irq_params.window_param.update_win = false; /* Statically skip 1 frame, because we may need to wait below things @@ -582,12 +590,39 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; } else { + struct dc_stream_state *stream_state = to_dm_crtc_state(crtc->state)->stream; + + if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, + &crc[0], &crc[1], &crc[2])) + DRM_ERROR("Secure Display: fail to get crc\n"); + else + crc_is_updated = true; + /* prepare work for psp to read ROI/CRC and send to I2C */ schedule_work(&secure_display_ctx->notify_ta_work); } cleanup: spin_unlock_irqrestore(&drm_dev->event_lock, flags1); + + spin_lock_irqsave(&secure_display_ctx->crc.lock, flags1); + + if (reset_crc_frame_count || secure_display_ctx->crc.frame_count == UINT_MAX) + /* Reset the reference frame count after user update the ROI + * or it reaches the maximum value. + */ + secure_display_ctx->crc.frame_count = 0; + else + secure_display_ctx->crc.frame_count += 1; + + if (crc_is_updated) { + secure_display_ctx->crc.crc_R = crc[0]; + secure_display_ctx->crc.crc_G = crc[1]; + secure_display_ctx->crc.crc_B = crc[2]; + complete_all(&secure_display_ctx->crc.completion); + } + + spin_unlock_irqrestore(&secure_display_ctx->crc.lock, flags1); } struct secure_display_context * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index f4765bcae840..7c7bd5922b7b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -40,6 +40,15 @@ enum amdgpu_dm_pipe_crc_source { }; #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +struct crc_data { + uint32_t crc_R; + uint32_t crc_G; + uint32_t crc_B; + uint32_t frame_count; + spinlock_t lock; + struct completion completion; +}; + struct crc_window_param { uint16_t x_start; uint16_t y_start; @@ -64,6 +73,8 @@ struct secure_display_context { /* Region of Interest (ROI) */ struct rect rect; + + struct crc_data crc; }; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index e94fe4a7e492..b673338f048d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -280,6 +280,50 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc) __drm_atomic_helper_crtc_reset(crtc, &state->base); } +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY +static bool amdgpu_dm_crtc_update_checksum_region_crc(struct drm_crtc *crtc) +{ + struct amdgpu_device *adev = drm_to_adev(crtc->dev); + struct drm_crtc_state *crtc_state = crtc->state; + struct secure_display_context *secure_display_ctx = + &adev->dm.secure_display_ctxs[crtc->index]; + struct drm_checksum_crc *new_data; + struct drm_property_blob *new_blob, **old_blob; + unsigned long flag; + + if (!amdgpu_dm_crc_window_is_activated(crtc)) + goto fail; + + wait_for_completion_interruptible_timeout( + &secure_display_ctx->crc.completion, 10 * HZ); + + new_blob = drm_property_create_blob(crtc->dev, + sizeof(struct drm_checksum_crc), + NULL); + if (IS_ERR(new_blob)) + goto fail; + + /* save new value to blob */ + new_data = (struct drm_checksum_crc *) new_blob->data; + spin_lock_irqsave(&secure_display_ctx->crc.lock, flag); + new_data->crc_r = secure_display_ctx->crc.crc_R; + new_data->crc_g = secure_display_ctx->crc.crc_G; + new_data->crc_b = secure_display_ctx->crc.crc_B; + new_data->frame_count = secure_display_ctx->crc.frame_count; + spin_unlock_irqrestore(&secure_display_ctx->crc.lock, flag); + + old_blob = &crtc_state->checksum_region.crc_blob; + if (!drm_property_replace_blob(old_blob, new_blob)) + goto fail; + + return true; + +fail: + DRM_WARN("Checksum Region: fail to update checksum_region CRC\n"); + return false; +} +#endif + #ifdef CONFIG_DEBUG_FS static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) { @@ -307,6 +351,9 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY + .update_checksum_region_crc = amdgpu_dm_crtc_update_checksum_region_crc, +#endif }; static void dm_crtc_helper_disable(struct drm_crtc *crtc)