From patchwork Mon Jun 19 13:16:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 13284502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74046EB64DA for ; Mon, 19 Jun 2023 13:17:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=MXo0cEJ9l+KyerSRKpirlBF0AVEfZ+IIU1PbBWzUpkg=; b=WnLLS3yQSm3hXP klPFur9Gxb8wasc4+fD7tgrLgwygIYvj/1Myq2aeodRAVNnKZYHLO1w6PA8aNhbk9S73syfbiwasB TZrsyGFgC8wSSLprMjK2p2M8wk8jAdUqPdLPn5cJ31Q5p8MOyw/kaQWgrTnh6qZvCJONBZOZIWgOt vYSqWw5BINC/CXsGoxvI5aTY0MuHUCD/bQo4XjSzioIPjrztEqMZEWSWZScx2GpfnwZTplEg6hEBM w7XEFtYTun3m2i+GSo3W26XIn76qTid2nzyASdraOAlxVuMKUEJIJwwGHYor6/5ep4pQjrJ94KBM9 HTOEIOe3kfg+FYwWH2Uw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qBEkH-008Y3a-2n; Mon, 19 Jun 2023 13:16:37 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qBEkF-008Y36-0H for linux-arm-kernel@lists.infradead.org; Mon, 19 Jun 2023 13:16:36 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 35JDGMDK068789; Mon, 19 Jun 2023 08:16:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1687180582; bh=3Z2P91KL2E+qTXo1jtnMpvVUcnVeBnGAlUxA+ENl8Sc=; h=From:To:CC:Subject:Date; b=RGwgGSwy8nYNEqAHLpn9r50uLFEYvh2sVzCP+iLvJd5jt5iSR+R7dNgZoBPq+FS5G zlRt16qlS1cdNoSTLfc7vgJ4O4w4NeyZQTsNhOnFKKwYau4Hnoge93SqBPyhZvOEDh FGN+jyuTejfPUsLxFj1wlN8Nok1Vdo8hQ6EnCh7Y= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 35JDGMxJ002521 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 19 Jun 2023 08:16:22 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 19 Jun 2023 08:16:22 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 19 Jun 2023 08:16:22 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 35JDGMtM048714; Mon, 19 Jun 2023 08:16:22 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring CC: , , , Tero Kristo , Vignesh Raghavendra , Nishanth Menon Subject: [PATCH V2] arm64: dts: ti: k3-pinctrl: Introduce debounce select mux macros Date: Mon, 19 Jun 2023 08:16:20 -0500 Message-ID: <20230619131620.3286650-1-nm@ti.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230619_061635_226363_6638F05D X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce the debounce select mux macros to allow folks to setup debounce configuration for pins. Each configuration selected maps to a specific timing register as documented in appropriate Technical Reference Manual (example:[1]). [1] AM625x TRM (section 6.1.2.2): https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra --- Changes since V1: - I have'nt picked up Krystoff's ack since the file modified is now different. - Changes now applied to k3-pinctrl.h instead of the ABI header that is now set up to be deleted in v6.5-rc1. V1: https://lore.kernel.org/linux-devicetree/20230308084309.396192-1-nm@ti.com/ arch/arm64/boot/dts/ti/k3-pinctrl.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index c97548a3f42d..6004e0967ec5 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -11,6 +11,7 @@ #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DEBOUNCE_SHIFT (11) #define PULL_DISABLE (1 << PULLUDEN_SHIFT) #define PULL_ENABLE (0 << PULLUDEN_SHIFT) @@ -29,6 +30,14 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) +#define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) + #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))