From patchwork Mon Jun 19 15:04:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284672 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8371C0015E for ; Mon, 19 Jun 2023 15:05:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231778AbjFSPF2 (ORCPT ); Mon, 19 Jun 2023 11:05:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229657AbjFSPFI (ORCPT ); Mon, 19 Jun 2023 11:05:08 -0400 Received: from mail-oa1-x34.google.com (mail-oa1-x34.google.com [IPv6:2001:4860:4864:20::34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F68610E4 for ; Mon, 19 Jun 2023 08:04:22 -0700 (PDT) Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-1a49716e9c5so3655979fac.1 for ; Mon, 19 Jun 2023 08:04:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187061; x=1689779061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0m9rhWOn8qYbjuVQmQ20zeGCmNCpO//YkkWL6MmvNwg=; b=X4rnGsDhhgcstlEOl2O8Xh0D75fvA4vp4Lp/Hch/7e27uzGYUexdfNn8ekHr0mFBme xRW2Jgigs40z3tnW83vRGWXtbHyCNxWMrMBZJ6b1+dj/QesU3nVfa2PCr01i4TxFgyl5 JBfJcs93mVxfsGsi6e5la8UBwnx4Ipd7LNTUrMxmhu+eV0oXz/Fh8ARus8WzXPrPV/RS lHTfF2qz+tPJkpSeHgniix7/lRe+ods8MgZJ1EIpBI2htcjR7+uqSkL5vkczsm7R2HpG aU2lpY8HphbspEUze2dxaRhc3sjMSJ+IqLTvOqRFsi5UolLc0LtUzb8u+bMHAMdKZW1N WU3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187061; x=1689779061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0m9rhWOn8qYbjuVQmQ20zeGCmNCpO//YkkWL6MmvNwg=; b=Il6CCd2391mBfOb5d4Wj31iZ3cfY38affyqmbD/3CQzx1H5WDVINrPuiCHWxQEcy4c v3uJfGdqwyMW25tIbU4DspHcY61salOsKvUh3+41QcrPQAEgLDJWT2XhNLFFeWdbgK5o YjOPSV5id2dQ7nbgp9utCr7eDsfh7Q/1bvTB5/rOktLMlxBTHN0oo1Ni3Ukz9jpVOqcv 2NsGEouQfxXkWNuid+l4LSQNj8+RI9aDxTXgAmA+ULND/MoTcXVTET4WD3us3/FdD6K9 M/cPnGwUcjC+GjPOEJ1xGMm1xCbIRO/vDYByy1z0p8bri2YSKT7zTYk70BNVqR+7ON5q Zqcg== X-Gm-Message-State: AC+VfDywKAm0R7dgmcbUirW/VjT3gE4HXB+wVKBmVfu2lBZcqe4615pt cDxn8SSsNmJyXK0y3tiShKF3 X-Google-Smtp-Source: ACHHUZ5vRE7brlsRPe3Zp8R6nDsOTJqauqzXZH+wyitHVFyn/PXC/KWiff8ZoBlpQBA7Fut4l4DxOw== X-Received: by 2002:a05:6870:4710:b0:18f:558a:1f51 with SMTP id b16-20020a056870471000b0018f558a1f51mr11017078oaq.53.1687187061309; Mon, 19 Jun 2023 08:04:21 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:20 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v4 1/9] PCI: qcom: Disable write access to read only registers for IP v2.3.3 Date: Mon, 19 Jun 2023 20:34:00 +0530 Message-Id: <20230619150408.8468-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. Cc: Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4ab30892f6ef..ef385d36d653 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -836,6 +836,8 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); + dw_pcie_dbi_ro_wr_dis(pci); + return 0; } From patchwork Mon Jun 19 15:04:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284674 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60B9FC001DD for ; Mon, 19 Jun 2023 15:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229695AbjFSPFb (ORCPT ); Mon, 19 Jun 2023 11:05:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230083AbjFSPFK (ORCPT ); Mon, 19 Jun 2023 11:05:10 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1D2DE78 for ; Mon, 19 Jun 2023 08:04:25 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-25ee8d84b4fso1503626a91.0 for ; Mon, 19 Jun 2023 08:04:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187065; x=1689779065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B3Dy+kmf8ZISKkCa0j/2ldqP//6MEtxXXYzBp48Kt14=; b=vtWdf8pUd95J6h7vr8vtdO30v//wqJANxXMEAkrewzCtyzASzN6R1KCTHyzYqpE4XQ hT2kjH2LwEyWdUVa4l+QKByViVVB3fDKG589hDa2B/GS61bFgtH+ehQeoiGkasGegRpT YQx9WvmTyBkaBEXT8Br5Lw/JrB0Ls9D8M5+/Z7CN0NCZmzBFuhT9LpZE4Mfddpg8iiJB qYKTrgxOMkA5GiRUJ49ooaOW55zu4RQ+IbRQgq55Naz61UT/c70rzn9DvhG+UMzQVjsF jUk0ALOCs2vziKBb4OHIaKfoPmUib0Swi38K7NWzs4xSpQQxbr5Io76IuGCZcrAT2BCt ImLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187065; x=1689779065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B3Dy+kmf8ZISKkCa0j/2ldqP//6MEtxXXYzBp48Kt14=; b=Do5/jOgM8TxVjU4d5YHlbo/ETC45p5NXd4WCo/ZWo0/02mvH8BlZW7L1Lqpny/UauR 5bn9E1WvecLE8YHTgNR3+zX0SFgNNj6V1piFwdzsh2pkjX/nPofNuFUhD0MmuJpqPYme ld18sIHrq3VvFjHy+oZJNK1JHIdvJtllsRJNQJ7+XWUmCNp5Dtbjhc0qM05GUQE6TXUs hsTz6EbAUc9ZmjlxhGJE6iqIKjaZAmc8iYcL1NuAKF6nXoSZsmwLdJUZyEY+UIS5vhLt 3H7pgSnyHHzuwWYZW+HBj96DYld0TMX8LJngMgVuCwKd5nZ0TG129hBSckoauBFuN333 Kx5w== X-Gm-Message-State: AC+VfDxVg6+fNSNcm71Pn/LbXSz1cBhwlI0OuSObK4c8n6KVD5hO6Sof XmaWrtGiFCx+v5H8sKLZejW5 X-Google-Smtp-Source: ACHHUZ4qUQ3hwY9mNHMbObMwBwLYFeY8h8minGqKyB/SxZiGDuFVPaHBPp6CG8/MfyFm+ePr+YTp5A== X-Received: by 2002:a17:90a:e516:b0:25e:8f12:a74d with SMTP id t22-20020a17090ae51600b0025e8f12a74dmr9926485pjy.44.1687187065087; Mon, 19 Jun 2023 08:04:25 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:24 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 2/9] PCI: qcom: Use DWC helpers for modifying the read-only DBI registers Date: Mon, 19 Jun 2023 20:34:01 +0530 Message-Id: <20230619150408.8468-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DWC core already exposes dw_pcie_dbi_ro_wr_{en/dis} helper APIs for enabling and disabling the write access to read only DBI registers. So let's use them instead of doing it manually. Also, the existing code doesn't disable the write access when it's done. This is also fixed now. Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ef385d36d653..01795ee7ce45 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -61,7 +61,6 @@ /* DBI registers */ #define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c -#define MISC_CONTROL_1_REG 0x8bc /* MHI registers */ #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 @@ -132,9 +131,6 @@ /* AXI_MSTR_RESP_COMP_CTRL1 register fields */ #define CFG_BRIDGE_SB_INIT BIT(0) -/* MISC_CONTROL_1_REG register fields */ -#define DBI_RO_WR_EN 1 - /* PCI_EXP_SLTCAP register fields */ #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) @@ -826,7 +822,9 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) writel(0, pcie->parf + PARF_Q2A_FLUSH); writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); - writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG); + + dw_pcie_dbi_ro_wr_en(pci); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); From patchwork Mon Jun 19 15:04:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284673 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE7F3C001B3 for ; Mon, 19 Jun 2023 15:05:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230455AbjFSPFa (ORCPT ); Mon, 19 Jun 2023 11:05:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbjFSPFL (ORCPT ); Mon, 19 Jun 2023 11:05:11 -0400 Received: from mail-oi1-x231.google.com (mail-oi1-x231.google.com [IPv6:2607:f8b0:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBE1719AB for ; Mon, 19 Jun 2023 08:04:29 -0700 (PDT) Received: by mail-oi1-x231.google.com with SMTP id 5614622812f47-39eab4bcee8so2116559b6e.0 for ; Mon, 19 Jun 2023 08:04:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187069; x=1689779069; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KnYTPbLQMWkMCSqucReygW86UFXzEWRo6n6RYpHSl6Q=; b=yWd0G0ny+PmbdNeLBRGorz5mIOaQFrNwDntf5+renDW0fy412pD6JDBOdc+4S/CceP kgVH8/2BcsQ8og92IG+bF11zWQSMcmkiWcwY9TDDT6VtzQ/tVwq2o01g/xJzkd0tyTLj PEz+1SUZ1H39Pta0aAOe96LpDclPfkJM2qZM+DFUua25auQVZkvnW7ZirZ9KZKTxwG7R +0t6SYE0udQkuIfMiCQglLqqgrjobH76m7GmBeXSN6jyOjmE27uBV1gQlc8Y8YY8ak4L 7sWx9wuUjS0HkLELy60r0spaD+h0mlyJ3pGbS3R062GkeSwQUeiFfmXI9XpuJXjjkx+U zKvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187069; x=1689779069; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KnYTPbLQMWkMCSqucReygW86UFXzEWRo6n6RYpHSl6Q=; b=NW88jCi53ZQydNlRRLTMyRYPOzQbNl4FFR4UgPIYOS4YoPZY0psFYlcYAy+FMpiffX fwISpi1S6UA3sS0YhI58Vd7P0S40/Zwv7TTuyvIQFF93kVrn+yGGqSoHq6CjH8ca52or jiCrzzw7Z3qIX7LwNDtUkPqH76Dh8ep6n9dcAh0P7reEegBp3tN2ynnZqsUC3GXVgTqt +dRgI/uOKgw8FS09GAR/Wlrt1Th1fLLm28BLLy+ueFsrWFXY7Oj3X3obwCZTbnVYZAYf nV4a2b9GQFSNOkv+m88TyAQJXXejrbMzXQVlrqWf9CP3LcwxTrWadHfkzQ0IiBDVwB69 C0nA== X-Gm-Message-State: AC+VfDyMDjOOv6JWcSxHkZThv2ddWQ0X48xmd+59g58yW9FJXKmrsQDq WZEY1Ev+t/UKWxDPmr0N7sWs X-Google-Smtp-Source: ACHHUZ7wBeSAiIUYQJsKlfpNCJ9nrtg1ZRSoqtpfVEl/vL4msN1p3aq/MZxsBXrCKD3ygAu0a7+x1w== X-Received: by 2002:a05:6808:1455:b0:39a:a880:50dc with SMTP id x21-20020a056808145500b0039aa88050dcmr14860675oiv.52.1687187069106; Mon, 19 Jun 2023 08:04:29 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:28 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 3/9] PCI: qcom: Disable write access to read only registers for IP v2.9.0 Date: Mon, 19 Jun 2023 20:34:02 +0530 Message-Id: <20230619150408.8468-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. While at it, let's also add a newline after existing dw_pcie_dbi_ro_wr_en() guard function to align with rest of the driver. Fixes: 0cf7c2efe8ac ("PCI: qcom: Add IPQ60xx support") Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 01795ee7ce45..391a45d1e70a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1136,6 +1136,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) writel(0, pcie->parf + PARF_Q2A_FLUSH); dw_pcie_dbi_ro_wr_en(pci); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); @@ -1145,6 +1146,8 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); + dw_pcie_dbi_ro_wr_dis(pci); + for (i = 0; i < 256; i++) writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); From patchwork Mon Jun 19 15:04:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284676 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C920EB64DB for ; Mon, 19 Jun 2023 15:05:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbjFSPFe (ORCPT ); Mon, 19 Jun 2023 11:05:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230182AbjFSPFQ (ORCPT ); Mon, 19 Jun 2023 11:05:16 -0400 Received: from mail-oa1-x34.google.com (mail-oa1-x34.google.com [IPv6:2001:4860:4864:20::34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F67819B0 for ; Mon, 19 Jun 2023 08:04:33 -0700 (PDT) Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-1a9d57f8f9fso3311712fac.3 for ; Mon, 19 Jun 2023 08:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187073; x=1689779073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A98UhrwZrGyc1cxKVoW5P/FDL2aF5ZgMxYnhHsr36+Y=; b=EbDKlvCL0JefPd3whitlUpQhGUTNoSgjlKumRPfJJUtaRaRyJi+GXgBe31dGYr55C9 ooZUsmxAmjAppZ5UZ+pVq90G5rEuSmRRGezO0LHbpNsr0QBgX/e2E8trhwuUHjO1yboz IRGB2OQ4ucJyQBP+bUdwxIgscucJ1rALjFg6TBzngbUBHOD8yI8VZoJ+URb1UngfQi+R 1QjQXE4M89eAna+gUWYkhhDfYPqpcFOv2RDAWpYni6BG119UbCn8Ufsg5BjcyLIh/cUq niy86RbSU38dkxt+ppkH+YyH6w+dfqv88OPDc1LsJILqrDaL9+6bAAQXbBuxS11oViJJ xtDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187073; x=1689779073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A98UhrwZrGyc1cxKVoW5P/FDL2aF5ZgMxYnhHsr36+Y=; b=h9zaGJjtXbYKuV3Pf/uYaUW92qhZYoD9ZZIeu7psyD6N7H/qUFqkWT3hF1TJ4AvHH8 PQhgBqHSbYdw4tr3G4tfN6qV9mYx0mxxRh5w2e9+5fKvarv3E5wWUmP8lvegFSn6YsnE dkEkbsS0m/c/mfjuoKKFILCfvyRx3FeEFoVKZr70Zc4lUVIE0VrrdzqFmr4blowhA7LW i4qtTPCn3wq9rkec79sl8Zzg0YSoUGH8gIEmehADAEm0rV5Gj9EXYo0Pvhx2JG9OrxSe bJGxEhMdhHc7ZY1SCaV9/8C211PCN5nqEdhw15TykjL3D17SckjP+wb3v2e+alhzdH2D wa8Q== X-Gm-Message-State: AC+VfDwKq2wMu+ubzxMBHyHEc0FCIMjV9PYCfh/lq7z5WBVh+PDehU2A TSRxImS0epKCt5U09JxHcRZ1 X-Google-Smtp-Source: ACHHUZ5SNI/kwXJznqe6EkZb9zy0U9dMvylpUymgT1TDx1gqUr+yiw95cWcUBffVD5qvzPCw77UOnw== X-Received: by 2002:a05:6871:894:b0:1a2:cfd7:bfdc with SMTP id r20-20020a056871089400b001a2cfd7bfdcmr12096478oaq.6.1687187072875; Mon, 19 Jun 2023 08:04:32 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:32 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 4/9] PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and v1.9.0 Date: Mon, 19 Jun 2023 20:34:03 +0530 Message-Id: <20230619150408.8468-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SoCs making use of Qcom PCIe controller IPs v2.7.0 and v1.9.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 391a45d1e70a..8f448156eccc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -270,6 +270,20 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) return 0; } +static void qcom_pcie_clear_hpc(struct dw_pcie *pci) +{ + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); + val &= ~PCI_EXP_SLTCAP_HPC; + writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); + + dw_pcie_dbi_ro_wr_dis(pci); +} + static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) { u32 val; @@ -966,6 +980,13 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } +static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) +{ + qcom_pcie_clear_hpc(pcie->pci); + + return 0; +} + static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; @@ -1272,6 +1293,7 @@ static const struct qcom_pcie_ops ops_2_3_3 = { static const struct qcom_pcie_ops ops_2_7_0 = { .get_resources = qcom_pcie_get_resources_2_7_0, .init = qcom_pcie_init_2_7_0, + .post_init = qcom_pcie_post_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; @@ -1280,6 +1302,7 @@ static const struct qcom_pcie_ops ops_2_7_0 = { static const struct qcom_pcie_ops ops_1_9_0 = { .get_resources = qcom_pcie_get_resources_2_7_0, .init = qcom_pcie_init_2_7_0, + .post_init = qcom_pcie_post_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .config_sid = qcom_pcie_config_sid_1_9_0, From patchwork Mon Jun 19 15:04:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284675 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D81AFC001DF for ; Mon, 19 Jun 2023 15:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230288AbjFSPFb (ORCPT ); Mon, 19 Jun 2023 11:05:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230344AbjFSPFR (ORCPT ); Mon, 19 Jun 2023 11:05:17 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40BBA19B6 for ; Mon, 19 Jun 2023 08:04:37 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-25e836b733eso1757454a91.0 for ; Mon, 19 Jun 2023 08:04:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187077; x=1689779077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yzV1ZtX30jIpTNOGlDajFE+kq9Q8oevaq3YwpxK0i1A=; b=fMVP0famGSK6/m4FcwKj+6ky062gCAOpAnkt/sZ2VGVyb9dams7xgPlZYxk2abPxAG M7rAhy87w27XFGQiuj/RBnSRZ1V9JweXWRs1qPWV20UAdE4D0VrCKnAxFS1q69ya3g7s GEBJia4tmb1PaEItzzIDpwgyf539obnQeFocpPD+XUEV94cQCtBCAs/RCrTaxpKuLsJi yzSwbHbtKHCaXldbqJ0COxxfYkOnD0rSu2TjNR0OWe4thdYAnTYcbAVtWgXnIj7Kb0Do CYIeAW2J7oEsqWd49SD8CVlzRIVEJJ8UZvLiuOLdzQzU5NMcYUQah2L/6cWtUTonDRdy ZC2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187077; x=1689779077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yzV1ZtX30jIpTNOGlDajFE+kq9Q8oevaq3YwpxK0i1A=; b=BE+yFlgTsQqBSZbFFA/X9jj4dNDq6DUv8c0QMfgfLsQWDLK3rRwcw+80bJjwkdH+W+ 1Bus/VbkhEC7Kj3wonOaWiFVrdo07AjlEQUkYNWAkIKvNFqfOKFcQip+P96xW0vu12BW Xl7YWyak3XxbBe3AH9qc96BsZzh8+tpzoOWR084N1dfPAsx5iOAPTQXhSHytNE9EVlyn /qGMTWw8SVPfPpaH7HxUCYNjo8vinJ9hIe6+KKiIoLBwmdYPGn5FscWF3zNTCfbY319c QUV/YoIcb7HcpZAcwk8zIgJlUP42TJjD6rs5ttFEmju5koXB9Xs1G9HfVGJZR9gmYMhK +gSQ== X-Gm-Message-State: AC+VfDwpHS0I3d4Nfz4AornQt0qKizPq6PUKpVLIkgDiZvxZr0X6za0S v+ZFKWtLdfsPYQGWLyJTcqZs X-Google-Smtp-Source: ACHHUZ60YQ5YnGIsrISqp6t96KlcerAHzAtsdaB8aBfOYilDFQxsVATkWg+lo2y3VZkqEC3vTnEmLQ== X-Received: by 2002:a17:90a:656:b0:259:343:86b5 with SMTP id q22-20020a17090a065600b00259034386b5mr7427310pje.47.1687187076753; Mon, 19 Jun 2023 08:04:36 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:36 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 5/9] PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0 Date: Mon, 19 Jun 2023 20:34:04 +0530 Message-Id: <20230619150408.8468-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SoCs making use of Qcom PCIe controller IPs v2.3.3 and v2.9.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's not set the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Tested-by: Sricharan Ramabadhran Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8f448156eccc..64b6a8c6a99d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -140,7 +140,6 @@ PCI_EXP_SLTCAP_AIP | \ PCI_EXP_SLTCAP_PIP | \ PCI_EXP_SLTCAP_HPS | \ - PCI_EXP_SLTCAP_HPC | \ PCI_EXP_SLTCAP_EIP | \ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) From patchwork Mon Jun 19 15:04:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284685 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D8EDEB64DA for ; Mon, 19 Jun 2023 15:06:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229817AbjFSPGK (ORCPT ); Mon, 19 Jun 2023 11:06:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230511AbjFSPFT (ORCPT ); Mon, 19 Jun 2023 11:05:19 -0400 Received: from mail-oa1-x2f.google.com (mail-oa1-x2f.google.com [IPv6:2001:4860:4864:20::2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37D8A10C7 for ; Mon, 19 Jun 2023 08:04:41 -0700 (PDT) Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-1aa291b3fc4so997881fac.0 for ; Mon, 19 Jun 2023 08:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187080; x=1689779080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ltCiTsDOD5ydUGLVe1beQMJS2WLXn803YOi09x8rHPs=; b=RxWkwsnVaP8PkS+Iu4kSHBZxSZwvPpQ+s508UcLy+kyDeCLsGxKmiLpVWFg2PF8BV8 qHvx7HgeTREoO61gDGcC6iocs6OzDVNKR5mXRpAhSdTH+cjqgCj2/4AZuCTbFUp5BQ86 vRP8zT38xgSQpJurbkYnPowLjIjy1oXWE3Y9+Sy3tdESLZSM/LT9GbHjKDU76pMjLcJR TpV6/1IhdBV6+qT5qPhXMeXm7WTVqixTfEnBF2jD9+prcCNOoPjXFWZ+PmMLL5FTHasj nv0W4B2sAd5KKZeKfkQ2at0ZkrNKaZ0zxoMuY1RJ77gG+5qIcj47SAoxTzEfu37ytEAC wgog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187080; x=1689779080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ltCiTsDOD5ydUGLVe1beQMJS2WLXn803YOi09x8rHPs=; b=PIs4MRWDpKVctIvlxbdgpUucdyKgQaPpmLMSa8npE61oD03GFM3lzANZgkcXDGVTJ/ /vBLc2hHuLFVIuwhO2RoMw1RjH9nuS4t9i60kpHGNiDj/rJall3M3qikL7paGPzS+L8A A2xDpqlI37WJuma0cFbRZCxNDLJt5ocrsLwvIIej6Dw67QPGvSqsjUUysILqFu9ru2Dz 0Is6v17UaDAg1CIXjVcEuSY2C1omJ/L1APbt2whWM4DpbDDMT43+VVFRCcSfgcfYqAG2 AY0TRN+fjs3n8TTWRzdvJtvPk43z0l2Lyw3o3C/Om999OqUtdkT2cRRBxYmEjOqdJ33G v5hQ== X-Gm-Message-State: AC+VfDxaza7pqxHFLELXx2MzxdLBVS93cTSeZ1C4oxeHWjNVHQLXILoC hFms+i2CjpI8Z28S28bIU4rs X-Google-Smtp-Source: ACHHUZ7jUCBkk2GZ6mqGYAXM5FgcdG5o86hJ+mp4QPxJJVPhMwUe4RqjHcCfX7pPSzpKAYrptEqsBw== X-Received: by 2002:aca:220d:0:b0:39c:4563:d23c with SMTP id b13-20020aca220d000000b0039c4563d23cmr1033259oic.46.1687187080530; Mon, 19 Jun 2023 08:04:40 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:40 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 6/9] PCI: qcom: Do not advertise hotplug capability for IP v2.3.2 Date: Mon, 19 Jun 2023 20:34:05 +0530 Message-Id: <20230619150408.8468-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SoCs making use of Qcom PCIe controller IP v2.3.2 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 64b6a8c6a99d..9c8dfd224e6e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -616,6 +616,8 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) val |= EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); + qcom_pcie_clear_hpc(pcie->pci); + return 0; } From patchwork Mon Jun 19 15:04:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284687 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05161C001B3 for ; Mon, 19 Jun 2023 15:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229767AbjFSPGO (ORCPT ); Mon, 19 Jun 2023 11:06:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231417AbjFSPFU (ORCPT ); Mon, 19 Jun 2023 11:05:20 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F15F810E2 for ; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-25df7944f60so2775733a91.2 for ; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187084; x=1689779084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y/GAaoCJDXRESh8SzkgobGj/lkVGqp4sgMGqg7raF+w=; b=V9wXOuC0u6MhserqB+G6difAW8y4vzCRO18OAHl8pZnY48vHjoerHjTRsy+IVJqNcJ yRJh/pMYCSaxpRbcXAZFUsGHkqN5noXwbP/l5hlnO5r2kADG2CM0AQW5UtMji3Ppz+HK oTskUMwOIwrFfONX8n3SF9RSKCh3AOC19NJ12xPMVmOneKEpTzxmfyUAx+2pfBn5+AlB g1u2B4xEfnBiJo3IUVVaYLZuLmzh/0on5msGUMn1RuePtdM8wq4HTxrWZJupUxO/9MAd VhoNpR/Nu+8I11s4QzL5bA60jEWGz6kuipBuN5+njDVf+6Q8C3i7xutqeRTpI6rTbNPW wmAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187084; x=1689779084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y/GAaoCJDXRESh8SzkgobGj/lkVGqp4sgMGqg7raF+w=; b=IW4e5i/kIZrZMcS/eV6+X/ts54LBuCbDQk1N0G3wJxwQpRXfs/oQhKsdQiIUnO8//C QPqQATDF5z1jcPoA92/2BteFQOyDvajufS+1GZSMYHWj5dofKFX4fG8LqPxUBw73o/TI 5ZXbRbyND8p08hRUm33PGdanMubipgHhBzgtTlPNcSzVDYkzIlp/PxeuAn8F1WXkQCmj 5xjPTkBJQTlpTPNnXxd1T+YPVbvPNr9OVm2pcOh/V/PIzxrnbnZLWCQPuo3RF/o7s5ur 9icdLIvTER4wIh8iEfKC0q2NbbW9IYdRpgM7ryeengroylhO0ND5D/B2XK7BLSAVzqcV Rn3w== X-Gm-Message-State: AC+VfDxDSXtulLPJopW8jZwKRlsWgG2PXAfwOAlm7tO/ei8levvgrias x+dBmWemEETWLa+GHBBk8Lrf X-Google-Smtp-Source: ACHHUZ6Lgv+CRaeHvpmMJL0dObGrC9m7WE8tCgI+82+fGfhWauNyHfgIcYA5lk5e88NN9cFcN1NqLA== X-Received: by 2002:a17:90a:44:b0:260:a45e:751a with SMTP id 4-20020a17090a004400b00260a45e751amr1973170pjb.25.1687187084355; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:44 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 7/9] PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 Date: Mon, 19 Jun 2023 20:34:06 +0530 Message-Id: <20230619150408.8468-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The post init sequence of IP v2.4.0 is same as v2.3.2. So let's reuse the v2.3.2 sequence which now also disables hotplug capability of the controller as it is not at all supported on any SoCs making use of this IP. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 30 +------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9c8dfd224e6e..e6db9e551752 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -703,34 +703,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) return 0; } -static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) -{ - u32 val; - - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); - - /* change DBI base address */ - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); - - /* MAC PHY_POWERDOWN MUX DISABLE */ - val = readl(pcie->parf + PARF_SYS_CTRL); - val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; - writel(val, pcie->parf + PARF_SYS_CTRL); - - val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |= BYPASS; - writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - - val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |= EN; - writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - - return 0; -} - static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; @@ -1276,7 +1248,7 @@ static const struct qcom_pcie_ops ops_2_3_2 = { static const struct qcom_pcie_ops ops_2_4_0 = { .get_resources = qcom_pcie_get_resources_2_4_0, .init = qcom_pcie_init_2_4_0, - .post_init = qcom_pcie_post_init_2_4_0, + .post_init = qcom_pcie_post_init_2_3_2, .deinit = qcom_pcie_deinit_2_4_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; From patchwork Mon Jun 19 15:04:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284686 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DC48EB64DB for ; Mon, 19 Jun 2023 15:06:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229575AbjFSPGN (ORCPT ); Mon, 19 Jun 2023 11:06:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229767AbjFSPFX (ORCPT ); Mon, 19 Jun 2023 11:05:23 -0400 Received: from mail-oi1-x235.google.com (mail-oi1-x235.google.com [IPv6:2607:f8b0:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CED1A10E6 for ; Mon, 19 Jun 2023 08:04:48 -0700 (PDT) Received: by mail-oi1-x235.google.com with SMTP id 5614622812f47-39eab4bbe8aso2185408b6e.1 for ; Mon, 19 Jun 2023 08:04:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187088; x=1689779088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bkQkFXSrqR5MDMbqBcH7Nxin9P2rGGa9soJkqC/yxfY=; b=KL7WH9esTs7EFOrJOLlQDJsDcT/mfXXCsaCZDtwfYT+K05rl4Y0uOKqA/nDRWmM1Ay P0taJUuvOsjTeEXMez6C0nO7L1aJAoU0K3Fjc1lJVCl9ASZJCTyRjDx39SMKsSJgVjUI +nC498m4/o4uDShwgfyz9btY1mBsJhpn64wArvb82L+zGlP/PL09DQBvIavoKC1TNLcW MjtJF09kB4h01Yrj1fX0TNT3dROZOVwuDdNOAdKCMjF44SHOpvkte9RU97YN3M86+26U H5k9xq1Fmw/9RrXcAqB2TlMbGi9Ht0McM5hkCefS5MAV4huKmK5Oyu37azQTD3PDoCKG AzHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187088; x=1689779088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bkQkFXSrqR5MDMbqBcH7Nxin9P2rGGa9soJkqC/yxfY=; b=PkcaebYeHu4d04pCal8UAC7E5akPHx/lkF0VEZLdHTQssFh9HJWU+N3MFEuBYaOkoI C+8mou10evAVlSbA50wC2AuqxPNAqaj8zCVmFut0isUB1GcoEle+zUkuuamPfQWcv0hR k10shqOOcBh4jhP18xYqVb1sbVCGVOeKZsxSkpzr5TpBicT9vsM+RuCv/kuQqCgQllQo yAFN62d27PnuAqqlVTCgTPqQwInF1A2MgBNCT85YKsMQEBha+V3HOmjRwvbxMOH+1tyY rVYMTn6qVd67a9RxZML58PBagCEIXrmj6Eqzx5cHZdOnjmydezxsJ6gGRZWWENlidlo8 EQRA== X-Gm-Message-State: AC+VfDwQSfKU5BaBhHilIXftYPyPlWpN4qLrsNts4ZC7dGf9zXszHr1Y O3UKFrPj8v4C+IFWvJDMW1cp X-Google-Smtp-Source: ACHHUZ6jYi9B9kO4LbGSPIQT3nzgy6RoEcq55MHd7+0LtTnVlE8m58y0+GdIRnKABb/+X0ocxXlQNQ== X-Received: by 2002:a05:6808:301:b0:3a0:35c5:f79d with SMTP id i1-20020a056808030100b003a035c5f79dmr9833oie.36.1687187088151; Mon, 19 Jun 2023 08:04:48 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:47 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 8/9] PCI: qcom: Do not advertise hotplug capability for IP v1.0.0 Date: Mon, 19 Jun 2023 20:34:07 +0530 Message-Id: <20230619150408.8468-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SoCs making use of Qcom PCIe controller IP v1.0.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e6db9e551752..612266fb849a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -521,6 +521,8 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } + qcom_pcie_clear_hpc(pcie->pci); + return 0; } From patchwork Mon Jun 19 15:04:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284688 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 313F5C001DE for ; Mon, 19 Jun 2023 15:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229846AbjFSPGP (ORCPT ); Mon, 19 Jun 2023 11:06:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231583AbjFSPFZ (ORCPT ); Mon, 19 Jun 2023 11:05:25 -0400 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B37741700 for ; Mon, 19 Jun 2023 08:04:52 -0700 (PDT) Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-54f85f8b961so2735846a12.3 for ; Mon, 19 Jun 2023 08:04:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187092; x=1689779092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BAHgbKUGLDFGyzp+XWYZ2sseIunYBsYQIO/Xldf05CU=; b=XvdhBRHXtdzN60JPoHiXZGxe3Wk8p3gEVy+80P/yCIUnn5q/UjEz6wGlLUXO/Tcp/B p8G1lcxkxYlP5xBp89pAbZZsu5TTC+qOgOXZx0qANDXGrqsKG5jlWFQVYeQMgog4GiVg wdxkf03RP9va75x46RLsvNHYZv9BMqmZ8LQqPta7Z6Zq8i+eA+ZPRky6UY20MUYFYLkr AiJCUirnH8hMizZurVOfFD4mTj3SdBbkydnp+kTqBxXNiyFRO5NJsTl5mYeFNPA5V9gf rSIvT9+E06Kh8dESXnCMURATxRR6WFsSxEu8qtTmzg8ahZcvAundvWcd7CY1HHfnvrf3 CsnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187092; x=1689779092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BAHgbKUGLDFGyzp+XWYZ2sseIunYBsYQIO/Xldf05CU=; b=ZZbN12Ee4TnEfTrvzxpLvhIkVi+GTT2lQguDxXgvXpV/SvKI0NiglGZekzLD5j8yIx rXc/C7xpuupfvUlOlmEBPYvMDyJe+4V1sfxhBedxFMZHv89kuR/EiXW75zvmi6hTazyI 9K3JZE73v40nzjh/FmgNFpWEA8pA/KkK9jIu7PBwwqcrhkfp91BVUpKau1diUO9IISqn txHFCiynwrzidNwYm86xZgN6/MoGYiYMcEAEaXkroHZCX16MAHiwsyTG4nsYOpkAuG8b Uj4ZDjAIOT3MzOJOvkSRTlZpXXotTWcpEfA8WzoRpWPD4ZVPUg4QZ1sKVG/laRmp8ag1 YwYw== X-Gm-Message-State: AC+VfDwpmuZcoknflnJRiqXqiIg05w0bkdinxMO0jhVDPip+E6oDyKB5 r3yWVHWxAxtDs1NcbzgRZQ7a X-Google-Smtp-Source: ACHHUZ6mX5eL59bpG47z5VL6nwHLS8G/J72KGT7pv4yLTGgHpPgvjAqo6OiEFj63qn6HUCs8V7wiOA== X-Received: by 2002:a17:90a:df95:b0:25b:e216:bc15 with SMTP id p21-20020a17090adf9500b0025be216bc15mr10269006pjv.23.1687187092079; Mon, 19 Jun 2023 08:04:52 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:51 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 9/9] PCI: qcom: Do not advertise hotplug capability for IP v2.1.0 Date: Mon, 19 Jun 2023 20:34:08 +0530 Message-Id: <20230619150408.8468-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SoCs making use of Qcom PCIe controller IP v2.1.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 612266fb849a..7a87a47eb7ed 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -438,6 +438,8 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) writel(CFG_BRIDGE_SB_INIT, pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); + qcom_pcie_clear_hpc(pcie->pci); + return 0; }