From patchwork Tue Jun 20 10:34:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0201EB64DC for ; Tue, 20 Jun 2023 11:01:49 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551537.861147 (Exim 4.92) (envelope-from ) id 1qBZ71-00089U-Qt; Tue, 20 Jun 2023 11:01:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551537.861147; Tue, 20 Jun 2023 11:01:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ71-000883-JN; Tue, 20 Jun 2023 11:01:27 +0000 Received: by outflank-mailman (input) for mailman id 551537; Tue, 20 Jun 2023 10:35:21 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYhl-0004Ou-SB for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:21 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 27934a7d-0f56-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 12:35:20 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id BECA84EE074C; Tue, 20 Jun 2023 12:35:18 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 27934a7d-0f56-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 01/13] xen/x86: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:34:53 +0200 Message-Id: <5aa3a54af456b8faee681a1d737c361abe89296f.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin --- xen/arch/x86/acpi/cpufreq/powernow.c | 14 +++++++------- xen/include/acpi/cpufreq/processor_perf.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufreq/powernow.c index d4c7dcd5d9..8e0784b69c 100644 --- a/xen/arch/x86/acpi/cpufreq/powernow.c +++ b/xen/arch/x86/acpi/cpufreq/powernow.c @@ -32,14 +32,14 @@ #include #include -#define HW_PSTATE_MASK 0x00000007 -#define HW_PSTATE_VALID_MASK 0x80000000 -#define HW_PSTATE_MAX_MASK 0x000000f0 +#define HW_PSTATE_MASK 0x00000007U +#define HW_PSTATE_VALID_MASK 0x80000000U +#define HW_PSTATE_MAX_MASK 0x000000f0U #define HW_PSTATE_MAX_SHIFT 4 -#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */ -#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */ -#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */ -#define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* pstate current limit MSR */ +#define MSR_PSTATE_DEF_BASE 0xc0010064U /* base of Pstate MSRs */ +#define MSR_PSTATE_STATUS 0xc0010063U /* Pstate Status MSR */ +#define MSR_PSTATE_CTRL 0xc0010062U /* Pstate control MSR */ +#define MSR_PSTATE_CUR_LIMIT 0xc0010061U /* pstate current limit MSR */ #define MSR_HWCR_CPBDIS_MASK 0x02000000ULL #define ARCH_CPU_FLAG_RESUME 1 diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h index d8a1ba68a6..8b5a1b9bde 100644 --- a/xen/include/acpi/cpufreq/processor_perf.h +++ b/xen/include/acpi/cpufreq/processor_perf.h @@ -5,7 +5,7 @@ #include #include -#define XEN_PX_INIT 0x80000000 +#define XEN_PX_INIT 0x80000000U int powernow_cpufreq_init(void); unsigned int powernow_register_driver(void); From patchwork Tue Jun 20 10:34:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97328C001B3 for ; Tue, 20 Jun 2023 11:01:59 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551538.861151 (Exim 4.92) (envelope-from ) id 1qBZ72-0008HC-21; Tue, 20 Jun 2023 11:01:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551538.861151; Tue, 20 Jun 2023 11:01:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ71-0008GH-Td; Tue, 20 Jun 2023 11:01:27 +0000 Received: by outflank-mailman (input) for mailman id 551538; Tue, 20 Jun 2023 10:35:23 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYhn-0004Ou-Dm for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:23 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2864a1e3-0f56-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 12:35:21 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 33C7A4EE0754; Tue, 20 Jun 2023 12:35:20 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2864a1e3-0f56-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 02/13] AMD/IOMMU: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:34:54 +0200 Message-Id: <21337a20c5c8d66dff552c2f09054ea82b253dd6.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin Acked-by: Stefano Stabellini --- xen/drivers/passthrough/amd/iommu-defs.h | 122 +++++++++++------------ 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/xen/drivers/passthrough/amd/iommu-defs.h b/xen/drivers/passthrough/amd/iommu-defs.h index 35de548e3a..c145248f9a 100644 --- a/xen/drivers/passthrough/amd/iommu-defs.h +++ b/xen/drivers/passthrough/amd/iommu-defs.h @@ -38,49 +38,49 @@ ((uint64_t)(offset) << (12 + (PTE_PER_TABLE_SHIFT * ((level) - 1)))) /* IOMMU Capability */ -#define PCI_CAP_ID_MASK 0x000000FF +#define PCI_CAP_ID_MASK 0x000000FFU #define PCI_CAP_ID_SHIFT 0 -#define PCI_CAP_NEXT_PTR_MASK 0x0000FF00 +#define PCI_CAP_NEXT_PTR_MASK 0x0000FF00U #define PCI_CAP_NEXT_PTR_SHIFT 8 -#define PCI_CAP_TYPE_MASK 0x00070000 +#define PCI_CAP_TYPE_MASK 0x00070000U #define PCI_CAP_TYPE_SHIFT 16 -#define PCI_CAP_REV_MASK 0x00F80000 +#define PCI_CAP_REV_MASK 0x00F80000U #define PCI_CAP_REV_SHIFT 19 -#define PCI_CAP_IOTLB_MASK 0x01000000 +#define PCI_CAP_IOTLB_MASK 0x01000000U #define PCI_CAP_IOTLB_SHIFT 24 -#define PCI_CAP_HT_TUNNEL_MASK 0x02000000 +#define PCI_CAP_HT_TUNNEL_MASK 0x02000000U #define PCI_CAP_HT_TUNNEL_SHIFT 25 -#define PCI_CAP_NP_CACHE_MASK 0x04000000 +#define PCI_CAP_NP_CACHE_MASK 0x04000000U #define PCI_CAP_NP_CACHE_SHIFT 26 #define PCI_CAP_EFRSUP_SHIFT 27 -#define PCI_CAP_RESET_MASK 0x80000000 +#define PCI_CAP_RESET_MASK 0x80000000U #define PCI_CAP_RESET_SHIFT 31 #define PCI_CAP_TYPE_IOMMU 0x3 #define PCI_CAP_MMIO_BAR_LOW_OFFSET 0x04 #define PCI_CAP_MMIO_BAR_HIGH_OFFSET 0x08 -#define PCI_CAP_MMIO_BAR_LOW_MASK 0xFFFFC000 +#define PCI_CAP_MMIO_BAR_LOW_MASK 0xFFFFC000U #define IOMMU_MMIO_REGION_LENGTH 0x4000 #define PCI_CAP_RANGE_OFFSET 0x0C -#define PCI_CAP_BUS_NUMBER_MASK 0x0000FF00 +#define PCI_CAP_BUS_NUMBER_MASK 0x0000FF00U #define PCI_CAP_BUS_NUMBER_SHIFT 8 -#define PCI_CAP_FIRST_DEVICE_MASK 0x00FF0000 +#define PCI_CAP_FIRST_DEVICE_MASK 0x00FF0000U #define PCI_CAP_FIRST_DEVICE_SHIFT 16 -#define PCI_CAP_LAST_DEVICE_MASK 0xFF000000 +#define PCI_CAP_LAST_DEVICE_MASK 0xFF000000U #define PCI_CAP_LAST_DEVICE_SHIFT 24 -#define PCI_CAP_UNIT_ID_MASK 0x0000001F +#define PCI_CAP_UNIT_ID_MASK 0x0000001FU #define PCI_CAP_UNIT_ID_SHIFT 0 #define PCI_CAP_MISC_INFO_OFFSET 0x10 -#define PCI_CAP_MSI_NUMBER_MASK 0x0000001F +#define PCI_CAP_MSI_NUMBER_MASK 0x0000001FU #define PCI_CAP_MSI_NUMBER_SHIFT 0 /* Device Table */ #define IOMMU_DEV_TABLE_BASE_LOW_OFFSET 0x00 #define IOMMU_DEV_TABLE_BASE_HIGH_OFFSET 0x04 -#define IOMMU_DEV_TABLE_SIZE_MASK 0x000001FF +#define IOMMU_DEV_TABLE_SIZE_MASK 0x000001FFU #define IOMMU_DEV_TABLE_SIZE_SHIFT 0 #define IOMMU_DEV_TABLE_ENTRIES_PER_BUS 256 @@ -159,13 +159,13 @@ struct amd_iommu_dte { #define IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET 0x0C #define IOMMU_CMD_BUFFER_HEAD_OFFSET 0x2000 #define IOMMU_CMD_BUFFER_TAIL_OFFSET 0x2008 -#define IOMMU_CMD_BUFFER_LENGTH_MASK 0x0F000000 +#define IOMMU_CMD_BUFFER_LENGTH_MASK 0x0F000000U #define IOMMU_CMD_BUFFER_LENGTH_SHIFT 24 #define IOMMU_CMD_BUFFER_ENTRY_ORDER 4 #define IOMMU_CMD_BUFFER_MAX_ENTRIES (1u << 15) -#define IOMMU_CMD_OPCODE_MASK 0xF0000000 +#define IOMMU_CMD_OPCODE_MASK 0xF0000000U #define IOMMU_CMD_OPCODE_SHIFT 28 #define IOMMU_CMD_COMPLETION_WAIT 0x1 #define IOMMU_CMD_INVALIDATE_DEVTAB_ENTRY 0x2 @@ -178,50 +178,50 @@ struct amd_iommu_dte { /* COMPLETION_WAIT command */ #define IOMMU_COMP_WAIT_DATA_BUFFER_SIZE 8 #define IOMMU_COMP_WAIT_DATA_BUFFER_ALIGNMENT 8 -#define IOMMU_COMP_WAIT_S_FLAG_MASK 0x00000001 -#define IOMMU_COMP_WAIT_I_FLAG_MASK 0x00000002 -#define IOMMU_COMP_WAIT_F_FLAG_MASK 0x00000004 -#define IOMMU_COMP_WAIT_ADDR_LOW_MASK 0xFFFFFFF8 +#define IOMMU_COMP_WAIT_S_FLAG_MASK 0x00000001U +#define IOMMU_COMP_WAIT_I_FLAG_MASK 0x00000002U +#define IOMMU_COMP_WAIT_F_FLAG_MASK 0x00000004U +#define IOMMU_COMP_WAIT_ADDR_LOW_MASK 0xFFFFFFF8U #define IOMMU_COMP_WAIT_ADDR_LOW_SHIFT 3 -#define IOMMU_COMP_WAIT_ADDR_HIGH_MASK 0x000FFFFF +#define IOMMU_COMP_WAIT_ADDR_HIGH_MASK 0x000FFFFFU #define IOMMU_COMP_WAIT_ADDR_HIGH_SHIFT 0 /* INVALIDATE_IOMMU_PAGES command */ -#define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_MASK 0x0000FFFF +#define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_MASK 0x0000FFFFU #define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_SHIFT 0 -#define IOMMU_INV_IOMMU_PAGES_S_FLAG_MASK 0x00000001 +#define IOMMU_INV_IOMMU_PAGES_S_FLAG_MASK 0x00000001U #define IOMMU_INV_IOMMU_PAGES_S_FLAG_SHIFT 0 -#define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_MASK 0x00000002 +#define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_MASK 0x00000002U #define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_SHIFT 1 -#define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_MASK 0xFFFFF000 +#define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_MASK 0xFFFFF000U #define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_SHIFT 12 -#define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_MASK 0xFFFFFFFF +#define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_MASK 0xFFFFFFFFU #define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_SHIFT 0 /* INVALIDATE_DEVTAB_ENTRY command */ -#define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_SHIFT 0 /* INVALIDATE_INTERRUPT_TABLE command */ -#define IOMMU_INV_INT_TABLE_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_INV_INT_TABLE_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_INV_INT_TABLE_DEVICE_ID_SHIFT 0 /* INVALIDATE_IOTLB_PAGES command */ -#define IOMMU_INV_IOTLB_PAGES_MAXPEND_MASK 0xff000000 +#define IOMMU_INV_IOTLB_PAGES_MAXPEND_MASK 0xff000000U #define IOMMU_INV_IOTLB_PAGES_MAXPEND_SHIFT 24 -#define IOMMU_INV_IOTLB_PAGES_PASID1_MASK 0x00ff0000 +#define IOMMU_INV_IOTLB_PAGES_PASID1_MASK 0x00ff0000U #define IOMMU_INV_IOTLB_PAGES_PASID1_SHIFT 16 -#define IOMMU_INV_IOTLB_PAGES_PASID2_MASK 0x0fff0000 +#define IOMMU_INV_IOTLB_PAGES_PASID2_MASK 0x0fff0000U #define IOMMU_INV_IOTLB_PAGES_PASID2_SHIFT 16 -#define IOMMU_INV_IOTLB_PAGES_QUEUEID_MASK 0x0000ffff +#define IOMMU_INV_IOTLB_PAGES_QUEUEID_MASK 0x0000ffffU #define IOMMU_INV_IOTLB_PAGES_QUEUEID_SHIFT 0 -#define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_SHIFT 0 -#define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_MASK 0xFFFFF000 +#define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_MASK 0xFFFFF000U #define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_SHIFT 12 -#define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_MASK 0xFFFFFFFF +#define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_MASK 0xFFFFFFFFU #define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_SHIFT 0 -#define IOMMU_INV_IOTLB_PAGES_S_FLAG_MASK 0x00000001 +#define IOMMU_INV_IOTLB_PAGES_S_FLAG_MASK 0x00000001U #define IOMMU_INV_IOTLB_PAGES_S_FLAG_SHIFT 0 /* Event Log */ @@ -229,18 +229,18 @@ struct amd_iommu_dte { #define IOMMU_EVENT_LOG_BASE_HIGH_OFFSET 0x14 #define IOMMU_EVENT_LOG_HEAD_OFFSET 0x2010 #define IOMMU_EVENT_LOG_TAIL_OFFSET 0x2018 -#define IOMMU_EVENT_LOG_LENGTH_MASK 0x0F000000 +#define IOMMU_EVENT_LOG_LENGTH_MASK 0x0F000000U #define IOMMU_EVENT_LOG_LENGTH_SHIFT 24 -#define IOMMU_EVENT_LOG_HEAD_MASK 0x0007FFF0 +#define IOMMU_EVENT_LOG_HEAD_MASK 0x0007FFF0U #define IOMMU_EVENT_LOG_HEAD_SHIFT 4 -#define IOMMU_EVENT_LOG_TAIL_MASK 0x0007FFF0 +#define IOMMU_EVENT_LOG_TAIL_MASK 0x0007FFF0U #define IOMMU_EVENT_LOG_TAIL_SHIFT 4 #define IOMMU_EVENT_LOG_ENTRY_SIZE 16 #define IOMMU_EVENT_LOG_POWER_OF2_ENTRIES_PER_PAGE 8 #define IOMMU_EVENT_LOG_U32_PER_ENTRY (IOMMU_EVENT_LOG_ENTRY_SIZE / 4) -#define IOMMU_EVENT_CODE_MASK 0xF0000000 +#define IOMMU_EVENT_CODE_MASK 0xF0000000U #define IOMMU_EVENT_CODE_SHIFT 28 #define IOMMU_EVENT_ILLEGAL_DEV_TABLE_ENTRY 0x1 #define IOMMU_EVENT_IO_PAGE_FAULT 0x2 @@ -251,12 +251,12 @@ struct amd_iommu_dte { #define IOMMU_EVENT_IOTLB_INV_TIMEOUT 0x7 #define IOMMU_EVENT_INVALID_DEV_REQUEST 0x8 -#define IOMMU_EVENT_DOMAIN_ID_MASK 0x0000FFFF +#define IOMMU_EVENT_DOMAIN_ID_MASK 0x0000FFFFU #define IOMMU_EVENT_DOMAIN_ID_SHIFT 0 -#define IOMMU_EVENT_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_EVENT_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_EVENT_DEVICE_ID_SHIFT 0 #define IOMMU_EVENT_FLAGS_SHIFT 16 -#define IOMMU_EVENT_FLAGS_MASK 0x0FFF0000 +#define IOMMU_EVENT_FLAGS_MASK 0x0FFF0000U /* PPR Log */ #define IOMMU_PPR_LOG_ENTRY_SIZE 16 @@ -265,21 +265,21 @@ struct amd_iommu_dte { #define IOMMU_PPR_LOG_BASE_LOW_OFFSET 0x0038 #define IOMMU_PPR_LOG_BASE_HIGH_OFFSET 0x003C -#define IOMMU_PPR_LOG_BASE_LOW_MASK 0xFFFFF000 +#define IOMMU_PPR_LOG_BASE_LOW_MASK 0xFFFFF000U #define IOMMU_PPR_LOG_BASE_LOW_SHIFT 12 -#define IOMMU_PPR_LOG_BASE_HIGH_MASK 0x000FFFFF +#define IOMMU_PPR_LOG_BASE_HIGH_MASK 0x000FFFFFU #define IOMMU_PPR_LOG_BASE_HIGH_SHIFT 0 -#define IOMMU_PPR_LOG_LENGTH_MASK 0x0F000000 +#define IOMMU_PPR_LOG_LENGTH_MASK 0x0F000000U #define IOMMU_PPR_LOG_LENGTH_SHIFT 24 -#define IOMMU_PPR_LOG_HEAD_MASK 0x0007FFF0 +#define IOMMU_PPR_LOG_HEAD_MASK 0x0007FFF0U #define IOMMU_PPR_LOG_HEAD_SHIFT 4 -#define IOMMU_PPR_LOG_TAIL_MASK 0x0007FFF0 +#define IOMMU_PPR_LOG_TAIL_MASK 0x0007FFF0U #define IOMMU_PPR_LOG_TAIL_SHIFT 4 #define IOMMU_PPR_LOG_HEAD_OFFSET 0x2030 #define IOMMU_PPR_LOG_TAIL_OFFSET 0x2038 -#define IOMMU_PPR_LOG_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_PPR_LOG_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_PPR_LOG_DEVICE_ID_SHIFT 0 -#define IOMMU_PPR_LOG_CODE_MASK 0xF0000000 +#define IOMMU_PPR_LOG_CODE_MASK 0xF0000000U #define IOMMU_PPR_LOG_CODE_SHIFT 28 #define IOMMU_LOG_ENTRY_TIMEOUT 1000 @@ -342,17 +342,17 @@ union amd_iommu_control { #define IOMMU_EXCLUSION_BASE_HIGH_OFFSET 0x24 #define IOMMU_EXCLUSION_LIMIT_LOW_OFFSET 0x28 #define IOMMU_EXCLUSION_LIMIT_HIGH_OFFSET 0x2C -#define IOMMU_EXCLUSION_BASE_LOW_MASK 0xFFFFF000 +#define IOMMU_EXCLUSION_BASE_LOW_MASK 0xFFFFF000U #define IOMMU_EXCLUSION_BASE_LOW_SHIFT 12 -#define IOMMU_EXCLUSION_BASE_HIGH_MASK 0xFFFFFFFF +#define IOMMU_EXCLUSION_BASE_HIGH_MASK 0xFFFFFFFFU #define IOMMU_EXCLUSION_BASE_HIGH_SHIFT 0 -#define IOMMU_EXCLUSION_RANGE_ENABLE_MASK 0x00000001 +#define IOMMU_EXCLUSION_RANGE_ENABLE_MASK 0x00000001U #define IOMMU_EXCLUSION_RANGE_ENABLE_SHIFT 0 -#define IOMMU_EXCLUSION_ALLOW_ALL_MASK 0x00000002 +#define IOMMU_EXCLUSION_ALLOW_ALL_MASK 0x00000002U #define IOMMU_EXCLUSION_ALLOW_ALL_SHIFT 1 -#define IOMMU_EXCLUSION_LIMIT_LOW_MASK 0xFFFFF000 +#define IOMMU_EXCLUSION_LIMIT_LOW_MASK 0xFFFFF000U #define IOMMU_EXCLUSION_LIMIT_LOW_SHIFT 12 -#define IOMMU_EXCLUSION_LIMIT_HIGH_MASK 0xFFFFFFFF +#define IOMMU_EXCLUSION_LIMIT_HIGH_MASK 0xFFFFFFFFU #define IOMMU_EXCLUSION_LIMIT_HIGH_SHIFT 0 /* Extended Feature Register */ @@ -476,14 +476,14 @@ union amd_iommu_pte { #define INV_IOMMU_ALL_PAGES_ADDRESS ((1ULL << 63) - 1) -#define IOMMU_RING_BUFFER_PTR_MASK 0x0007FFF0 +#define IOMMU_RING_BUFFER_PTR_MASK 0x0007FFF0U -#define IOMMU_CMD_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_CMD_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_CMD_DEVICE_ID_SHIFT 0 -#define IOMMU_REG_BASE_ADDR_LOW_MASK 0xFFFFF000 +#define IOMMU_REG_BASE_ADDR_LOW_MASK 0xFFFFF000U #define IOMMU_REG_BASE_ADDR_LOW_SHIFT 12 -#define IOMMU_REG_BASE_ADDR_HIGH_MASK 0x000FFFFF +#define IOMMU_REG_BASE_ADDR_HIGH_MASK 0x000FFFFFU #define IOMMU_REG_BASE_ADDR_HIGH_SHIFT 0 #endif /* AMD_IOMMU_DEFS_H */ From patchwork Tue Jun 20 10:34:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44FB6C0015E for ; Tue, 20 Jun 2023 11:01:50 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551540.861158 (Exim 4.92) (envelope-from ) id 1qBZ72-0008Q6-Ci; Tue, 20 Jun 2023 11:01:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551540.861158; Tue, 20 Jun 2023 11:01:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ72-0008OD-7M; Tue, 20 Jun 2023 11:01:28 +0000 Received: by outflank-mailman (input) for mailman id 551540; Tue, 20 Jun 2023 10:35:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYho-0004Pq-5h for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:24 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 294fe34c-0f56-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 12:35:23 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 8DF784EE0755; Tue, 20 Jun 2023 12:35:21 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 294fe34c-0f56-11ee-b234-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 03/13] xen/x86: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:34:55 +0200 Message-Id: <397206cfac500d171be31dcd3503d9f61e531a97.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- xen/arch/x86/hvm/svm/asid.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/hvm/svm/asid.c b/xen/arch/x86/hvm/svm/asid.c index 09f8c23fd9..56306d1a16 100644 --- a/xen/arch/x86/hvm/svm/asid.c +++ b/xen/arch/x86/hvm/svm/asid.c @@ -16,7 +16,7 @@ void svm_asid_init(const struct cpuinfo_x86 *c) /* Check for erratum #170, and leave ASIDs disabled if it's present. */ if ( !cpu_has_amd_erratum(c, AMD_ERRATUM_170) ) - nasids = cpuid_ebx(0x8000000A); + nasids = cpuid_ebx(0x8000000AU); hvm_asid_init(nasids); } diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 59a6e88dff..56cb2f61bb 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -269,9 +269,9 @@ svm_msrbit(unsigned long *msr_bitmap, uint32_t msr) */ if ( msr <= 0x1fff ) msr_bit = msr_bitmap + 0x0000 / BYTES_PER_LONG; - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) msr_bit = msr_bitmap + 0x0800 / BYTES_PER_LONG; - else if ( (msr >= 0xc0010000) && (msr <= 0xc0011fff) ) + else if ( (msr >= 0xc0010000U) && (msr <= 0xc0011fffU) ) msr_bit = msr_bitmap + 0x1000 / BYTES_PER_LONG; return msr_bit; @@ -2539,8 +2539,8 @@ const struct hvm_function_table * __init start_svm(void) setup_vmcb_dump(); - if ( boot_cpu_data.extended_cpuid_level >= 0x8000000a ) - svm_feature_flags = cpuid_edx(0x8000000a); + if ( boot_cpu_data.extended_cpuid_level >= 0x8000000aU ) + svm_feature_flags = cpuid_edx(0x8000000aU); printk("SVM: Supported advanced features:\n"); From patchwork Tue Jun 20 10:34:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09756EB64DD for ; Tue, 20 Jun 2023 11:01:59 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551543.861165 (Exim 4.92) (envelope-from ) id 1qBZ72-0008VY-Ol; Tue, 20 Jun 2023 11:01:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551543.861165; Tue, 20 Jun 2023 11:01:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ72-0008TF-HK; Tue, 20 Jun 2023 11:01:28 +0000 Received: by outflank-mailman (input) for mailman id 551543; Tue, 20 Jun 2023 10:35:25 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYhp-0004Pq-Uc for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:25 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2a678d70-0f56-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 12:35:25 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 364074EE0756; Tue, 20 Jun 2023 12:35:23 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2a678d70-0f56-11ee-b234-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 04/13] xen/arm: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:34:56 +0200 Message-Id: <4d27e872f889f4080af42cc1ff2591ac56834e21.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin --- xen/arch/arm/domain_build.c | 2 +- xen/arch/arm/efi/efi-boot.h | 2 +- xen/arch/arm/gic-v2.c | 6 +++--- xen/arch/arm/include/asm/arm64/brk.h | 2 +- xen/arch/arm/include/asm/arm64/efibind.h | 10 +++++----- xen/arch/arm/include/asm/arm64/insn.h | 16 ++++++++-------- xen/arch/arm/include/asm/vreg.h | 2 +- xen/arch/arm/kernel.c | 2 +- xen/arch/arm/traps.c | 4 ++-- xen/arch/arm/vgic-v2.c | 2 +- xen/include/public/arch-arm/smccc.h | 8 ++++---- 11 files changed, 28 insertions(+), 28 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index d0d6be922d..78261352a6 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -3752,7 +3752,7 @@ static int __init construct_domain(struct domain *d, struct kernel_info *kinfo) *... */ regs->r0 = 0; /* SBZ */ - regs->r1 = 0xffffffff; /* We use DTB therefore no machine id */ + regs->r1 = 0xffffffffU; /* We use DTB therefore no machine id */ regs->r2 = kinfo->dtb_paddr; } #ifdef CONFIG_ARM_64 diff --git a/xen/arch/arm/efi/efi-boot.h b/xen/arch/arm/efi/efi-boot.h index bb64925d70..585332647d 100644 --- a/xen/arch/arm/efi/efi-boot.h +++ b/xen/arch/arm/efi/efi-boot.h @@ -46,7 +46,7 @@ static int get_module_file_index(const char *name, unsigned int name_len); static void PrintMessage(const CHAR16 *s); #define DEVICE_TREE_GUID \ -{0xb1b621d5, 0xf19c, 0x41a5, {0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0}} +{0xb1b621d5U, 0xf19cU, 0x41a5U, {0x83U, 0x0bU, 0xd9U, 0x15U, 0x2cU, 0x69U, 0xaaU, 0xe0U}} static struct file __initdata dtbfile; static void __initdata *fdt; diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 6476ff4230..191c89b01b 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -386,9 +386,9 @@ static void gicv2_cpu_init(void) /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so * even though they are controlled with GICD registers, they must * be set up here with the other per-cpu state. */ - writel_gicd(0xffffffff, GICD_ICACTIVER); /* Diactivate PPIs and SGIs */ - writel_gicd(0xffff0000, GICD_ICENABLER); /* Disable all PPI */ - writel_gicd(0x0000ffff, GICD_ISENABLER); /* Enable all SGI */ + writel_gicd(0xffffffffU, GICD_ICACTIVER); /* Diactivate PPIs and SGIs */ + writel_gicd(0xffff0000U, GICD_ICENABLER); /* Disable all PPI */ + writel_gicd(0x0000ffffU, GICD_ISENABLER); /* Enable all SGI */ /* Set SGI priorities */ for ( i = 0; i < 16; i += 4 ) diff --git a/xen/arch/arm/include/asm/arm64/brk.h b/xen/arch/arm/include/asm/arm64/brk.h index 04442c4b9f..3af153a053 100644 --- a/xen/arch/arm/include/asm/arm64/brk.h +++ b/xen/arch/arm/include/asm/arm64/brk.h @@ -21,7 +21,7 @@ * BRK instruction encoding * The #imm16 value should be placed at bits[20:5] within BRK ins */ -#define AARCH64_BREAK_MON 0xd4200000 +#define AARCH64_BREAK_MON 0xd4200000U /* * BRK instruction for provoking a fault on purpose diff --git a/xen/arch/arm/include/asm/arm64/efibind.h b/xen/arch/arm/include/asm/arm64/efibind.h index 8b43bb8495..0e890b666d 100644 --- a/xen/arch/arm/include/asm/arm64/efibind.h +++ b/xen/arch/arm/include/asm/arm64/efibind.h @@ -22,12 +22,12 @@ Revision History #pragma pack() #endif -#define EFIERR(a) (0x8000000000000000 | a) -#define EFI_ERROR_MASK 0x8000000000000000 -#define EFIERR_OEM(a) (0xc000000000000000 | a) +#define EFIERR(a) (0x8000000000000000U | a) +#define EFI_ERROR_MASK 0x8000000000000000U +#define EFIERR_OEM(a) (0xc000000000000000U | a) -#define BAD_POINTER 0xFBFBFBFBFBFBFBFB -#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFF +#define BAD_POINTER 0xFBFBFBFBFBFBFBFBU +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFU #define EFI_STUB_ERROR MAX_ADDRESS diff --git a/xen/arch/arm/include/asm/arm64/insn.h b/xen/arch/arm/include/asm/arm64/insn.h index 4e0d364d41..b522b07bf5 100644 --- a/xen/arch/arm/include/asm/arm64/insn.h +++ b/xen/arch/arm/include/asm/arm64/insn.h @@ -60,14 +60,14 @@ static always_inline bool aarch64_insn_is_##abbr(u32 code) \ static always_inline u32 aarch64_insn_get_##abbr##_value(void) \ { return (val); } -__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) -__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) -__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) -__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000) -__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000) -__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000) -__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000) -__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) +__AARCH64_INSN_FUNCS(b, 0xFC000000U, 0x14000000) +__AARCH64_INSN_FUNCS(bl, 0xFC000000U, 0x94000000U) +__AARCH64_INSN_FUNCS(cbz, 0x7F000000U, 0x34000000) +__AARCH64_INSN_FUNCS(cbnz, 0x7F000000U, 0x35000000) +__AARCH64_INSN_FUNCS(tbz, 0x7F000000U, 0x36000000) +__AARCH64_INSN_FUNCS(tbnz, 0x7F000000U, 0x37000000) +__AARCH64_INSN_FUNCS(bcond, 0xFF000010U, 0x54000000) +__AARCH64_INSN_FUNCS(hint, 0xFFFFF01FU, 0xD503201FU) bool aarch64_insn_is_branch_imm(u32 insn); diff --git a/xen/arch/arm/include/asm/vreg.h b/xen/arch/arm/include/asm/vreg.h index bf945eebbd..387ce76e7e 100644 --- a/xen/arch/arm/include/asm/vreg.h +++ b/xen/arch/arm/include/asm/vreg.h @@ -56,7 +56,7 @@ static inline bool vreg_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr, if ( ret && cp64.read ) { - set_user_reg(regs, cp64.reg1, x & 0xffffffff); + set_user_reg(regs, cp64.reg1, x & 0xffffffffU); set_user_reg(regs, cp64.reg2, x >> 32); } diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index ca5318515e..508c54824d 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -39,7 +39,7 @@ struct minimal_dtb_header { /* There are other fields but we don't use them yet. */ }; -#define DTB_MAGIC 0xd00dfeed +#define DTB_MAGIC 0xd00dfeedU /** * copy_from_paddr - copy data from a physical address diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ef5c6a8195..def92fafae 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -398,7 +398,7 @@ static vaddr_t exception_handler32(vaddr_t offset) register_t sctlr = READ_SYSREG(SCTLR_EL1); if ( sctlr & SCTLR_A32_EL1_V ) - return 0xffff0000 + offset; + return 0xffff0000U + offset; else /* always have security exceptions */ return READ_SYSREG(VBAR_EL1) + offset; } @@ -809,7 +809,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, #ifdef CONFIG_ARM_64 (uint32_t)(ctxt->far >> 32), ctxt->ifsr32_el2, - (uint32_t)(ctxt->far & 0xffffffff), + (uint32_t)(ctxt->far & 0xffffffffU), ctxt->esr_el1 #else ctxt->ifar, ctxt->ifsr, ctxt->dfar, ctxt->dfsr diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 0b083c33e6..35363fee09 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -306,7 +306,7 @@ static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info, case VREG32(GICD_SGIR): if ( dabt.size != DABT_WORD ) goto bad_width; /* Write only -- read unknown */ - *r = 0xdeadbeef; + *r = 0xdeadbeefU; return 1; case VRANGE32(0xF04, 0xF0C): diff --git a/xen/include/public/arch-arm/smccc.h b/xen/include/public/arch-arm/smccc.h index 802d800aad..8553f2f39e 100644 --- a/xen/include/public/arch-arm/smccc.h +++ b/xen/include/public/arch-arm/smccc.h @@ -26,16 +26,16 @@ #define XEN_SMCCC_MINOR_REVISION 1 /* Hypervisor Service UID. Randomly generated with uuidgen. */ -#define XEN_SMCCC_UID XEN_DEFINE_UUID(0xa71812dc, 0xc698, 0x4369, 0x9acf, \ - 0x79, 0xd1, 0x8d, 0xde, 0xe6, 0x67) +#define XEN_SMCCC_UID XEN_DEFINE_UUID(0xa71812dcU, 0xc698U, 0x4369U, 0x9acfU, \ + 0x79U, 0xd1U, 0x8dU, 0xdeU, 0xe6U, 0x67U) /* Standard Service Service Call version. */ #define SSSC_SMCCC_MAJOR_REVISION 0 #define SSSC_SMCCC_MINOR_REVISION 1 /* Standard Service Call UID. Randomly generated with uuidgen. */ -#define SSSC_SMCCC_UID XEN_DEFINE_UUID(0xf863386f, 0x4b39, 0x4cbd, 0x9220,\ - 0xce, 0x16, 0x41, 0xe5, 0x9f, 0x6f) +#define SSSC_SMCCC_UID XEN_DEFINE_UUID(0xf863386fU, 0x4b39U, 0x4cbdU, 0x9220U,\ + 0xceU, 0x16U, 0x41U, 0xe5U, 0x9fU, 0x6fU) #endif /* __XEN_PUBLIC_ARCH_ARM_SMCCC_H__ */ From patchwork Tue Jun 20 10:34:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0FB5EB64DB for ; Tue, 20 Jun 2023 11:01:50 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551544.861171 (Exim 4.92) (envelope-from ) id 1qBZ73-0000G7-7H; Tue, 20 Jun 2023 11:01:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551544.861171; Tue, 20 Jun 2023 11:01:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ73-0000E6-0v; Tue, 20 Jun 2023 11:01:29 +0000 Received: by outflank-mailman (input) for mailman id 551544; Tue, 20 Jun 2023 10:35:27 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYhr-0004Pq-I4 for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:27 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2b8d6657-0f56-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 12:35:26 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 079F94EE0757; Tue, 20 Jun 2023 12:35:24 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2b8d6657-0f56-11ee-b234-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Julien Grall , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 05/13] xen/common: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:34:57 +0200 Message-Id: <8aff4bc56b29372345e828462766d803b8c9b710.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. Signed-off-by: Simone Ballarin --- xen/common/device_tree.c | 4 ++-- xen/include/xen/libfdt/fdt.h | 2 +- xen/include/xen/libfdt/libfdt.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c index 8da1052911..0677193ab3 100644 --- a/xen/common/device_tree.c +++ b/xen/common/device_tree.c @@ -2115,7 +2115,7 @@ static void __init __unflatten_device_tree(const void *fdt, /* Allocate memory for the expanded device tree */ mem = (unsigned long)_xmalloc (size + 4, __alignof__(struct dt_device_node)); - ((__be32 *)mem)[size / 4] = cpu_to_be32(0xdeadbeef); + ((__be32 *)mem)[size / 4] = cpu_to_be32(0xdeadbeefU); dt_dprintk(" unflattening %lx...\n", mem); @@ -2125,7 +2125,7 @@ static void __init __unflatten_device_tree(const void *fdt, if ( be32_to_cpup((__be32 *)start) != FDT_END ) printk(XENLOG_WARNING "Weird tag at end of tree: %08x\n", *((u32 *)start)); - if ( be32_to_cpu(((__be32 *)mem)[size / 4]) != 0xdeadbeef ) + if ( be32_to_cpu(((__be32 *)mem)[size / 4]) != 0xdeadbeefU ) printk(XENLOG_WARNING "End of tree marker overwritten: %08x\n", be32_to_cpu(((__be32 *)mem)[size / 4])); *allnextp = NULL; diff --git a/xen/include/xen/libfdt/fdt.h b/xen/include/xen/libfdt/fdt.h index f2e68807f2..7c99d838e8 100644 --- a/xen/include/xen/libfdt/fdt.h +++ b/xen/include/xen/libfdt/fdt.h @@ -47,7 +47,7 @@ struct fdt_property { #endif /* !__ASSEMBLY */ -#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_MAGIC 0xd00dfeedU /* 4: version, 4: total size */ #define FDT_TAGSIZE sizeof(fdt32_t) #define FDT_BEGIN_NODE 0x1 /* Start node: full name */ diff --git a/xen/include/xen/libfdt/libfdt.h b/xen/include/xen/libfdt/libfdt.h index c71689e2be..dd6b649602 100644 --- a/xen/include/xen/libfdt/libfdt.h +++ b/xen/include/xen/libfdt/libfdt.h @@ -109,7 +109,7 @@ extern "C" { #define FDT_ERR_MAX 19 /* constants */ -#define FDT_MAX_PHANDLE 0xfffffffe +#define FDT_MAX_PHANDLE 0xfffffffeU /* Valid values for phandles range from 1 to 2^32-2. */ /**********************************************************************/ From patchwork Tue Jun 20 10:34:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6ADE7EB64D8 for ; Tue, 20 Jun 2023 11:01:59 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551547.861180 (Exim 4.92) (envelope-from ) id 1qBZ73-0000SC-NU; Tue, 20 Jun 2023 11:01:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551547.861180; Tue, 20 Jun 2023 11:01:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ73-0000PD-HZ; Tue, 20 Jun 2023 11:01:29 +0000 Received: by outflank-mailman (input) for mailman id 551547; Tue, 20 Jun 2023 10:35:29 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYht-0004Pq-EJ for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:29 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2c7ac34e-0f56-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 12:35:28 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id DC8C24EE0753; Tue, 20 Jun 2023 12:35:26 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2c7ac34e-0f56-11ee-b234-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 06/13] xen/efi: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:34:58 +0200 Message-Id: <019b934cb1e96affd7429c1632fbfe3faacc663e.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin --- xen/arch/x86/include/asm/x86_64/efibind.h | 10 +++++----- xen/common/efi/boot.c | 8 ++++---- xen/common/efi/runtime.c | 2 +- xen/include/efi/efiapi.h | 10 +++++----- xen/include/efi/efidef.h | 2 +- xen/include/efi/efiprot.h | 22 +++++++++++----------- 6 files changed, 27 insertions(+), 27 deletions(-) diff --git a/xen/arch/x86/include/asm/x86_64/efibind.h b/xen/arch/x86/include/asm/x86_64/efibind.h index e23cd16cb6..773ef9b063 100644 --- a/xen/arch/x86/include/asm/x86_64/efibind.h +++ b/xen/arch/x86/include/asm/x86_64/efibind.h @@ -117,13 +117,13 @@ typedef uint64_t UINTN; #endif #endif -#define EFIERR(a) (0x8000000000000000 | a) -#define EFI_ERROR_MASK 0x8000000000000000 -#define EFIERR_OEM(a) (0xc000000000000000 | a) +#define EFIERR(a) (0x8000000000000000U | a) +#define EFI_ERROR_MASK 0x8000000000000000U +#define EFIERR_OEM(a) (0xc000000000000000U | a) -#define BAD_POINTER 0xFBFBFBFBFBFBFBFB -#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFF +#define BAD_POINTER 0xFBFBFBFBFBFBFBFBU +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFU #ifdef EFI_NT_EMULATOR #define BREAKPOINT() __asm { int 3 } diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index c5850c26af..28a57fe434 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -34,13 +34,13 @@ #define EFI_REVISION(major, minor) (((major) << 16) | (minor)) #define SMBIOS3_TABLE_GUID \ - { 0xf2fd1544, 0x9794, 0x4a2c, {0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94} } + { 0xf2fd1544U, 0x9794U, 0x4a2cU, {0x99U, 0x2eU, 0xe5U, 0xbbU, 0xcfU, 0x20U, 0xe3U, 0x94U} } #define SHIM_LOCK_PROTOCOL_GUID \ - { 0x605dab50, 0xe046, 0x4300, {0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23} } + { 0x605dab50U, 0xe046U, 0x4300U, {0xabU, 0xb6U, 0x3dU, 0xd8U, 0x10U, 0xddU, 0x8bU, 0x23U} } #define APPLE_PROPERTIES_PROTOCOL_GUID \ - { 0x91bd12fe, 0xf6c3, 0x44fb, { 0xa5, 0xb7, 0x51, 0x22, 0xab, 0x30, 0x3a, 0xe0} } + { 0x91bd12feU, 0xf6c3U, 0x44fbU, { 0xa5U, 0xb7U, 0x51U, 0x22U, 0xabU, 0x30U, 0x3aU, 0xe0U} } #define EFI_SYSTEM_RESOURCE_TABLE_GUID \ - { 0xb122a263, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80} } + { 0xb122a263U, 0x3661U, 0x4f68U, {0x99U, 0x29U, 0x78U, 0xf8U, 0xb0U, 0xd6U, 0x21U, 0x80U} } #define EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION 1 typedef struct { diff --git a/xen/common/efi/runtime.c b/xen/common/efi/runtime.c index 13b0975866..5cb7504c96 100644 --- a/xen/common/efi/runtime.c +++ b/xen/common/efi/runtime.c @@ -698,7 +698,7 @@ int efi_runtime_call(struct xenpf_efi_runtime_call *op) #ifndef COMPAT op->status = status; #else - op->status = (status & 0x3fffffff) | ((status >> 32) & 0xc0000000); + op->status = (status & 0x3fffffffU) | ((status >> 32) & 0xc0000000U); #endif return rc; diff --git a/xen/include/efi/efiapi.h b/xen/include/efi/efiapi.h index a616d1238a..8481e176ae 100644 --- a/xen/include/efi/efiapi.h +++ b/xen/include/efi/efiapi.h @@ -868,19 +868,19 @@ typedef struct _EFI_BOOT_SERVICES { // #define MPS_TABLE_GUID \ - { 0xeb9d2d2f, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d} } + { 0xeb9d2d2fU, 0x2d88U, 0x11d3U, {0x9aU, 0x16U, 0x0U, 0x90U, 0x27U, 0x3fU, 0xc1U, 0x4dU} } #define ACPI_TABLE_GUID \ - { 0xeb9d2d30, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d} } + { 0xeb9d2d30U, 0x2d88U, 0x11d3U, {0x9aU, 0x16U, 0x0U, 0x90U, 0x27U, 0x3fU, 0xc1U, 0x4dU} } #define ACPI_20_TABLE_GUID \ - { 0x8868e871, 0xe4f1, 0x11d3, {0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} } + { 0x8868e871U, 0xe4f1U, 0x11d3U, {0xbcU, 0x22U, 0x0U, 0x80U, 0xc7U, 0x3cU, 0x88U, 0x81U} } #define SMBIOS_TABLE_GUID \ - { 0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d} } + { 0xeb9d2d31U, 0x2d88U, 0x11d3U, {0x9aU, 0x16U, 0x0U, 0x90U, 0x27U, 0x3fU, 0xc1U, 0x4dU} } #define SAL_SYSTEM_TABLE_GUID \ - { 0xeb9d2d32, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d} } + { 0xeb9d2d32U, 0x2d88U, 0x11d3U, {0x9aU, 0x16U, 0x0U, 0x90U, 0x27U, 0x3fU, 0xc1U, 0x4dU} } typedef struct _EFI_CONFIGURATION_TABLE { diff --git a/xen/include/efi/efidef.h b/xen/include/efi/efidef.h index 86a7e111bf..dab60882d2 100644 --- a/xen/include/efi/efidef.h +++ b/xen/include/efi/efidef.h @@ -167,7 +167,7 @@ typedef enum { #define EFI_MEMORY_MORE_RELIABLE 0x0000000000010000 // range requires a runtime mapping -#define EFI_MEMORY_RUNTIME 0x8000000000000000 +#define EFI_MEMORY_RUNTIME 0x8000000000000000U #define EFI_MEMORY_DESCRIPTOR_VERSION 1 typedef struct { diff --git a/xen/include/efi/efiprot.h b/xen/include/efi/efiprot.h index 56d7636b2b..d1a8063bde 100644 --- a/xen/include/efi/efiprot.h +++ b/xen/include/efi/efiprot.h @@ -38,7 +38,7 @@ Revision History // #define BLOCK_IO_PROTOCOL \ - { 0x964e5b21, 0x6459, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b} } + { 0x964e5b21U, 0x6459U, 0x11d2U, {0x8eU, 0x39U, 0x0U, 0xa0U, 0xc9U, 0x69U, 0x72U, 0x3bU} } #define EFI_BLOCK_IO_INTERFACE_REVISION 0x00010000 INTERFACE_DECL(_EFI_BLOCK_IO); @@ -114,7 +114,7 @@ typedef struct _EFI_BLOCK_IO { // #define DISK_IO_PROTOCOL \ - { 0xce345171, 0xba0b, 0x11d2, {0x8e, 0x4f, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b} } + { 0xce345171U, 0xba0bU, 0x11d2U, {0x8eU, 0x4fU, 0x0U, 0xa0U, 0xc9U, 0x69U, 0x72U, 0x3bU} } #define EFI_DISK_IO_INTERFACE_REVISION 0x00010000 INTERFACE_DECL(_EFI_DISK_IO); @@ -153,7 +153,7 @@ typedef struct _EFI_DISK_IO { // #define SIMPLE_FILE_SYSTEM_PROTOCOL \ - { 0x964e5b22, 0x6459, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b} } + { 0x964e5b22U, 0x6459U, 0x11d2U, {0x8eU, 0x39U, 0x0U, 0xa0U, 0xc9U, 0x69U, 0x72U, 0x3bU} } INTERFACE_DECL(_EFI_FILE_IO_INTERFACE); INTERFACE_DECL(_EFI_FILE_HANDLE); @@ -335,7 +335,7 @@ typedef struct { #define SIZE_OF_EFI_FILE_SYSTEM_INFO EFI_FIELD_OFFSET(EFI_FILE_SYSTEM_INFO,VolumeLabel) #define EFI_FILE_SYSTEM_VOLUME_LABEL_INFO_ID \ - { 0xDB47D7D3,0xFE81, 0x11d3, {0x9A, 0x35, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D} } + { 0xDB47D7D3U,0xFE81U, 0x11d3U, {0x9AU, 0x35U, 0x00U, 0x90U, 0x27U, 0x3FU, 0xC1U, 0x4DU} } typedef struct { CHAR16 VolumeLabel[1]; @@ -349,7 +349,7 @@ typedef struct { #define LOAD_FILE_PROTOCOL \ - { 0x56EC3091, 0x954C, 0x11d2, {0x8E, 0x3F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B} } + { 0x56EC3091U, 0x954CU, 0x11d2U, {0x8EU, 0x3FU, 0x00U, 0xA0U, 0xC9U, 0x69U, 0x72U, 0x3BU} } INTERFACE_DECL(_EFI_LOAD_FILE_INTERFACE); @@ -373,7 +373,7 @@ typedef struct _EFI_LOAD_FILE_INTERFACE { // #define DEVICE_IO_PROTOCOL \ - { 0xaf6ac311, 0x84c3, 0x11d2, {0x8e, 0x3c, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b} } + { 0xaf6ac311U, 0x84c3U, 0x11d2U, {0x8eU, 0x3cU, 0x00U, 0xa0U, 0xc9U, 0x69U, 0x72U, 0x3bU} } INTERFACE_DECL(_EFI_DEVICE_IO_INTERFACE); @@ -484,7 +484,7 @@ typedef struct _EFI_DEVICE_IO_INTERFACE { // #define UNICODE_COLLATION_PROTOCOL \ - { 0x1d85cd7f, 0xf43d, 0x11d2, {0x9a, 0xc, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d} } + { 0x1d85cd7fU, 0xf43dU, 0x11d2U, {0x9aU, 0xcU, 0x0U, 0x90U, 0x27U, 0x3fU, 0xc1U, 0x4dU} } #define UNICODE_BYTE_ORDER_MARK (CHAR16)(0xfeff) @@ -557,7 +557,7 @@ typedef struct _EFI_UNICODE_COLLATION_INTERFACE { /* Graphics output protocol */ #define EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID \ { \ - 0x9042a9de, 0x23dc, 0x4a38, {0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a } \ + 0x9042a9deU, 0x23dcU, 0x4a38U, {0x96U, 0xfbU, 0x7aU, 0xdeU, 0xd0U, 0x80U, 0x51U, 0x6aU } \ } typedef struct _EFI_GRAPHICS_OUTPUT_PROTOCOL EFI_GRAPHICS_OUTPUT_PROTOCOL; @@ -730,7 +730,7 @@ struct _EFI_GRAPHICS_OUTPUT_PROTOCOL { * UEFI Specification Version 2.5 Section 11.9 */ #define EFI_EDID_DISCOVERED_PROTOCOL_GUID \ - { 0x1C0C34F6, 0xD380, 0x41FA, { 0xA0, 0x49, 0x8a, 0xD0, 0x6C, 0x1A, 0x66, 0xAA} } + { 0x1C0C34F6U, 0xD380U, 0x41FAU, { 0xA0U, 0x49U, 0x8aU, 0xD0U, 0x6CU, 0x1AU, 0x66U, 0xAAU} } typedef struct _EFI_EDID_DISCOVERED_PROTOCOL { UINT32 SizeOfEdid; @@ -742,7 +742,7 @@ typedef struct _EFI_EDID_DISCOVERED_PROTOCOL { * UEFI Specification Version 2.5 Section 11.9 */ #define EFI_EDID_ACTIVE_PROTOCOL_GUID \ - { 0xBD8C1056, 0x9F36, 0x44EC, { 0x92, 0xA8, 0xA6, 0x33, 0x7F, 0x81, 0x79, 0x86} } + { 0xBD8C1056U, 0x9F36U, 0x44ECU, { 0x92U, 0xA8U, 0xA6U, 0x33U, 0x7FU, 0x81U, 0x79U, 0x86U} } typedef struct _EFI_EDID_ACTIVE_PROTOCOL { UINT32 SizeOfEdid; @@ -754,7 +754,7 @@ typedef struct _EFI_EDID_ACTIVE_PROTOCOL { * UEFI Specification Version 2.5 Section 11.9 */ #define EFI_EDID_OVERRIDE_PROTOCOL_GUID \ - { 0x48ECB431, 0xFB72, 0x45C0, { 0xA9, 0x22, 0xF4, 0x58, 0xFE, 0x04, 0x0B, 0xD5} } + { 0x48ECB431U, 0xFB72U, 0x45C0U, { 0xA9U, 0x22U, 0xF4U, 0x58U, 0xFEU, 0x04U, 0x0BU, 0xD5U} } INTERFACE_DECL(_EFI_EDID_OVERRIDE_PROTOCOL); From patchwork Tue Jun 20 10:34:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78255EB64D8 for ; Tue, 20 Jun 2023 11:01:49 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551549.861189 (Exim 4.92) (envelope-from ) id 1qBZ74-0000dL-6S; Tue, 20 Jun 2023 11:01:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551549.861189; Tue, 20 Jun 2023 11:01:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ73-0000Z6-Vx; Tue, 20 Jun 2023 11:01:29 +0000 Received: by outflank-mailman (input) for mailman id 551549; Tue, 20 Jun 2023 10:35:31 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYhv-0004Pq-MY for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:31 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2de375c1-0f56-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 12:35:30 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 694CC4EE0758; Tue, 20 Jun 2023 12:35:28 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2de375c1-0f56-11ee-b234-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 07/13] xen/x86: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:34:59 +0200 Message-Id: <6c440188b0bdb58dc3e925788956b3d301d5a18b.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin --- xen/arch/x86/cpu/vpmu_intel.c | 4 ++-- xen/arch/x86/hvm/vmx/vmcs.c | 6 ++--- xen/arch/x86/hvm/vmx/vvmx.c | 12 +++++----- xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 6 ++--- xen/arch/x86/include/asm/hvm/vmx/vmx.h | 32 ++++++++++++------------- 5 files changed, 30 insertions(+), 30 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 35e350578b..7a0ff76d8e 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -950,10 +950,10 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) fixed_ctrl_mask |= (FIXED_CTR_CTRL_ANYTHREAD_MASK << (FIXED_CTR_CTRL_BITS * i)); - fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1); + fixed_counters_mask = ~((1Ull << core2_get_bitwidth_fix_count()) - 1); global_ctrl_mask = ~((((1ULL << fixed_pmc_cnt) - 1) << 32) | ((1ULL << arch_pmc_cnt) - 1)); - global_ovf_ctrl_mask = ~(0xC000000000000000 | + global_ovf_ctrl_mask = ~(0xC000000000000000U | (((1ULL << fixed_pmc_cnt) - 1) << 32) | ((1ULL << arch_pmc_cnt) - 1)); if ( version > 2 ) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index b209563625..d5a2b847a9 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -911,7 +911,7 @@ void vmx_clear_msr_intercept(struct vcpu *v, unsigned int msr, if ( type & VMX_MSR_W ) clear_bit(msr, msr_bitmap->write_low); } - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) { msr &= 0x1fff; if ( type & VMX_MSR_R ) @@ -939,7 +939,7 @@ void vmx_set_msr_intercept(struct vcpu *v, unsigned int msr, if ( type & VMX_MSR_W ) set_bit(msr, msr_bitmap->write_low); } - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) { msr &= 0x1fff; if ( type & VMX_MSR_R ) @@ -957,7 +957,7 @@ bool vmx_msr_is_intercepted(struct vmx_msr_bitmap *msr_bitmap, if ( msr <= 0x1fff ) return test_bit(msr, is_write ? msr_bitmap->write_low : msr_bitmap->read_low); - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) return test_bit(msr & 0x1fff, is_write ? msr_bitmap->write_high : msr_bitmap->read_high); else diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 1034534c97..f59de0f124 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -257,14 +257,14 @@ uint64_t get_vvmcs_virtual(void *vvmcs, uint32_t vmcs_encoding) switch ( enc.width ) { case VVMCS_WIDTH_16: - res &= 0xffff; + res &= 0xffffU; break; case VVMCS_WIDTH_64: if ( enc.access_type ) res >>= 32; break; case VVMCS_WIDTH_32: - res &= 0xffffffff; + res &= 0xffffffffU; break; case VVMCS_WIDTH_NATURAL: default: @@ -311,19 +311,19 @@ void set_vvmcs_virtual(void *vvmcs, uint32_t vmcs_encoding, uint64_t val) switch ( enc.width ) { case VVMCS_WIDTH_16: - res = val & 0xffff; + res = val & 0xffffU; break; case VVMCS_WIDTH_64: if ( enc.access_type ) { - res &= 0xffffffff; + res &= 0xffffffffU; res |= val << 32; } else res = val; break; case VVMCS_WIDTH_32: - res = val & 0xffffffff; + res = val & 0xffffffffU; break; case VVMCS_WIDTH_NATURAL: default: @@ -2307,7 +2307,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) break; case MSR_IA32_VMX_CR0_FIXED1: /* allow 0-settings for all bits */ - data = 0xffffffff; + data = 0xffffffffU; break; case MSR_IA32_VMX_CR4_FIXED0: /* VMXE bit must be 1 in VMX operation */ diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h index d07fcb2bc9..4acf3970f5 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -207,7 +207,7 @@ void vmx_vmcs_reload(struct vcpu *v); #define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000 #define CPU_BASED_MONITOR_EXITING 0x20000000 #define CPU_BASED_PAUSE_EXITING 0x40000000 -#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 +#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000U extern u32 vmx_cpu_based_exec_control; #define PIN_BASED_EXT_INTR_MASK 0x00000001 @@ -257,7 +257,7 @@ extern u32 vmx_vmentry_control; #define SECONDARY_EXEC_XSAVES 0x00100000 #define SECONDARY_EXEC_TSC_SCALING 0x02000000 #define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000 -#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000 +#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000U extern u32 vmx_secondary_exec_control; #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 @@ -346,7 +346,7 @@ extern u64 vmx_ept_vpid_cap; #define cpu_has_vmx_notify_vm_exiting \ (vmx_secondary_exec_control & SECONDARY_EXEC_NOTIFY_VM_EXITING) -#define VMCS_RID_TYPE_MASK 0x80000000 +#define VMCS_RID_TYPE_MASK 0x80000000U /* GUEST_INTERRUPTIBILITY_INFO flags. */ #define VMX_INTR_SHADOW_STI 0x00000001 diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h index 36c108d879..b0a834d327 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -136,7 +136,7 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) /* * Exit Reasons */ -#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000 +#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000U #define VMX_EXIT_REASONS_BUS_LOCK (1u << 26) #define EXIT_REASON_EXCEPTION_NMI 0 @@ -208,17 +208,17 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) * Note INTR_INFO_NMI_UNBLOCKED_BY_IRET is also used with Exit Qualification * field for EPT violations, PML full and SPP-related event vmexits. */ -#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ -#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ -#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ -#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */ -#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ -#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 +#define INTR_INFO_VECTOR_MASK 0xffU /* 7:0 */ +#define INTR_INFO_INTR_TYPE_MASK 0x700U /* 10:8 */ +#define INTR_INFO_DELIVER_CODE_MASK 0x800U /* 11 */ +#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */ +#define INTR_INFO_VALID_MASK 0x80000000U /* 31 */ +#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000U /* * Exit Qualifications for NOTIFY VM EXIT */ -#define NOTIFY_VM_CONTEXT_INVALID 1u +#define NOTIFY_VM_CONTEXT_INVALID 1U /* * Exit Qualifications for MOV for Control Register Access @@ -247,14 +247,14 @@ typedef union cr_access_qual { * Access Rights */ #define X86_SEG_AR_SEG_TYPE 0xf /* 3:0, segment type */ -#define X86_SEG_AR_DESC_TYPE (1u << 4) /* 4, descriptor type */ +#define X86_SEG_AR_DESC_TYPE (1U << 4) /* 4, descriptor type */ #define X86_SEG_AR_DPL 0x60 /* 6:5, descriptor privilege level */ -#define X86_SEG_AR_SEG_PRESENT (1u << 7) /* 7, segment present */ -#define X86_SEG_AR_AVL (1u << 12) /* 12, available for system software */ -#define X86_SEG_AR_CS_LM_ACTIVE (1u << 13) /* 13, long mode active (CS only) */ -#define X86_SEG_AR_DEF_OP_SIZE (1u << 14) /* 14, default operation size */ -#define X86_SEG_AR_GRANULARITY (1u << 15) /* 15, granularity */ -#define X86_SEG_AR_SEG_UNUSABLE (1u << 16) /* 16, segment unusable */ +#define X86_SEG_AR_SEG_PRESENT (1U << 7) /* 7, segment present */ +#define X86_SEG_AR_AVL (1U << 12) /* 12, available for system software */ +#define X86_SEG_AR_CS_LM_ACTIVE (1U << 13) /* 13, long mode active (CS only) */ +#define X86_SEG_AR_DEF_OP_SIZE (1U << 14) /* 14, default operation size */ +#define X86_SEG_AR_GRANULARITY (1U << 15) /* 15, granularity */ +#define X86_SEG_AR_SEG_UNUSABLE (1U << 16) /* 16, segment unusable */ #define VMCALL_OPCODE ".byte 0x0f,0x01,0xc1\n" #define VMCLEAR_OPCODE ".byte 0x66,0x0f,0xc7\n" /* reg/opcode: /6 */ @@ -606,7 +606,7 @@ static inline void vmx_pi_hooks_assign(struct domain *d) {} static inline void vmx_pi_hooks_deassign(struct domain *d) {} #endif -#define APIC_INVALID_DEST 0xffffffff +#define APIC_INVALID_DEST 0xffffffffU /* EPT violation qualifications definitions */ typedef union ept_qual { From patchwork Tue Jun 20 10:35:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F380EB64D7 for ; Tue, 20 Jun 2023 11:01:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551551.861200 (Exim 4.92) (envelope-from ) id 1qBZ75-0000op-2I; Tue, 20 Jun 2023 11:01:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551551.861200; Tue, 20 Jun 2023 11:01:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ74-0000mI-En; Tue, 20 Jun 2023 11:01:30 +0000 Received: by outflank-mailman (input) for mailman id 551551; Tue, 20 Jun 2023 10:35:33 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYhx-0004Pq-7R for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:33 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2ef2b969-0f56-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 12:35:32 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id DC6234EE0752; Tue, 20 Jun 2023 12:35:30 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2ef2b969-0f56-11ee-b234-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Paul Durrant , =?utf-8?q?Rog?= =?utf-8?q?er_Pau_Monn=C3=A9?= , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 08/13] xen/pci: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:35:00 +0200 Message-Id: <3d1a98c8070d4e502402356dd65153dcc813edef.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- xen/drivers/passthrough/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 07d1986d33..95846e84f2 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -990,8 +990,8 @@ bool_t __init pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func) vendor = pci_conf_read32(PCI_SBDF(seg, bus, dev, func), PCI_VENDOR_ID); /* some broken boards return 0 or ~0 if a slot is empty: */ - if ( (vendor == 0xffffffff) || (vendor == 0x00000000) || - (vendor == 0x0000ffff) || (vendor == 0xffff0000) ) + if ( (vendor == 0xffffffffU) || (vendor == 0x00000000U) || + (vendor == 0x0000ffffU) || (vendor == 0xffff0000U) ) return 0; return 1; } From patchwork Tue Jun 20 10:35:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81952C001B3 for ; Tue, 20 Jun 2023 11:01:51 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551553.861205 (Exim 4.92) (envelope-from ) id 1qBZ75-0000wi-BN; Tue, 20 Jun 2023 11:01:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551553.861205; Tue, 20 Jun 2023 11:01:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ74-0000tY-Tq; Tue, 20 Jun 2023 11:01:30 +0000 Received: by outflank-mailman (input) for mailman id 551553; Tue, 20 Jun 2023 10:35:35 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYhz-0004Ou-8Q for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:35 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2fa244a0-0f56-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 12:35:33 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 8BB184EE0754; Tue, 20 Jun 2023 12:35:32 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2fa244a0-0f56-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Juergen Gross , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 09/13] xen/public: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:35:01 +0200 Message-Id: <2214598125081ccfb324555288bee0340f8b1024.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin --- xen/include/public/io/ring.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/include/public/io/ring.h b/xen/include/public/io/ring.h index 025939278b..6a6deeee8f 100644 --- a/xen/include/public/io/ring.h +++ b/xen/include/public/io/ring.h @@ -36,11 +36,11 @@ typedef unsigned int RING_IDX; /* Round a 32-bit unsigned constant down to the nearest power of two. */ -#define __RD2(_x) (((_x) & 0x00000002) ? 0x2 : ((_x) & 0x1)) -#define __RD4(_x) (((_x) & 0x0000000c) ? __RD2((_x)>>2)<<2 : __RD2(_x)) -#define __RD8(_x) (((_x) & 0x000000f0) ? __RD4((_x)>>4)<<4 : __RD4(_x)) -#define __RD16(_x) (((_x) & 0x0000ff00) ? __RD8((_x)>>8)<<8 : __RD8(_x)) -#define __RD32(_x) (((_x) & 0xffff0000) ? __RD16((_x)>>16)<<16 : __RD16(_x)) +#define __RD2(_x) (((_x) & 0x00000002U) ? 0x2 : ((_x) & 0x1)) +#define __RD4(_x) (((_x) & 0x0000000cU) ? __RD2((_x)>>2)<<2 : __RD2(_x)) +#define __RD8(_x) (((_x) & 0x000000f0U) ? __RD4((_x)>>4)<<4 : __RD4(_x)) +#define __RD16(_x) (((_x) & 0x0000ff00U) ? __RD8((_x)>>8)<<8 : __RD8(_x)) +#define __RD32(_x) (((_x) & 0xffff0000U) ? __RD16((_x)>>16)<<16 : __RD16(_x)) /* * Calculate size of a shared ring, given the total available space for the From patchwork Tue Jun 20 10:35:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D134EB64DD for ; Tue, 20 Jun 2023 11:01:50 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551557.861223 (Exim 4.92) (envelope-from ) id 1qBZ76-0001MN-N6; Tue, 20 Jun 2023 11:01:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551557.861223; Tue, 20 Jun 2023 11:01:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ76-0001Hz-5A; Tue, 20 Jun 2023 11:01:32 +0000 Received: by outflank-mailman (input) for mailman id 551557; Tue, 20 Jun 2023 10:35:40 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYi4-0004Ou-SI for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:40 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 3099a977-0f56-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 12:35:35 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id AE2424EE0753; Tue, 20 Jun 2023 12:35:33 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3099a977-0f56-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 10/13] xen/x86: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:35:02 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- xen/arch/x86/monitor.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/monitor.c b/xen/arch/x86/monitor.c index d4857faf8a..dc336c239a 100644 --- a/xen/arch/x86/monitor.c +++ b/xen/arch/x86/monitor.c @@ -48,17 +48,17 @@ static unsigned long *monitor_bitmap_for_msr(const struct domain *d, u32 *msr) switch ( *msr ) { - case 0 ... 0x1fff: + case 0 ... 0x1fffU: BUILD_BUG_ON(sizeof(d->arch.monitor.msr_bitmap->low) * 8 <= 0x1fff); return d->arch.monitor.msr_bitmap->low; - case 0x40000000 ... 0x40001fff: + case 0x40000000U ... 0x40001fffU: BUILD_BUG_ON( sizeof(d->arch.monitor.msr_bitmap->hypervisor) * 8 <= 0x1fff); *msr &= 0x1fff; return d->arch.monitor.msr_bitmap->hypervisor; - case 0xc0000000 ... 0xc0001fff: + case 0xc0000000U ... 0xc0001fffU: BUILD_BUG_ON(sizeof(d->arch.monitor.msr_bitmap->high) * 8 <= 0x1fff); *msr &= 0x1fff; return d->arch.monitor.msr_bitmap->high; From patchwork Tue Jun 20 10:35:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C06BC0015E for ; Tue, 20 Jun 2023 11:01:59 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551555.861210 (Exim 4.92) (envelope-from ) id 1qBZ75-0001AM-Qp; Tue, 20 Jun 2023 11:01:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551555.861210; Tue, 20 Jun 2023 11:01:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ75-00015l-Gm; Tue, 20 Jun 2023 11:01:31 +0000 Received: by outflank-mailman (input) for mailman id 551555; Tue, 20 Jun 2023 10:35:37 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYi1-0004Pq-7O for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:37 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 314738fd-0f56-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 12:35:36 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 506864EE0755; Tue, 20 Jun 2023 12:35:35 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 314738fd-0f56-11ee-b234-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 11/13] xen/vpci: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:35:03 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- xen/drivers/vpci/msi.c | 2 +- xen/drivers/vpci/msix.c | 2 +- xen/drivers/vpci/vpci.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 8f2b59e61a..7908a5dac6 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -124,7 +124,7 @@ static void cf_check address_hi_write( struct vpci_msi *msi = data; /* Clear and update high part. */ - msi->address &= 0xffffffff; + msi->address &= 0xffffffffU; msi->address |= (uint64_t)val << 32; update_msi(pdev, msi); diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 25bde77586..d440ffcd81 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -531,7 +531,7 @@ static int cf_check msix_write( case PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET: entry->updated = true; - entry->addr &= 0xffffffff; + entry->addr &= 0xffffffffU; entry->addr |= (uint64_t)data << 32; break; diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index d73fa76302..3bec9a4153 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -319,7 +319,7 @@ static void vpci_write_hw(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, static uint32_t merge_result(uint32_t data, uint32_t new, unsigned int size, unsigned int offset) { - uint32_t mask = 0xffffffff >> (32 - 8 * size); + uint32_t mask = 0xffffffffU >> (32 - 8 * size); return (data & ~(mask << (offset * 8))) | ((new & mask) << (offset * 8)); } @@ -402,7 +402,7 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size) data = merge_result(data, tmp_data, size - data_offset, data_offset); } - return data & (0xffffffff >> (32 - 8 * size)); + return data & (0xffffffffU >> (32 - 8 * size)); } /* @@ -427,7 +427,7 @@ static void vpci_write_helper(const struct pci_dev *pdev, data = merge_result(val, data, size, offset); } - r->write(pdev, r->offset, data & (0xffffffff >> (32 - 8 * r->size)), + r->write(pdev, r->offset, data & (0xffffffffU >> (32 - 8 * r->size)), r->private); } From patchwork Tue Jun 20 10:35:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 596E6EB64DB for ; Tue, 20 Jun 2023 11:01:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551560.861248 (Exim 4.92) (envelope-from ) id 1qBZ78-000214-M4; Tue, 20 Jun 2023 11:01:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551560.861248; Tue, 20 Jun 2023 11:01:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBZ78-0001sq-1B; Tue, 20 Jun 2023 11:01:34 +0000 Received: by outflank-mailman (input) for mailman id 551560; Tue, 20 Jun 2023 10:35:43 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYi6-0004Ou-Sc for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:43 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 324ab0d2-0f56-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 12:35:38 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 76FC14EE0754; Tue, 20 Jun 2023 12:35:36 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 324ab0d2-0f56-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Paul Durrant , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 12/13] xen/x86: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:35:04 +0200 Message-Id: <27690fdf9658339f12061f1bd171ebe5f969eb1b.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin --- xen/arch/x86/apic.c | 2 +- xen/arch/x86/cpu-policy.c | 8 +- xen/arch/x86/cpu/mcheck/mce-apei.c | 8 +- xen/arch/x86/cpuid.c | 8 +- xen/arch/x86/efi/efi-boot.h | 6 +- xen/arch/x86/hvm/hypercall.c | 2 +- xen/arch/x86/hvm/irq.c | 2 +- xen/arch/x86/hvm/pmtimer.c | 4 +- xen/arch/x86/hvm/stdvga.c | 66 +++--- xen/arch/x86/hvm/viridian/viridian.c | 2 +- xen/arch/x86/hvm/vlapic.c | 6 +- xen/arch/x86/include/asm/apicdef.h | 2 +- xen/arch/x86/include/asm/config.h | 2 +- xen/arch/x86/include/asm/guest/hyperv-tlfs.h | 28 +-- xen/arch/x86/include/asm/hpet.h | 2 +- xen/arch/x86/include/asm/hvm/trace.h | 4 +- xen/arch/x86/include/asm/hvm/vioapic.h | 2 +- xen/arch/x86/include/asm/msi.h | 2 +- xen/arch/x86/include/asm/msr-index.h | 204 +++++++++---------- xen/arch/x86/include/asm/pci.h | 8 +- xen/arch/x86/include/asm/x86-defns.h | 24 +-- xen/arch/x86/percpu.c | 2 +- xen/arch/x86/psr.c | 2 +- xen/arch/x86/spec_ctrl.c | 8 +- xen/arch/x86/x86_64/acpi_mmcfg.c | 2 +- xen/arch/x86/x86_64/pci.c | 2 +- xen/arch/x86/x86_emulate/x86_emulate.h | 2 +- xen/include/public/arch-x86/xen-x86_64.h | 8 +- xen/lib/x86/cpuid.c | 8 +- xen/lib/x86/policy.c | 2 +- 30 files changed, 214 insertions(+), 214 deletions(-) diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index f71474d47d..03c5c0f2ee 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1211,7 +1211,7 @@ static void __init calibrate_APIC_clock(void) * Setup the APIC counter to maximum. There is no way the lapic * can underflow in the 100ms detection time frame. */ - __setup_APIC_LVTT(0xffffffff); + __setup_APIC_LVTT(0xffffffffU); bus_freq = calibrate_apic_timer(); if ( !bus_freq ) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index f40eeb8be8..5516249cb6 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -321,7 +321,7 @@ static void recalculate_misc(struct cpu_policy *p) p->extd.vendor_edx = p->basic.vendor_edx; p->extd.raw_fms = p->basic.raw_fms; - p->extd.raw[0x1].b &= 0xff00ffff; + p->extd.raw[0x1].b &= 0xff00ffffU; p->extd.e1d |= p->basic._1d & CPUID_COMMON_1D_FEATURES; p->extd.raw[0x8].a &= 0x0000ffff; /* GuestMaxPhysAddr hidden. */ @@ -378,9 +378,9 @@ static void __init calculate_host_policy(void) * this information. */ if ( cpu_has_lfence_dispatch ) - max_extd_leaf = max(max_extd_leaf, 0x80000021); + max_extd_leaf = max(max_extd_leaf, 0x80000021U); - p->extd.max_leaf = 0x80000000 | min_t(uint32_t, max_extd_leaf & 0xffff, + p->extd.max_leaf = 0x80000000U | min_t(uint32_t, max_extd_leaf & 0xffffU, ARRAY_SIZE(p->extd.raw) - 1); x86_cpu_featureset_to_policy(boot_cpu_data.x86_capability, p); @@ -768,7 +768,7 @@ void recalculate_cpuid_policy(struct domain *d) p->basic.max_leaf = min(p->basic.max_leaf, max->basic.max_leaf); p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf); - p->extd.max_leaf = 0x80000000 | min(p->extd.max_leaf & 0xffff, + p->extd.max_leaf = 0x80000000U | min(p->extd.max_leaf & 0xffff, ((p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ? CPUID_GUEST_NR_EXTD_AMD diff --git a/xen/arch/x86/cpu/mcheck/mce-apei.c b/xen/arch/x86/cpu/mcheck/mce-apei.c index 53b6735896..1aa213b321 100644 --- a/xen/arch/x86/cpu/mcheck/mce-apei.c +++ b/xen/arch/x86/cpu/mcheck/mce-apei.c @@ -37,11 +37,11 @@ #include "mce.h" #define CPER_CREATOR_MCE \ - UUID_LE(0x75a574e3, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c, \ - 0x64, 0x90, 0xb8, 0x9d) + UUID_LE(0x75a574e3U, 0x5052U, 0x4b29U, 0x8aU, 0x8eU, 0xbeU, 0x2cU, \ + 0x64U, 0x90U, 0xb8U, 0x9dU) #define CPER_SECTION_TYPE_MCE \ - UUID_LE(0xfe08ffbe, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96, \ - 0x04, 0x4a, 0x38, 0xfc) + UUID_LE(0xfe08ffbeU, 0x95e4U, 0x4be7U, 0xbcU, 0x73U, 0x40U, 0x96U, \ + 0x04U, 0x4aU, 0x38U, 0xfcU) /* * CPER specification (in UEFI specification 2.3 appendix N) requires diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 455a09b2dd..7290a979c6 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -93,7 +93,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, } break; - case 0x40000000 ... 0x400000ff: + case 0x40000000U ... 0x400000ffU: if ( is_viridian_domain(d) ) return cpuid_viridian_leaves(v, leaf, subleaf, res); @@ -103,10 +103,10 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, * Intel reserve up until 0x4fffffff for hypervisor use. AMD reserve * only until 0x400000ff, but we already use double that. */ - case 0x40000100 ... 0x400001ff: + case 0x40000100U ... 0x400001ffU: return cpuid_hypervisor_leaves(v, leaf, subleaf, res); - case 0x80000000 ... 0x80000000 + CPUID_GUEST_NR_EXTD - 1: + case 0x80000000U ... 0x80000000U + CPUID_GUEST_NR_EXTD - 1: ASSERT((p->extd.max_leaf & 0xffff) < ARRAY_SIZE(p->extd.raw)); if ( (leaf & 0xffff) > min_t(uint32_t, p->extd.max_leaf & 0xffff, ARRAY_SIZE(p->extd.raw) - 1) ) @@ -352,7 +352,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, } break; - case 0x80000001: + case 0x80000001U: /* SYSCALL is hidden outside of long mode on Intel. */ if ( p->x86_vendor == X86_VENDOR_INTEL && is_hvm_domain(d) && !hvm_long_mode_active(v) ) diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h index c94e53d139..9fe7b06082 100644 --- a/xen/arch/x86/efi/efi-boot.h +++ b/xen/arch/x86/efi/efi-boot.h @@ -740,16 +740,16 @@ static void __init efi_arch_handle_module(const struct file *file, static void __init efi_arch_cpu(void) { - uint32_t eax = cpuid_eax(0x80000000); + uint32_t eax = cpuid_eax(0x80000000U); uint32_t *caps = boot_cpu_data.x86_capability; boot_tsc_stamp = rdtsc(); caps[FEATURESET_1c] = cpuid_ecx(1); - if ( (eax >> 16) == 0x8000 && eax > 0x80000000 ) + if ( (eax >> 16) == 0x8000 && eax > 0x80000000U ) { - caps[FEATURESET_e1d] = cpuid_edx(0x80000001); + caps[FEATURESET_e1d] = cpuid_edx(0x80000001U); if ( cpu_has_nx ) trampoline_efer |= EFER_NXE; diff --git a/xen/arch/x86/hvm/hypercall.c b/xen/arch/x86/hvm/hypercall.c index 20d266ffd5..eeb73e1aa5 100644 --- a/xen/arch/x86/hvm/hypercall.c +++ b/xen/arch/x86/hvm/hypercall.c @@ -129,7 +129,7 @@ int hvm_hypercall(struct cpu_user_regs *regs) break; } - if ( (eax & 0x80000000) && is_viridian_domain(currd) ) + if ( (eax & 0x80000000U) && is_viridian_domain(currd) ) { int ret; diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c index 1258371eb0..5c00127cfc 100644 --- a/xen/arch/x86/hvm/irq.c +++ b/xen/arch/x86/hvm/irq.c @@ -383,7 +383,7 @@ int hvm_inject_msi(struct domain *d, uint64_t addr, uint32_t data) if ( !vector ) { - int pirq = ((addr >> 32) & 0xffffff00) | dest; + int pirq = ((addr >> 32) & 0xffffff00U) | dest; if ( pirq > 0 ) { diff --git a/xen/arch/x86/hvm/pmtimer.c b/xen/arch/x86/hvm/pmtimer.c index 2145c531b6..eb4a455763 100644 --- a/xen/arch/x86/hvm/pmtimer.c +++ b/xen/arch/x86/hvm/pmtimer.c @@ -40,8 +40,8 @@ #define SCI_IRQ 9 /* We provide a 32-bit counter (must match the TMR_VAL_EXT bit in the FADT) */ -#define TMR_VAL_MASK (0xffffffff) -#define TMR_VAL_MSB (0x80000000) +#define TMR_VAL_MASK (0xffffffffU) +#define TMR_VAL_MSB (0x80000000U) /* Dispatch SCIs based on the PM1a_STS and PM1a_EN registers */ static void pmt_update_sci(PMTState *s) diff --git a/xen/arch/x86/hvm/stdvga.c b/xen/arch/x86/hvm/stdvga.c index 798a9a0549..52efa8348a 100644 --- a/xen/arch/x86/hvm/stdvga.c +++ b/xen/arch/x86/hvm/stdvga.c @@ -39,46 +39,46 @@ #define PAT(x) (x) static const uint32_t mask16[16] = { - PAT(0x00000000), - PAT(0x000000ff), - PAT(0x0000ff00), - PAT(0x0000ffff), - PAT(0x00ff0000), - PAT(0x00ff00ff), - PAT(0x00ffff00), - PAT(0x00ffffff), - PAT(0xff000000), - PAT(0xff0000ff), - PAT(0xff00ff00), - PAT(0xff00ffff), - PAT(0xffff0000), - PAT(0xffff00ff), - PAT(0xffffff00), - PAT(0xffffffff), + PAT(0x00000000U), + PAT(0x000000ffU), + PAT(0x0000ff00U), + PAT(0x0000ffffU), + PAT(0x00ff0000U), + PAT(0x00ff00ffU), + PAT(0x00ffff00U), + PAT(0x00ffffffU), + PAT(0xff000000U), + PAT(0xff0000ffU), + PAT(0xff00ff00U), + PAT(0xff00ffffU), + PAT(0xffff0000U), + PAT(0xffff00ffU), + PAT(0xffffff00U), + PAT(0xffffffffU), }; /* force some bits to zero */ static const uint8_t sr_mask[8] = { - (uint8_t)~0xfc, - (uint8_t)~0xc2, - (uint8_t)~0xf0, - (uint8_t)~0xc0, - (uint8_t)~0xf1, - (uint8_t)~0xff, - (uint8_t)~0xff, - (uint8_t)~0x00, + (uint8_t)~0xfcU, + (uint8_t)~0xc2U, + (uint8_t)~0xf0U, + (uint8_t)~0xc0U, + (uint8_t)~0xf1U, + (uint8_t)~0xffU, + (uint8_t)~0xffU, + (uint8_t)~0x00U, }; static const uint8_t gr_mask[9] = { - (uint8_t)~0xf0, /* 0x00 */ - (uint8_t)~0xf0, /* 0x01 */ - (uint8_t)~0xf0, /* 0x02 */ - (uint8_t)~0xe0, /* 0x03 */ - (uint8_t)~0xfc, /* 0x04 */ - (uint8_t)~0x84, /* 0x05 */ - (uint8_t)~0xf0, /* 0x06 */ - (uint8_t)~0xf0, /* 0x07 */ - (uint8_t)~0x00, /* 0x08 */ + (uint8_t)~0xf0U, /* 0x00 */ + (uint8_t)~0xf0U, /* 0x01 */ + (uint8_t)~0xf0U, /* 0x02 */ + (uint8_t)~0xe0U, /* 0x03 */ + (uint8_t)~0xfcU, /* 0x04 */ + (uint8_t)~0x84U, /* 0x05 */ + (uint8_t)~0xf0U, /* 0x06 */ + (uint8_t)~0xf0U, /* 0x07 */ + (uint8_t)~0x00U, /* 0x08 */ }; static uint8_t *vram_getb(struct hvm_hw_stdvga *s, unsigned int a) diff --git a/xen/arch/x86/hvm/viridian/viridian.c b/xen/arch/x86/hvm/viridian/viridian.c index 7405c117bc..61171e3363 100644 --- a/xen/arch/x86/hvm/viridian/viridian.c +++ b/xen/arch/x86/hvm/viridian/viridian.c @@ -291,7 +291,7 @@ static void enable_hypercall_page(struct domain *d) * calling convention) to differentiate Xen and Viridian hypercalls. */ *(u8 *)(p + 0) = 0x0d; /* orl $0x80000000, %eax */ - *(u32 *)(p + 1) = 0x80000000; + *(u32 *)(p + 1) = 0x80000000U; *(u8 *)(p + 5) = 0x0f; /* vmcall/vmmcall */ *(u8 *)(p + 6) = 0x01; *(u8 *)(p + 7) = (cpu_has_vmx ? 0xc1 : 0xd9); diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 785d5d88d9..04009007dd 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -237,7 +237,7 @@ bool_t vlapic_match_dest( case APIC_DEST_NOSHORT: if ( dest_mode ) return vlapic_match_logical_addr(target, dest); - return (dest == _VLAPIC_ID(target, 0xffffffff)) || + return (dest == _VLAPIC_ID(target, 0xffffffffU)) || (dest == VLAPIC_ID(target)); case APIC_DEST_SELF: @@ -467,7 +467,7 @@ static bool_t is_multicast_dest(struct vlapic *vlapic, unsigned int short_hand, return short_hand != APIC_DEST_SELF; if ( vlapic_x2apic_mode(vlapic) ) - return dest_mode ? hweight16(dest) > 1 : dest == 0xffffffff; + return dest_mode ? hweight16(dest) > 1 : dest == 0xffffffffU; if ( dest_mode ) return hweight8(dest & @@ -831,7 +831,7 @@ void vlapic_reg_write(struct vcpu *v, unsigned int reg, uint32_t val) break; case APIC_ICR2: - vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000); + vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000U); break; case APIC_LVTT: /* LVT Timer Reg */ diff --git a/xen/arch/x86/include/asm/apicdef.h b/xen/arch/x86/include/asm/apicdef.h index 2440d83c8d..7f21d3f49c 100644 --- a/xen/arch/x86/include/asm/apicdef.h +++ b/xen/arch/x86/include/asm/apicdef.h @@ -8,7 +8,7 @@ * Ingo Molnar , 1999, 2000 */ -#define APIC_DEFAULT_PHYS_BASE 0xfee00000 +#define APIC_DEFAULT_PHYS_BASE 0xfee00000U #define APIC_ID 0x20 #define APIC_ID_MASK (0xFFu<<24) diff --git a/xen/arch/x86/include/asm/config.h b/xen/arch/x86/include/asm/config.h index fbc4bb3416..bbced338be 100644 --- a/xen/arch/x86/include/asm/config.h +++ b/xen/arch/x86/include/asm/config.h @@ -257,7 +257,7 @@ extern unsigned char boot_edid_info[128]; #endif /* CONFIG_PV32 */ #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START -#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000 +#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000U #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \ ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2) diff --git a/xen/arch/x86/include/asm/guest/hyperv-tlfs.h b/xen/arch/x86/include/asm/guest/hyperv-tlfs.h index 38f997a0c8..a6915ad731 100644 --- a/xen/arch/x86/include/asm/guest/hyperv-tlfs.h +++ b/xen/arch/x86/include/asm/guest/hyperv-tlfs.h @@ -471,30 +471,30 @@ typedef struct _HV_REFERENCE_TSC_PAGE { /* Define hypervisor message types. */ enum hv_message_type { - HVMSG_NONE = 0x00000000, + HVMSG_NONE = 0x00000000U, /* Memory access messages. */ - HVMSG_UNMAPPED_GPA = 0x80000000, - HVMSG_GPA_INTERCEPT = 0x80000001, + HVMSG_UNMAPPED_GPA = 0x80000000U, + HVMSG_GPA_INTERCEPT = 0x80000001U, /* Timer notification messages. */ - HVMSG_TIMER_EXPIRED = 0x80000010, + HVMSG_TIMER_EXPIRED = 0x80000010U, /* Error messages. */ - HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, - HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, - HVMSG_UNSUPPORTED_FEATURE = 0x80000022, + HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020U, + HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021U, + HVMSG_UNSUPPORTED_FEATURE = 0x80000022U, /* Trace buffer complete messages. */ - HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, + HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040U, /* Platform-specific processor intercept messages. */ - HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, - HVMSG_X64_MSR_INTERCEPT = 0x80010001, - HVMSG_X64_CPUID_INTERCEPT = 0x80010002, - HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, - HVMSG_X64_APIC_EOI = 0x80010004, - HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 + HVMSG_X64_IOPORT_INTERCEPT = 0x80010000U, + HVMSG_X64_MSR_INTERCEPT = 0x80010001U, + HVMSG_X64_CPUID_INTERCEPT = 0x80010002U, + HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003U, + HVMSG_X64_APIC_EOI = 0x80010004U, + HVMSG_X64_LEGACY_FP_ERROR = 0x80010005U }; /* Define synthetic interrupt controller message flags. */ diff --git a/xen/arch/x86/include/asm/hpet.h b/xen/arch/x86/include/asm/hpet.h index 9919f74730..c5e8e9c8db 100644 --- a/xen/arch/x86/include/asm/hpet.h +++ b/xen/arch/x86/include/asm/hpet.h @@ -41,7 +41,7 @@ #define HPET_TN_ROUTE 0x3e00 #define HPET_TN_FSB 0x4000 #define HPET_TN_FSB_CAP 0x8000 -#define HPET_TN_RESERVED 0xffff0081 +#define HPET_TN_RESERVED 0xffff0081U #define HPET_TN_INT_ROUTE_CAP (0xffffffffULL << 32) diff --git a/xen/arch/x86/include/asm/hvm/trace.h b/xen/arch/x86/include/asm/hvm/trace.h index 696e42eb94..60b88b9c1f 100644 --- a/xen/arch/x86/include/asm/hvm/trace.h +++ b/xen/arch/x86/include/asm/hvm/trace.h @@ -58,7 +58,7 @@ #define DO_TRC_HVM_VLAPIC DEFAULT_HVM_MISC -#define TRC_PAR_LONG(par) ((par)&0xFFFFFFFF),((par)>>32) +#define TRC_PAR_LONG(par) ((par)&0xFFFFFFFFU),((par)>>32) #define TRACE_2_LONG_2D(_e, d1, d2, ...) \ TRACE_4D(_e, d1, d2) @@ -93,7 +93,7 @@ HVMTRACE_ND(evt, 0, 0) #define HVMTRACE_LONG_1D(evt, d1) \ - HVMTRACE_2D(evt ## 64, (d1) & 0xFFFFFFFF, (d1) >> 32) + HVMTRACE_2D(evt ## 64, (d1) & 0xFFFFFFFFU, (d1) >> 32) #define HVMTRACE_LONG_2D(evt, d1, d2, ...) \ HVMTRACE_3D(evt ## 64, d1, d2) #define HVMTRACE_LONG_3D(evt, d1, d2, d3, ...) \ diff --git a/xen/arch/x86/include/asm/hvm/vioapic.h b/xen/arch/x86/include/asm/hvm/vioapic.h index 2944ec20dd..68af6dce79 100644 --- a/xen/arch/x86/include/asm/hvm/vioapic.h +++ b/xen/arch/x86/include/asm/hvm/vioapic.h @@ -32,7 +32,7 @@ #define VIOAPIC_EDGE_TRIG 0 #define VIOAPIC_LEVEL_TRIG 1 -#define VIOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000 +#define VIOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000U #define VIOAPIC_MEM_LENGTH 0x100 /* Direct registers. */ diff --git a/xen/arch/x86/include/asm/msi.h b/xen/arch/x86/include/asm/msi.h index a53ade95c9..d89723d009 100644 --- a/xen/arch/x86/include/asm/msi.h +++ b/xen/arch/x86/include/asm/msi.h @@ -37,7 +37,7 @@ */ #define MSI_ADDR_BASE_HI 0 -#define MSI_ADDR_BASE_LO 0xfee00000 +#define MSI_ADDR_BASE_LO 0xfee00000U #define MSI_ADDR_BASE_MASK (~0xfffff) #define MSI_ADDR_HEADER MSI_ADDR_BASE_LO diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 2749e433d2..7ed48d23cd 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -30,7 +30,7 @@ #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 #define MSR_CTC_THREAD_MASK 0x0000ffff -#define MSR_CTC_CORE_MASK 0xffff0000 +#define MSR_CTC_CORE_MASK 0xffff0000U #define MSR_SPEC_CTRL 0x00000048 #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) @@ -168,7 +168,7 @@ #define MSR_UARCH_MISC_CTRL 0x00001b01 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0) -#define MSR_EFER 0xc0000080 /* Extended Feature Enable Register */ +#define MSR_EFER 0xc0000080U /* Extended Feature Enable Register */ #define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */ #define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */ #define EFER_LMA (_AC(1, ULL) << 10) /* Long Mode Active */ @@ -181,35 +181,35 @@ (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \ EFER_AIBRSE) -#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ -#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ -#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ -#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ -#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ -#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ -#define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */ -#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ +#define MSR_STAR 0xc0000081U /* legacy mode SYSCALL target */ +#define MSR_LSTAR 0xc0000082U /* long mode SYSCALL target */ +#define MSR_CSTAR 0xc0000083U /* compat mode SYSCALL target */ +#define MSR_SYSCALL_MASK 0xc0000084U /* EFLAGS mask for syscall */ +#define MSR_FS_BASE 0xc0000100U /* 64bit FS base */ +#define MSR_GS_BASE 0xc0000101U /* 64bit GS base */ +#define MSR_SHADOW_GS_BASE 0xc0000102U /* SwapGS GS shadow */ +#define MSR_TSC_AUX 0xc0000103U /* Auxiliary TSC */ -#define MSR_K8_SYSCFG 0xc0010010 +#define MSR_K8_SYSCFG 0xc0010010U #define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18) #define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19) #define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20) #define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21) #define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22) -#define MSR_K8_IORR_BASE0 0xc0010016 -#define MSR_K8_IORR_MASK0 0xc0010017 -#define MSR_K8_IORR_BASE1 0xc0010018 -#define MSR_K8_IORR_MASK1 0xc0010019 +#define MSR_K8_IORR_BASE0 0xc0010016U +#define MSR_K8_IORR_MASK0 0xc0010017U +#define MSR_K8_IORR_BASE1 0xc0010018U +#define MSR_K8_IORR_MASK1 0xc0010019U -#define MSR_K8_TSEG_BASE 0xc0010112 /* AMD doc: SMMAddr */ -#define MSR_K8_TSEG_MASK 0xc0010113 /* AMD doc: SMMMask */ +#define MSR_K8_TSEG_BASE 0xc0010112U /* AMD doc: SMMAddr */ +#define MSR_K8_TSEG_MASK 0xc0010113U /* AMD doc: SMMMask */ -#define MSR_K8_VM_CR 0xc0010114 +#define MSR_K8_VM_CR 0xc0010114U #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1) #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4) -#define MSR_VIRT_SPEC_CTRL 0xc001011f /* Layout matches MSR_SPEC_CTRL */ +#define MSR_VIRT_SPEC_CTRL 0xc001011fU /* Layout matches MSR_SPEC_CTRL */ /* * Legacy MSR constants in need of cleanup. No new MSRs below this comment. @@ -293,7 +293,7 @@ #define CMCI_EN (1UL<<30) #define CMCI_THRESHOLD_MASK 0x7FFF -#define MSR_AMD64_MC0_MASK 0xc0010044 +#define MSR_AMD64_MC0_MASK 0xc0010044U #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) @@ -325,83 +325,83 @@ /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */ -#define MSR_K7_EVNTSEL0 0xc0010000 -#define MSR_K7_PERFCTR0 0xc0010004 -#define MSR_K7_EVNTSEL1 0xc0010001 -#define MSR_K7_PERFCTR1 0xc0010005 -#define MSR_K7_EVNTSEL2 0xc0010002 -#define MSR_K7_PERFCTR2 0xc0010006 -#define MSR_K7_EVNTSEL3 0xc0010003 -#define MSR_K7_PERFCTR3 0xc0010007 -#define MSR_K8_TOP_MEM1 0xc001001a -#define MSR_K7_CLK_CTL 0xc001001b -#define MSR_K8_TOP_MEM2 0xc001001d - -#define MSR_K8_HWCR 0xc0010015 +#define MSR_K7_EVNTSEL0 0xc0010000U +#define MSR_K7_PERFCTR0 0xc0010004U +#define MSR_K7_EVNTSEL1 0xc0010001U +#define MSR_K7_PERFCTR1 0xc0010005U +#define MSR_K7_EVNTSEL2 0xc0010002U +#define MSR_K7_PERFCTR2 0xc0010006U +#define MSR_K7_EVNTSEL3 0xc0010003U +#define MSR_K7_PERFCTR3 0xc0010007U +#define MSR_K8_TOP_MEM1 0xc001001aU +#define MSR_K7_CLK_CTL 0xc001001bU +#define MSR_K8_TOP_MEM2 0xc001001dU + +#define MSR_K8_HWCR 0xc0010015U #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24) #define K8_HWCR_CPUID_USER_DIS (1ULL << 35) -#define MSR_K7_FID_VID_CTL 0xc0010041 -#define MSR_K7_FID_VID_STATUS 0xc0010042 -#define MSR_K8_PSTATE_LIMIT 0xc0010061 -#define MSR_K8_PSTATE_CTRL 0xc0010062 -#define MSR_K8_PSTATE_STATUS 0xc0010063 -#define MSR_K8_PSTATE0 0xc0010064 -#define MSR_K8_PSTATE1 0xc0010065 -#define MSR_K8_PSTATE2 0xc0010066 -#define MSR_K8_PSTATE3 0xc0010067 -#define MSR_K8_PSTATE4 0xc0010068 -#define MSR_K8_PSTATE5 0xc0010069 -#define MSR_K8_PSTATE6 0xc001006A -#define MSR_K8_PSTATE7 0xc001006B -#define MSR_K8_ENABLE_C1E 0xc0010055 -#define MSR_K8_VM_HSAVE_PA 0xc0010117 - -#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200 -#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201 -#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202 -#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203 -#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204 -#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205 -#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206 -#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207 -#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208 -#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209 -#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020a -#define MSR_AMD_FAM15H_PERFCTR5 0xc001020b - -#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002 -#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003 -#define MSR_K8_FEATURE_MASK 0xc0011004 -#define MSR_K8_EXT_FEATURE_MASK 0xc0011005 +#define MSR_K7_FID_VID_CTL 0xc0010041U +#define MSR_K7_FID_VID_STATUS 0xc0010042U +#define MSR_K8_PSTATE_LIMIT 0xc0010061U +#define MSR_K8_PSTATE_CTRL 0xc0010062U +#define MSR_K8_PSTATE_STATUS 0xc0010063U +#define MSR_K8_PSTATE0 0xc0010064U +#define MSR_K8_PSTATE1 0xc0010065U +#define MSR_K8_PSTATE2 0xc0010066U +#define MSR_K8_PSTATE3 0xc0010067U +#define MSR_K8_PSTATE4 0xc0010068U +#define MSR_K8_PSTATE5 0xc0010069U +#define MSR_K8_PSTATE6 0xc001006AU +#define MSR_K8_PSTATE7 0xc001006BU +#define MSR_K8_ENABLE_C1E 0xc0010055U +#define MSR_K8_VM_HSAVE_PA 0xc0010117U + +#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200U +#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201U +#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202U +#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203U +#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204U +#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205U +#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206U +#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207U +#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208U +#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209U +#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020aU +#define MSR_AMD_FAM15H_PERFCTR5 0xc001020bU + +#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002U +#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003U +#define MSR_K8_FEATURE_MASK 0xc0011004U +#define MSR_K8_EXT_FEATURE_MASK 0xc0011005U /* AMD64 MSRs */ -#define MSR_AMD64_NB_CFG 0xc001001f +#define MSR_AMD64_NB_CFG 0xc001001fU #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 -#define MSR_AMD64_LS_CFG 0xc0011020 -#define MSR_AMD64_IC_CFG 0xc0011021 -#define MSR_AMD64_DC_CFG 0xc0011022 -#define MSR_AMD64_DE_CFG 0xc0011029 +#define MSR_AMD64_LS_CFG 0xc0011020U +#define MSR_AMD64_IC_CFG 0xc0011021U +#define MSR_AMD64_DC_CFG 0xc0011022U +#define MSR_AMD64_DE_CFG 0xc0011029U #define AMD64_DE_CFG_LFENCE_SERIALISE (_AC(1, ULL) << 1) -#define MSR_AMD64_EX_CFG 0xc001102c -#define MSR_AMD64_DE_CFG2 0xc00110e3 +#define MSR_AMD64_EX_CFG 0xc001102cU +#define MSR_AMD64_DE_CFG2 0xc00110e3U -#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027 -#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019 -#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101a -#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101b +#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027U +#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019U +#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101aU +#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101bU /* AMD Family10h machine check MSRs */ -#define MSR_F10_MC4_MISC1 0xc0000408 -#define MSR_F10_MC4_MISC2 0xc0000409 -#define MSR_F10_MC4_MISC3 0xc000040A +#define MSR_F10_MC4_MISC1 0xc0000408U +#define MSR_F10_MC4_MISC2 0xc0000409U +#define MSR_F10_MC4_MISC3 0xc000040AU /* AMD Family10h Bus Unit MSRs */ -#define MSR_F10_BU_CFG 0xc0011023 -#define MSR_F10_BU_CFG2 0xc001102a +#define MSR_F10_BU_CFG 0xc0011023U +#define MSR_F10_BU_CFG2 0xc001102aU /* Other AMD Fam10h MSRs */ -#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 +#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058U #define FAM10H_MMIO_CONF_ENABLE (1<<0) #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 @@ -410,31 +410,31 @@ /* AMD Microcode MSRs */ #define MSR_AMD_PATCHLEVEL 0x0000008b -#define MSR_AMD_PATCHLOADER 0xc0010020 +#define MSR_AMD_PATCHLOADER 0xc0010020U /* AMD TSC RATE MSR */ -#define MSR_AMD64_TSC_RATIO 0xc0000104 +#define MSR_AMD64_TSC_RATIO 0xc0000104U /* AMD Lightweight Profiling MSRs */ -#define MSR_AMD64_LWP_CFG 0xc0000105 -#define MSR_AMD64_LWP_CBADDR 0xc0000106 +#define MSR_AMD64_LWP_CFG 0xc0000105U +#define MSR_AMD64_LWP_CBADDR 0xc0000106U /* AMD OS Visible Workaround MSRs */ -#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140 -#define MSR_AMD_OSVW_STATUS 0xc0010141 +#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140U +#define MSR_AMD_OSVW_STATUS 0xc0010141U /* AMD Protected Processor Inventory Number */ -#define MSR_AMD_PPIN_CTL 0xc00102f0 -#define MSR_AMD_PPIN 0xc00102f1 +#define MSR_AMD_PPIN_CTL 0xc00102f0U +#define MSR_AMD_PPIN 0xc00102f1U /* K6 MSRs */ -#define MSR_K6_EFER 0xc0000080 -#define MSR_K6_STAR 0xc0000081 -#define MSR_K6_WHCR 0xc0000082 -#define MSR_K6_UWCCR 0xc0000085 -#define MSR_K6_EPMR 0xc0000086 -#define MSR_K6_PSOR 0xc0000087 -#define MSR_K6_PFIR 0xc0000088 +#define MSR_K6_EFER 0xc0000080U +#define MSR_K6_STAR 0xc0000081U +#define MSR_K6_WHCR 0xc0000082U +#define MSR_K6_UWCCR 0xc0000085U +#define MSR_K6_EPMR 0xc0000086U +#define MSR_K6_PSOR 0xc0000087U +#define MSR_K6_PFIR 0xc0000088U /* Centaur-Hauls/IDT defined MSRs. */ #define MSR_IDT_FCR1 0x00000107 @@ -459,10 +459,10 @@ #define MSR_VIA_BCR2 0x00001147 /* Transmeta defined MSRs */ -#define MSR_TMTA_LONGRUN_CTRL 0x80868010 -#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 -#define MSR_TMTA_LRTI_READOUT 0x80868018 -#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a +#define MSR_TMTA_LONGRUN_CTRL 0x80868010U +#define MSR_TMTA_LONGRUN_FLAGS 0x80868011U +#define MSR_TMTA_LRTI_READOUT 0x80868018U +#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801aU /* Intel defined MSRs. */ #define MSR_IA32_P5_MC_ADDR 0x00000000 diff --git a/xen/arch/x86/include/asm/pci.h b/xen/arch/x86/include/asm/pci.h index f4a58c8acf..e1dd12eb19 100644 --- a/xen/arch/x86/include/asm/pci.h +++ b/xen/arch/x86/include/asm/pci.h @@ -3,10 +3,10 @@ #include -#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00) >> 8) -#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fc) -#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000) >> 16) -#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000)) +#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00U) >> 8) +#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fcU) +#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000U) >> 16) +#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000U)) #define IS_SNB_GFX(id) (id == 0x01068086 || id == 0x01168086 \ || id == 0x01268086 || id == 0x01028086 \ diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h index e350227e57..87173abc70 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -30,17 +30,17 @@ /* * Intel CPU flags in CR0 */ -#define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */ -#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */ -#define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */ -#define X86_CR0_TS 0x00000008 /* Task Switched (RW) */ -#define X86_CR0_ET 0x00000010 /* Extension type (RO) */ -#define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */ -#define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */ -#define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */ -#define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */ -#define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */ -#define X86_CR0_PG 0x80000000 /* Paging (RW) */ +#define X86_CR0_PE 0x00000001U /* Enable Protected Mode (RW) */ +#define X86_CR0_MP 0x00000002U /* Monitor Coprocessor (RW) */ +#define X86_CR0_EM 0x00000004U /* Require FPU Emulation (RO) */ +#define X86_CR0_TS 0x00000008U /* Task Switched (RW) */ +#define X86_CR0_ET 0x00000010U /* Extension type (RO) */ +#define X86_CR0_NE 0x00000020U /* Numeric Error Reporting (RW) */ +#define X86_CR0_WP 0x00010000U /* Supervisor Write Protect (RW) */ +#define X86_CR0_AM 0x00040000U /* Alignment Checking (RW) */ +#define X86_CR0_NW 0x20000000U /* Not Write-Through (RW) */ +#define X86_CR0_CD 0x40000000U /* Cache Disable (RW) */ +#define X86_CR0_PG 0x80000000U /* Paging (RW) */ /* * Intel CPU flags in CR3 @@ -103,7 +103,7 @@ /* * Debug status flags in DR6. */ -#define X86_DR6_DEFAULT 0xffff0ff0 /* Default %dr6 value. */ +#define X86_DR6_DEFAULT 0xffff0ff0U /* Default %dr6 value. */ /* * Debug control flags in DR7. diff --git a/xen/arch/x86/percpu.c b/xen/arch/x86/percpu.c index 288050cdba..1ebeb65ad6 100644 --- a/xen/arch/x86/percpu.c +++ b/xen/arch/x86/percpu.c @@ -12,7 +12,7 @@ unsigned long __per_cpu_offset[NR_CPUS]; * possible #PF at (NULL + a little) which has security implications in the * context of PV guests. */ -#define INVALID_PERCPU_AREA (0x8000000000000000L - (long)__per_cpu_start) +#define INVALID_PERCPU_AREA (0x8000000000000000UL - (long)__per_cpu_start) #define PERCPU_ORDER get_order_from_bytes(__per_cpu_data_end - __per_cpu_start) void __init percpu_init_areas(void) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index a1e0af27c5..5581b4717a 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -191,7 +191,7 @@ static struct feat_node *feat_l2_cat; static struct feat_node *feat_mba; /* Common functions */ -#define cat_default_val(len) (0xffffffff >> (32 - (len))) +#define cat_default_val(len) (0xffffffffU >> (32 - (len))) /* * get_cdp_data - get DATA COS register value from input COS ID. diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 4081cef200..b030ad8a5b 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -398,8 +398,8 @@ static void __init print_details(enum ind_thunk thunk) cpuid_count(7, 0, &max, &tmp, &tmp, &_7d0); if ( max >= 2 ) cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2); - if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 ) - cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp); + if ( boot_cpu_data.extended_cpuid_level >= 0x80000008U ) + cpuid(0x80000008U, &tmp, &e8b, &tmp, &tmp); if ( cpu_has_arch_caps ) rdmsrl(MSR_ARCH_CAPABILITIES, caps); @@ -1337,8 +1337,8 @@ void __init init_speculation_mitigations(void) * TODO: Adjust cpu_has_svm_spec_ctrl to be usable earlier on boot. */ if ( opt_msr_sc_hvm && - (boot_cpu_data.extended_cpuid_level >= 0x8000000a) && - (cpuid_edx(0x8000000a) & (1u << SVM_FEATURE_SPEC_CTRL)) ) + (boot_cpu_data.extended_cpuid_level >= 0x8000000aU) && + (cpuid_edx(0x8000000aU) & (1u << SVM_FEATURE_SPEC_CTRL)) ) setup_force_cpu_cap(X86_FEATURE_SC_MSR_HVM); } diff --git a/xen/arch/x86/x86_64/acpi_mmcfg.c b/xen/arch/x86/x86_64/acpi_mmcfg.c index 2159c68189..cdde7e453c 100644 --- a/xen/arch/x86/x86_64/acpi_mmcfg.c +++ b/xen/arch/x86/x86_64/acpi_mmcfg.c @@ -50,7 +50,7 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, { int year; - if (cfg->address < 0xFFFFFFFF) + if (cfg->address < 0xFFFFFFFFU) return 0; if (!strncmp(mcfg->header.oem_id, "SGI", 3)) diff --git a/xen/arch/x86/x86_64/pci.c b/xen/arch/x86/x86_64/pci.c index aad1c3f7cf..8d33429103 100644 --- a/xen/arch/x86/x86_64/pci.c +++ b/xen/arch/x86/x86_64/pci.c @@ -9,7 +9,7 @@ #include #define PCI_CONF_ADDRESS(sbdf, reg) \ - (0x80000000 | ((sbdf).bdf << 8) | ((reg) & ~3)) + (0x80000000U | ((sbdf).bdf << 8) | ((reg) & ~3)) uint8_t pci_conf_read8(pci_sbdf_t sbdf, unsigned int reg) { diff --git a/xen/arch/x86/x86_emulate/x86_emulate.h b/xen/arch/x86/x86_emulate/x86_emulate.h index 40d5054fb7..ec6d93fb2f 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.h +++ b/xen/arch/x86/x86_emulate/x86_emulate.h @@ -620,7 +620,7 @@ struct x86_emulate_ctxt * below). * Hence no separate #define-s get added. */ -#define X86EMUL_OPC_EXT_MASK 0xffff0000 +#define X86EMUL_OPC_EXT_MASK 0xffff0000U #define X86EMUL_OPC(ext, byte) ((uint8_t)(byte) | \ MASK_INSR((ext), X86EMUL_OPC_EXT_MASK)) /* diff --git a/xen/include/public/arch-x86/xen-x86_64.h b/xen/include/public/arch-x86/xen-x86_64.h index 5d9035ed22..7ea579e5fb 100644 --- a/xen/include/public/arch-x86/xen-x86_64.h +++ b/xen/include/public/arch-x86/xen-x86_64.h @@ -53,10 +53,10 @@ #define FLAT_USER_SS32 FLAT_RING3_SS32 #define FLAT_USER_SS FLAT_USER_SS64 -#define __HYPERVISOR_VIRT_START 0xFFFF800000000000 -#define __HYPERVISOR_VIRT_END 0xFFFF880000000000 -#define __MACH2PHYS_VIRT_START 0xFFFF800000000000 -#define __MACH2PHYS_VIRT_END 0xFFFF804000000000 +#define __HYPERVISOR_VIRT_START 0xFFFF800000000000U +#define __HYPERVISOR_VIRT_END 0xFFFF880000000000U +#define __MACH2PHYS_VIRT_START 0xFFFF800000000000U +#define __MACH2PHYS_VIRT_END 0xFFFF804000000000U #ifndef HYPERVISOR_VIRT_START #define HYPERVISOR_VIRT_START xen_mk_ulong(__HYPERVISOR_VIRT_START) diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c index 07e5501914..a4ea579ebe 100644 --- a/xen/lib/x86/cpuid.c +++ b/xen/lib/x86/cpuid.c @@ -217,10 +217,10 @@ void x86_cpu_policy_fill_native(struct cpu_policy *p) } /* Extended leaves. */ - cpuid_leaf(0x80000000, &p->extd.raw[0]); + cpuid_leaf(0x80000000U, &p->extd.raw[0]); for ( i = 1; i <= MIN(p->extd.max_leaf & 0xffffU, ARRAY_SIZE(p->extd.raw) - 1); ++i ) - cpuid_leaf(0x80000000 + i, &p->extd.raw[i]); + cpuid_leaf(0x80000000U + i, &p->extd.raw[i]); /* Don't report leaves from possible lower level hypervisor, for now. */ p->hv_limit = 0; @@ -421,7 +421,7 @@ int x86_cpuid_copy_to_buffer(const struct cpu_policy *p, /* Extended leaves. */ for ( leaf = 0; leaf <= MIN(p->extd.max_leaf & 0xfffful, ARRAY_SIZE(p->extd.raw) - 1); ++leaf ) - COPY_LEAF(0x80000000 | leaf, XEN_CPUID_NO_SUBLEAF, &p->extd.raw[leaf]); + COPY_LEAF(0x80000000U | leaf, XEN_CPUID_NO_SUBLEAF, &p->extd.raw[leaf]); #undef COPY_LEAF @@ -521,7 +521,7 @@ int x86_cpuid_copy_from_buffer(struct cpu_policy *p, p->hv2_limit = l.a; break; - case 0x80000000 ... 0x80000000 + ARRAY_SIZE(p->extd.raw) - 1: + case 0x80000000U ... 0x80000000U + ARRAY_SIZE(p->extd.raw) - 1: if ( data.subleaf != XEN_CPUID_NO_SUBLEAF ) goto out_of_range; diff --git a/xen/lib/x86/policy.c b/xen/lib/x86/policy.c index a9c60000af..f033d22785 100644 --- a/xen/lib/x86/policy.c +++ b/xen/lib/x86/policy.c @@ -22,7 +22,7 @@ int x86_cpu_policies_are_compatible(const struct cpu_policy *host, FAIL_CPUID(7, 0); if ( guest->extd.max_leaf > host->extd.max_leaf ) - FAIL_CPUID(0x80000000, NA); + FAIL_CPUID(0x80000000U, NA); /* TODO: Audit more CPUID data. */ From patchwork Tue Jun 20 10:35:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13285641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBYi5-0004Ou-SI for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 10:35:41 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 33315939-0f56-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 12:35:39 +0200 (CEST) Received: from beta.bugseng.com (93-40-74-174.ip37.fastwebnet.it [93.40.74.174]) by support.bugseng.com (Postfix) with ESMTPSA id 272A74EE0752; Tue, 20 Jun 2023 12:35:38 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 33315939-0f56-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Michal Orzel , Xenia Ragiadakou , Ayan Kumar , Simone Ballarin Subject: [XEN PATCH 13/13] xen: fixed violations of MISRA C:2012 Rule 7.2 Date: Tue, 20 Jun 2023 12:35:05 +0200 Message-Id: <3560de5fd05a67cc10c9426ffd55639ebe24d98d.1687250177.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type". I propose to use "U" as a suffix to explicitly state when an integer constant is represented in an unsigned type. For homogeneity, I also added the "U" suffix in some cases that the tool didn't report as violations. Signed-off-by: Simone Ballarin --- xen/common/gunzip.c | 2 +- xen/common/xmalloc_tlsf.c | 2 +- xen/drivers/char/ehci-dbgp.c | 4 ++-- xen/include/public/memory.h | 2 +- xen/include/public/sysctl.h | 4 ++-- xen/include/xen/bitops.h | 10 +++++----- xen/include/xen/cper.h | 34 +++++++++++++++++----------------- xen/lib/muldiv64.c | 2 +- 8 files changed, 30 insertions(+), 30 deletions(-) diff --git a/xen/common/gunzip.c b/xen/common/gunzip.c index 71ec5f26be..b810499be2 100644 --- a/xen/common/gunzip.c +++ b/xen/common/gunzip.c @@ -11,7 +11,7 @@ static unsigned char *__initdata window; static memptr __initdata free_mem_ptr; static memptr __initdata free_mem_end_ptr; -#define WSIZE 0x80000000 +#define WSIZE 0x80000000U static unsigned char *__initdata inbuf; static unsigned int __initdata insize; diff --git a/xen/common/xmalloc_tlsf.c b/xen/common/xmalloc_tlsf.c index 75bdf18c4e..c21bf71e88 100644 --- a/xen/common/xmalloc_tlsf.c +++ b/xen/common/xmalloc_tlsf.c @@ -46,7 +46,7 @@ #define BHDR_OVERHEAD (sizeof(struct bhdr) - MIN_BLOCK_SIZE) #define PTR_MASK (sizeof(void *) - 1) -#define BLOCK_SIZE_MASK (0xFFFFFFFF - PTR_MASK) +#define BLOCK_SIZE_MASK (0xFFFFFFFFU - PTR_MASK) #define GET_NEXT_BLOCK(addr, r) ((struct bhdr *) \ ((char *)(addr) + (r))) diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c index bb9d3198d9..4d8d765122 100644 --- a/xen/drivers/char/ehci-dbgp.c +++ b/xen/drivers/char/ehci-dbgp.c @@ -375,12 +375,12 @@ static inline u32 dbgp_pid_write_update(u32 x, u32 tok) static u8 data0 = USB_PID_DATA1; data0 ^= USB_PID_DATA0 ^ USB_PID_DATA1; - return (x & 0xffff0000) | (data0 << 8) | (tok & 0xff); + return (x & 0xffff0000U) | (data0 << 8) | (tok & 0xffU); } static inline u32 dbgp_pid_read_update(u32 x, u32 tok) { - return (x & 0xffffff00) | (tok & 0xff); + return (x & 0xffffff00U) | (tok & 0xffU); } static inline void dbgp_set_data(struct ehci_dbg_port __iomem *ehci_debug, diff --git a/xen/include/public/memory.h b/xen/include/public/memory.h index c5f0d31e23..5e545ae9a4 100644 --- a/xen/include/public/memory.h +++ b/xen/include/public/memory.h @@ -234,7 +234,7 @@ struct xen_add_to_physmap { unsigned int space; /* => enum phys_map_space */ -#define XENMAPIDX_grant_table_status 0x80000000 +#define XENMAPIDX_grant_table_status 0x80000000U /* Index into space being mapped. */ xen_ulong_t idx; diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index 9d06e92d0f..4e8b087502 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -384,7 +384,7 @@ struct xen_sysctl_pm_op { struct xen_set_cpufreq_para set_para; uint64_aligned_t get_avgfreq; uint32_t set_sched_opt_smt; -#define XEN_SYSCTL_CX_UNLIMITED 0xffffffff +#define XEN_SYSCTL_CX_UNLIMITED 0xffffffffU uint32_t get_max_cstate; uint32_t set_max_cstate; } u; @@ -547,7 +547,7 @@ struct xen_sysctl_numainfo { #define XEN_SYSCTL_CPUPOOL_OP_RMCPU 5 /* R */ #define XEN_SYSCTL_CPUPOOL_OP_MOVEDOMAIN 6 /* M */ #define XEN_SYSCTL_CPUPOOL_OP_FREEINFO 7 /* F */ -#define XEN_SYSCTL_CPUPOOL_PAR_ANY 0xFFFFFFFF +#define XEN_SYSCTL_CPUPOOL_PAR_ANY 0xFFFFFFFFU struct xen_sysctl_cpupool_op { uint32_t op; /* IN */ uint32_t cpupool_id; /* IN: CDIARM OUT: CI */ diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index 33619a0873..3b7e09a26e 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -227,11 +227,11 @@ static inline __u32 ror32(__u32 word, unsigned int shift) } /* base-2 logarithm */ -#define __L2(_x) (((_x) & 0x00000002) ? 1 : 0) -#define __L4(_x) (((_x) & 0x0000000c) ? ( 2 + __L2( (_x)>> 2)) : __L2( _x)) -#define __L8(_x) (((_x) & 0x000000f0) ? ( 4 + __L4( (_x)>> 4)) : __L4( _x)) -#define __L16(_x) (((_x) & 0x0000ff00) ? ( 8 + __L8( (_x)>> 8)) : __L8( _x)) -#define ilog2(_x) (((_x) & 0xffff0000) ? (16 + __L16((_x)>>16)) : __L16(_x)) +#define __L2(_x) (((_x) & 0x00000002U) ? 1 : 0) +#define __L4(_x) (((_x) & 0x0000000cU) ? ( 2 + __L2( (_x)>> 2)) : __L2( _x)) +#define __L8(_x) (((_x) & 0x000000f0U) ? ( 4 + __L4( (_x)>> 4)) : __L4( _x)) +#define __L16(_x) (((_x) & 0x0000ff00U) ? ( 8 + __L8( (_x)>> 8)) : __L8( _x)) +#define ilog2(_x) (((_x) & 0xffff0000U) ? (16 + __L16((_x)>>16)) : __L16(_x)) /** * for_each_set_bit - iterate over every set bit in a memory region diff --git a/xen/include/xen/cper.h b/xen/include/xen/cper.h index f8e5272bc1..71d14faa02 100644 --- a/xen/include/xen/cper.h +++ b/xen/include/xen/cper.h @@ -56,7 +56,7 @@ static inline uint64_t cper_next_record_id(void) #define CPER_SIG_RECORD "CPER" #define CPER_SIG_SIZE 4 /* Used in signature_end field in struct cper_record_header */ -#define CPER_SIG_END 0xffffffff +#define CPER_SIG_END 0xffffffffU /* * CPER record header revision, used in revision field in struct @@ -80,36 +80,36 @@ static inline uint64_t cper_next_record_id(void) * Corrected Machine Check */ #define CPER_NOTIFY_CMC \ - UUID_LE(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \ - 0xEB, 0xD4, 0xF8, 0x90) + UUID_LE(0x2DCE8BB1U, 0xBDD7U, 0x450eU, 0xB9U, 0xADU, 0x9CU, 0xF4U, \ + 0xEBU, 0xD4U, 0xF8U, 0x90U) /* Corrected Platform Error */ #define CPER_NOTIFY_CPE \ - UUID_LE(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \ - 0xF2, 0x7E, 0xBE, 0xEE) + UUID_LE(0x4E292F96U, 0xD843U, 0x4a55U, 0xA8U, 0xC2U, 0xD4U, 0x81U, \ + 0xF2U, 0x7EU, 0xBEU, 0xEEU) /* Machine Check Exception */ #define CPER_NOTIFY_MCE \ - UUID_LE(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \ - 0xE1, 0x49, 0x13, 0xBB) + UUID_LE(0xE8F56FFEU, 0x919CU, 0x4cc5U, 0xBAU, 0x88U, 0x65U, 0xABU, \ + 0xE1U, 0x49U, 0x13U, 0xBBU) /* PCI Express Error */ #define CPER_NOTIFY_PCIE \ - UUID_LE(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \ - 0xAF, 0x67, 0xC1, 0x04) + UUID_LE(0xCF93C01FU, 0x1A16U, 0x4dfcU, 0xB8U, 0xBCU, 0x9CU, 0x4DU, \ + 0xAFU, 0x67U, 0xC1U, 0x04U) /* INIT Record (for IPF) */ #define CPER_NOTIFY_INIT \ - UUID_LE(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \ - 0xD3, 0x9B, 0xC9, 0x8E) + UUID_LE(0xCC5263E8U, 0x9308U, 0x454aU, 0x89U, 0xD0U, 0x34U, 0x0BU, \ + 0xD3U, 0x9BU, 0xC9U, 0x8EU) /* Non-Maskable Interrupt */ #define CPER_NOTIFY_NMI \ - UUID_LE(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \ - 0x85, 0xD6, 0xE9, 0x8A) + UUID_LE(0x5BAD89FFU, 0xB7E6U, 0x42c9U, 0x81U, 0x4AU, 0xCFU, 0x24U, \ + 0x85U, 0xD6U, 0xE9U, 0x8AU) /* BOOT Error Record */ #define CPER_NOTIFY_BOOT \ - UUID_LE(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \ - 0xD4, 0x64, 0xB3, 0x8F) + UUID_LE(0x3D61A466U, 0xAB40U, 0x409aU, 0xA6U, 0x98U, 0xF3U, 0x62U, \ + 0xD4U, 0x64U, 0xB3U, 0x8FU) /* DMA Remapping Error */ #define CPER_NOTIFY_DMAR \ - UUID_LE(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \ - 0x72, 0x2D, 0xEB, 0x41) + UUID_LE(0x667DD791U, 0xC6B3U, 0x4c27U, 0x8AU, 0x6BU, 0x0FU, 0x8EU, \ + 0x72U, 0x2DU, 0xEBU, 0x41U) /* * Flags bits definitions for flags in struct cper_record_header diff --git a/xen/lib/muldiv64.c b/xen/lib/muldiv64.c index 78177ce616..641ac25d01 100644 --- a/xen/lib/muldiv64.c +++ b/xen/lib/muldiv64.c @@ -27,7 +27,7 @@ uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) rh = (uint64_t)u.l.high * (uint64_t)b; rh += (rl >> 32); res.l.high = rh / c; - res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; + res.l.low = (((rh % c) << 32) + (rl & 0xffffffffU)) / c; return res.ll; #endif