From patchwork Wed Jun 21 01:00:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 13286529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08F1EEB64D7 for ; Wed, 21 Jun 2023 01:00:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=QWYsp78VlU7voHI92FcI7qsWibjT/aqEqD6Pl910aZ8=; b=2zyXJm6cYs/tx9 uewXXpYE8XmJgg01VH8H7GvTZoQ8vsVwq6R4l1PXFjKQENATQDBDfESNCuCPmwjv5WeY11pxrAbhJ hFir1SLs6OZbTgJtZfuyaDpGZtIhJ7B027GF7+jnew6rwF67idaUtndZKO/n8zQBabjK97OhxPt44 YAYtbNa6z9kX2xsNRRG/weboR9R5bfa+lScLsT0spVbQExAeTNXvwUM3p7OTEU5mBxbVzSQZ9hmk6 wfQsb3RvBS+NdJdtRlxRkXd27Go9JXzv2/J3+AeLBGI2OikLfTiSig/dKY0qsx8pS1YMcXSBc7Ndl 4CX+nSmU0q6nX2mB5ICQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qBmD1-00Cl88-2X; Wed, 21 Jun 2023 01:00:31 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qBmCy-00Cl7P-0n for linux-arm-kernel@lists.infradead.org; Wed, 21 Jun 2023 01:00:29 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 35L10O58038938; Tue, 20 Jun 2023 20:00:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1687309224; bh=8CDTcOmq/dQciFNG3eoxG8Ph7s1HxOKsVHuVKlcktQE=; h=From:To:CC:Subject:Date; b=I8moJvgk3m+uadKvEauDvdj0apwrvRk8YcjgUrotwwvJsm2H+aR5mOjA7gPN2HTWz MaTqpMX+cewpGsdasuT0LmfUMEPbJdo0eTIhiQcRfyxus8poN0PtwHWTZd3bJ9rxqa UD2T7slb5R5aaitQ6Vj1bo3HsKx2bznj2Woq7/Rc= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 35L10OlU109241 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Jun 2023 20:00:24 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 20 Jun 2023 20:00:23 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 20 Jun 2023 20:00:23 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 35L10Npr013278; Tue, 20 Jun 2023 20:00:23 -0500 From: Nishanth Menon To: Jassi Brar Subject: [PATCH] mailbox: ti-msgmgr: Fill non-message tx data fields with 0x0 Date: Tue, 20 Jun 2023 20:00:22 -0500 Message-ID: <20230621010022.240211-1-nm@ti.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230620_180028_431806_F65E0D6F X-CRM114-Status: GOOD ( 17.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , vigneshr@ti.com, d-gole@ti.com, praneeth@ti.com, linux-kernel@vger.kernel.org, afd@ti.com, Jassi Brar , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Sec proxy/message manager data buffer is 60 bytes with the last of the registers indicating transmission completion. This however poses a bit of a challenge. The backing memory for sec_proxy / message manager is regular memory, and all sec proxy does is to trigger a burst of all 60 bytes of data over to the target thread backing ring accelerator. It doesn't do a memory scrub when it moves data out in the burst. When we transmit multiple messages, remnants of previous message is also transmitted which results in some random data being set in TISCI fields of messages that have been expanded forward. The entire concept of backward compatibility hinges on the fact that the unused message fields remain 0x0 allowing for 0x0 value to be specially considered when backward compatibility of message extension is done. So, instead of just writing the completion register, we continue to fill the message buffer up with 0x0 (note: for partial message involving completion, we already do this). This allows us to scale and introduce ABI changes back also work with other boot stages that may have left data in the internal memory. While at this, be consistent and explicit with the data_reg pointer increment. Fixes: aace66b170ce ("mailbox: Introduce TI message manager driver") Signed-off-by: Nishanth Menon --- Test logs: K2 platforms: https://gist.github.com/nmenon/ee4198b0a5889e8beb068798d8a440e0 K3 platforms: https://gist.github.com/nmenon/f0a9e7bd814aa475c3d71d3ead944f02 Tests based on next-20230615 drivers/mailbox/ti-msgmgr.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index ddac423ac1a9..03048cbda525 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -430,14 +430,20 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) /* Ensure all unused data is 0 */ data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes)); writel(data_trail, data_reg); - data_reg++; + data_reg += sizeof(u32); } + /* * 'data_reg' indicates next register to write. If we did not already * write on tx complete reg(last reg), we must do so for transmit + * In addition, we also need to make sure all intermediate data + * registers(if any required), are reset to 0 for TISCI backward + * compatibility to be maintained. */ - if (data_reg <= qinst->queue_buff_end) - writel(0, qinst->queue_buff_end); + while (data_reg <= qinst->queue_buff_end) { + writel(0, data_reg); + data_reg += sizeof(u32); + } /* If we are in polled mode, wait for a response before proceeding */ if (ti_msgmgr_chan_has_polled_queue_rx(message->chan_rx))