From patchwork Thu Jun 22 04:19:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13288243 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E1961C02; Thu, 22 Jun 2023 04:19:58 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA42B10CE; Wed, 21 Jun 2023 21:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687407596; x=1718943596; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UtwbdSn3PxBMhABoZLMkSt6Wfnm48v4gql/S1jq6XPg=; b=WFSKNX3PIbuGIYpNud4Pq7ujruS71JAs/eyB+UvOBByu4QIhb/Al0KPl Qgdt9uIrpxymD7gnjwdPf/doe3O47q/cwa+kinzr9rxj4KGjRiiqoC/PX 4gFOr1Gl6HiO8rd3TJxdEpEwef/4aPG44QWrJ0gpc6kA1eEmMSs+WNXQv 4eGh97zMbVK9hqTteXolHUB8hSRzMVafSh+mOouGO1l6dMjq1uZDe6HcS 0/m0sNHgiGi5TLKo2cgepX/Qnd7AL3Z5mFRDmDvC+uo2Js+oQ3YifpWQj aOwh1A1cDTtuKIUGwersWeWN6hTidwE3itfdXSrRAWIOQGAQCkJ/rLbny w==; X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="363811776" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="363811776" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2023 21:19:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="744453742" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="744453742" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.229.33]) by orsmga008.jf.intel.com with ESMTP; 21 Jun 2023 21:19:44 -0700 From: Choong Yong Liang To: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan, Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann Subject: [PATCH net-next 1/6] platform/x86: intel_pmc_core: Add IPC mailbox accessor function and add SoC register access Date: Thu, 22 Jun 2023 12:19:00 +0800 Message-Id: <20230622041905.629430-2-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> References: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org From: "David E. Box" - Exports intel_pmc_core_ipc() for host access to the PMC IPC mailbox - Add support to use IPC command allows host to access SoC registers through PMC firmware that are otherwise inaccessible to the host due to security policies. Signed-off-by: David E. Box Signed-off-by: Chao Qin Signed-off-by: Choong Yong Liang --- MAINTAINERS | 1 + drivers/platform/x86/intel/pmc/adl.c | 2 +- drivers/platform/x86/intel/pmc/cnp.c | 2 +- drivers/platform/x86/intel/pmc/core.c | 63 ++++++++++++++++++- drivers/platform/x86/intel/pmc/icl.c | 2 +- drivers/platform/x86/intel/pmc/mtl.c | 2 +- drivers/platform/x86/intel/pmc/spt.c | 2 +- drivers/platform/x86/intel/pmc/tgl.c | 2 +- .../core.h => include/linux/intel_pmc_core.h | 27 +++++++- 9 files changed, 95 insertions(+), 8 deletions(-) rename drivers/platform/x86/intel/pmc/core.h => include/linux/intel_pmc_core.h (95%) diff --git a/MAINTAINERS b/MAINTAINERS index cb14589d14ab..bdb08a79a5f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10581,6 +10581,7 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-platform-intel-pmc F: drivers/platform/x86/intel/pmc/ +F: include/linux/intel_pmc_core* INTEL PMIC GPIO DRIVERS M: Andy Shevchenko diff --git a/drivers/platform/x86/intel/pmc/adl.c b/drivers/platform/x86/intel/pmc/adl.c index 5cbd40979f2a..b6a376c536c0 100644 --- a/drivers/platform/x86/intel/pmc/adl.c +++ b/drivers/platform/x86/intel/pmc/adl.c @@ -8,7 +8,7 @@ * */ -#include "core.h" +#include /* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */ const struct pmc_bit_map adl_pfear_map[] = { diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/intel/pmc/cnp.c index 7fb38815c4eb..504034cc5ec3 100644 --- a/drivers/platform/x86/intel/pmc/cnp.c +++ b/drivers/platform/x86/intel/pmc/cnp.c @@ -8,7 +8,7 @@ * */ -#include "core.h" +#include /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */ const struct pmc_bit_map cnp_pfear_map[] = { diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index da6e7206d38b..0d60763c5144 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -26,7 +27,9 @@ #include #include -#include "core.h" +#define PMC_IPCS_PARAM_COUNT 7 + +static const struct x86_cpu_id *pmc_cpu_id; /* Maximum number of modes supported by platfoms that has low power mode capability */ const char *pmc_lpm_modes[] = { @@ -53,6 +56,63 @@ const struct pmc_bit_map msr_map[] = { {} }; +int intel_pmc_core_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf) +{ + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object params[PMC_IPCS_PARAM_COUNT] = { + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + }; + struct acpi_object_list arg_list = { PMC_IPCS_PARAM_COUNT, params }; + union acpi_object *obj; + int status; + + if (!pmc_cpu_id || !ipc_cmd || !rbuf) + return -EINVAL; + + /* + * 0: IPC Command + * 1: IPC Sub Command + * 2: Size + * 3-6: Write Buffer for offset + */ + params[0].integer.value = ipc_cmd->cmd; + params[1].integer.value = ipc_cmd->sub_cmd; + params[2].integer.value = ipc_cmd->size; + params[3].integer.value = ipc_cmd->wbuf[0]; + params[4].integer.value = ipc_cmd->wbuf[1]; + params[5].integer.value = ipc_cmd->wbuf[2]; + params[6].integer.value = ipc_cmd->wbuf[3]; + + status = acpi_evaluate_object(NULL, "\\IPCS", &arg_list, &buffer); + if (ACPI_FAILURE(status)) + return -ENODEV; + + obj = buffer.pointer; + /* Check if the number of elements in package is 5 */ + if (obj && obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) { + const union acpi_object *objs = obj->package.elements; + + if ((u8)objs[0].integer.value != 0) + return -EINVAL; + + rbuf[0] = objs[1].integer.value; + rbuf[1] = objs[2].integer.value; + rbuf[2] = objs[3].integer.value; + rbuf[3] = objs[4].integer.value; + } else { + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(intel_pmc_core_ipc); + static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) { return readl(pmcdev->regbase + reg_offset); @@ -1130,6 +1190,7 @@ static int pmc_core_probe(struct platform_device *pdev) mutex_init(&pmcdev->lock); core_init(pmcdev); + pmc_cpu_id = cpu_id; if (lpit_read_residency_count_address(&slp_s0_addr)) { pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; diff --git a/drivers/platform/x86/intel/pmc/icl.c b/drivers/platform/x86/intel/pmc/icl.c index 2f11b1a6daeb..f18048ff9382 100644 --- a/drivers/platform/x86/intel/pmc/icl.c +++ b/drivers/platform/x86/intel/pmc/icl.c @@ -8,7 +8,7 @@ * */ -#include "core.h" +#include const struct pmc_bit_map icl_pfear_map[] = { {"RES_65", BIT(0)}, diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c index e8cc156412ce..7897f5fe9881 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -9,7 +9,7 @@ */ #include -#include "core.h" +#include const struct pmc_reg_map mtl_reg_map = { .pfear_sts = ext_tgl_pfear_map, diff --git a/drivers/platform/x86/intel/pmc/spt.c b/drivers/platform/x86/intel/pmc/spt.c index e16982236778..95ce490cf5d6 100644 --- a/drivers/platform/x86/intel/pmc/spt.c +++ b/drivers/platform/x86/intel/pmc/spt.c @@ -8,7 +8,7 @@ * */ -#include "core.h" +#include const struct pmc_bit_map spt_pll_map[] = { {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0}, diff --git a/drivers/platform/x86/intel/pmc/tgl.c b/drivers/platform/x86/intel/pmc/tgl.c index c245ada849d0..a1719d809497 100644 --- a/drivers/platform/x86/intel/pmc/tgl.c +++ b/drivers/platform/x86/intel/pmc/tgl.c @@ -8,7 +8,7 @@ * */ -#include "core.h" +#include #define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972" #define ACPI_GET_LOW_MODE_REGISTERS 1 diff --git a/drivers/platform/x86/intel/pmc/core.h b/include/linux/intel_pmc_core.h similarity index 95% rename from drivers/platform/x86/intel/pmc/core.h rename to include/linux/intel_pmc_core.h index 9ca9b9746719..82810e8b92a2 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/include/linux/intel_pmc_core.h @@ -250,7 +250,16 @@ enum ppfear_regs { #define MTL_LPM_STATUS_OFFSET 0x1700 #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C -extern const char *pmc_lpm_modes[]; +#define IPC_SOC_REGISTER_ACCESS 0xAA +#define IPC_SOC_SUB_CMD_READ 0x00 +#define IPC_SOC_SUB_CMD_WRITE 0x01 + +struct pmc_ipc_cmd { + u32 cmd; + u32 sub_cmd; + u32 size; + u32 wbuf[4]; +}; struct pmc_bit_map { const char *name; @@ -427,4 +436,20 @@ static const struct file_operations __name ## _fops = { \ .release = single_release, \ } +#if IS_ENABLED(CONFIG_INTEL_PMC_CORE) +/** + * intel_pmc_core_ipc() - PMC IPC Mailbox accessor + * @ipc_cmd: struct pmc_ipc_cmd prepared with input to send + * @rbuf: Allocated u32[4] array for returned IPC data + * + * Return: 0 on success. Non-zero on mailbox error + */ +int intel_pmc_core_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf); +#else +static inline int intel_pmc_core_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf) +{ + return -ENODEV; +} +#endif /* CONFIG_INTEL_PMC_CORE */ + #endif /* PMC_CORE_H */ From patchwork Thu Jun 22 04:19:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13288244 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A4603C25; Thu, 22 Jun 2023 04:20:12 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D419A1BD8; Wed, 21 Jun 2023 21:20:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687407609; x=1718943609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zyt+QXbWH/hEYQv+Zq2xXU3qTdjhA8YElygEXrQATwQ=; b=hhkgdl2KdZiUvDsqxO+DzfbCt1zovhMXqQrpKgs0iKTOcQZOi4YkkmsM 0/85e82R04SgABWOtExL0y+PJGLAQXp2WadaVgYd9LIbyONdohY16jBI5 5JaYUC83Mn06jo+OEkIFo08eTgqwjrkUMsUwzR1cEc0c4aHduC91Vs2LQ RYsFcDCH2bR7GL0NJagsti02nVB6Wndfn+bbqnEyNTd810z4WwiYyNLOH rMmEfjbSGDCMv6Sr70OxBb1JID5BeWYtP9sRyVGFrg3qUZjmGdWDKRV38 B3qrSI5SmnaOoW0nIURpKPEmI8uks9dzaqzg9kppc9Zl3v8PAiv6UadzT Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="363811835" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="363811835" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2023 21:20:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="744453777" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="744453777" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.229.33]) by orsmga008.jf.intel.com with ESMTP; 21 Jun 2023 21:19:57 -0700 From: Choong Yong Liang To: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan, Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann Subject: [PATCH net-next 2/6] net: pcs: xpcs: combine C37 SGMII AN and 2500BASEX for Intel mGbE controller Date: Thu, 22 Jun 2023 12:19:01 +0800 Message-Id: <20230622041905.629430-3-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> References: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org From: "Tan, Tee Min" This commit introduces xpcs_sgmii_2500basex_features[] that combine xpcs_sgmii_features[] and xpcs_2500basex_features[] for Intel mGbE controller that desire to interchange the speed mode of 10/100/1000/2500Mbps at runtime. Also, we introduce xpcs_config_aneg_c37_sgmii_2500basex() function which is called by the xpcs_do_config() with the new AN mode: DW_SGMII_2500BASEX, and this new function will proceed next-level calling to perform C37 SGMII AN/2500BASEX configuration based on the PHY interface updated by PHY driver. Signed-off-by: Tan, Tee Min Signed-off-by: Choong Yong Liang --- drivers/net/pcs/pcs-xpcs.c | 72 ++++++++++++++++++++++++++++++------ include/linux/pcs/pcs-xpcs.h | 1 + 2 files changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index e4e59aa9faf7..cd1dc09c422f 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -104,6 +104,21 @@ static const int xpcs_2500basex_features[] = { __ETHTOOL_LINK_MODE_MASK_NBITS, }; +static const int xpcs_sgmii_2500basex_features[] = { + ETHTOOL_LINK_MODE_Pause_BIT, + ETHTOOL_LINK_MODE_Asym_Pause_BIT, + ETHTOOL_LINK_MODE_Autoneg_BIT, + ETHTOOL_LINK_MODE_10baseT_Half_BIT, + ETHTOOL_LINK_MODE_10baseT_Full_BIT, + ETHTOOL_LINK_MODE_100baseT_Half_BIT, + ETHTOOL_LINK_MODE_100baseT_Full_BIT, + ETHTOOL_LINK_MODE_1000baseT_Half_BIT, + ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + ETHTOOL_LINK_MODE_2500baseX_Full_BIT, + ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + __ETHTOOL_LINK_MODE_MASK_NBITS, +}; + static const phy_interface_t xpcs_usxgmii_interfaces[] = { PHY_INTERFACE_MODE_USXGMII, }; @@ -133,6 +148,12 @@ static const phy_interface_t xpcs_2500basex_interfaces[] = { PHY_INTERFACE_MODE_MAX, }; +static const phy_interface_t xpcs_sgmii_2500basex_interfaces[] = { + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_2500BASEX, + PHY_INTERFACE_MODE_MAX, +}; + enum { DW_XPCS_USXGMII, DW_XPCS_10GKR, @@ -141,6 +162,7 @@ enum { DW_XPCS_SGMII, DW_XPCS_1000BASEX, DW_XPCS_2500BASEX, + DW_XPCS_SGMII_2500BASEX, DW_XPCS_INTERFACE_MAX, }; @@ -267,6 +289,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs, case DW_AN_C37_SGMII: case DW_2500BASEX: case DW_AN_C37_1000BASEX: + case DW_SGMII_2500BASEX: dev = MDIO_MMD_VEND2; break; default: @@ -712,6 +735,8 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode) else ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; + /* Disable 2.5G GMII for SGMII C37 mode */ + ret &= ~DW_VR_MII_DIG_CTRL1_2G5_EN; ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); if (ret < 0) return ret; @@ -807,6 +832,26 @@ static int xpcs_config_2500basex(struct dw_xpcs *xpcs) return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret); } +static int xpcs_config_aneg_c37_sgmii_2500basex(struct dw_xpcs *xpcs, + unsigned int mode, + phy_interface_t interface) +{ + int ret = -EOPNOTSUPP; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + ret = xpcs_config_aneg_c37_sgmii(xpcs, mode); + break; + case PHY_INTERFACE_MODE_2500BASEX: + ret = xpcs_config_2500basex(xpcs); + break; + default: + break; + } + + return ret; +} + int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, unsigned int mode, const unsigned long *advertising) { @@ -843,6 +888,12 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, if (ret) return ret; break; + case DW_SGMII_2500BASEX: + ret = xpcs_config_aneg_c37_sgmii_2500basex(xpcs, mode, + interface); + if (ret) + return ret; + break; default: return -1; } @@ -1028,6 +1079,11 @@ static void xpcs_get_state(struct phylink_pcs *pcs, } break; case DW_AN_C37_SGMII: + case DW_SGMII_2500BASEX: + /* 2500BASEX is not supported for in-band AN mode. */ + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) + break; + ret = xpcs_get_state_c37_sgmii(xpcs, state); if (ret) { pr_err("xpcs_get_state_c37_sgmii returned %pe\n", @@ -1180,23 +1236,17 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { .num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces), .an_mode = DW_10GBASER, }, - [DW_XPCS_SGMII] = { - .supported = xpcs_sgmii_features, - .interface = xpcs_sgmii_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), - .an_mode = DW_AN_C37_SGMII, - }, [DW_XPCS_1000BASEX] = { .supported = xpcs_1000basex_features, .interface = xpcs_1000basex_interfaces, .num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces), .an_mode = DW_AN_C37_1000BASEX, }, - [DW_XPCS_2500BASEX] = { - .supported = xpcs_2500basex_features, - .interface = xpcs_2500basex_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces), - .an_mode = DW_2500BASEX, + [DW_XPCS_SGMII_2500BASEX] = { + .supported = xpcs_sgmii_2500basex_features, + .interface = xpcs_sgmii_2500basex_interfaces, + .num_interfaces = ARRAY_SIZE(xpcs_sgmii_2500basex_features), + .an_mode = DW_SGMII_2500BASEX, }, }; diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h index ec8175b847cc..3e2265ca9e22 100644 --- a/include/linux/pcs/pcs-xpcs.h +++ b/include/linux/pcs/pcs-xpcs.h @@ -19,6 +19,7 @@ #define DW_2500BASEX 3 #define DW_AN_C37_1000BASEX 4 #define DW_10GBASER 5 +#define DW_SGMII_2500BASEX 6 struct xpcs_id; From patchwork Thu Jun 22 04:19:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13288245 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 899271C26; Thu, 22 Jun 2023 04:20:28 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCD281BD8; Wed, 21 Jun 2023 21:20:20 -0700 (PDT) DKIM-Signature: v=1; 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d="scan'208";a="744453782" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.229.33]) by orsmga008.jf.intel.com with ESMTP; 21 Jun 2023 21:20:08 -0700 From: Choong Yong Liang To: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan, Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann Subject: [PATCH net-next 3/6] net: phy: update in-band AN mode when changing interface by PHY driver Date: Thu, 22 Jun 2023 12:19:02 +0800 Message-Id: <20230622041905.629430-4-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> References: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org From: "Tan, Tee Min" Add cur_link_an_mode into phy_device struct for PHY drivers to communicate the in-band AN mode setting with phylink framework. As there is a mechanism in PHY drivers to switch the PHY interface between SGMII and 2500BaseX according to link speed. In this case, the in-band AN mode should be switching based on the PHY interface as well, if the PHY interface has been changed/updated by PHY driver. For e.g., disable in-band AN in 2500BaseX mode, or enable in-band AN back for SGMII mode (10/100/1000Mbps). Signed-off-by: Tan, Tee Min Signed-off-by: Choong Yong Liang --- drivers/net/phy/marvell10g.c | 6 ++++++ drivers/net/phy/phylink.c | 3 +++ include/linux/phy.h | 2 ++ 3 files changed, 11 insertions(+) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 55d9d7acc32e..5cf26d02841d 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -30,6 +30,7 @@ #include #include #include +#include #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) @@ -939,6 +940,9 @@ static void mv3310_update_interface(struct phy_device *phydev) * xaui / rxaui modes according to the speed. * Florian suggests setting phydev->interface to communicate this to the * MAC. Only do this if we are already in one of the above modes. + * In-band Auto-negotiation is not supported in 2500BASE-X. + * Setting phydev->cur_link_an_mode to communicate this to the + * phylink framework. */ switch (phydev->speed) { case SPEED_10000: @@ -949,11 +953,13 @@ static void mv3310_update_interface(struct phy_device *phydev) break; case SPEED_2500: phydev->interface = PHY_INTERFACE_MODE_2500BASEX; + phydev->cur_link_an_mode = MLO_AN_PHY; break; case SPEED_1000: case SPEED_100: case SPEED_10: phydev->interface = PHY_INTERFACE_MODE_SGMII; + phydev->cur_link_an_mode = MLO_AN_INBAND; break; default: break; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 97c15e1f81de..d5783ea95eee 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1654,6 +1654,7 @@ static void phylink_phy_change(struct phy_device *phydev, bool up) pl->phy_state.pause |= MLO_PAUSE_RX; pl->phy_state.interface = phydev->interface; pl->phy_state.link = up; + pl->cur_link_an_mode = phydev->cur_link_an_mode; mutex_unlock(&pl->state_mutex); phylink_run_resolve(pl); @@ -1758,6 +1759,8 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, if (pl->config->mac_managed_pm) phy->mac_managed_pm = true; + pl->phydev->cur_link_an_mode = pl->cur_link_an_mode; + return 0; } diff --git a/include/linux/phy.h b/include/linux/phy.h index 11c1e91563d4..c685b526e307 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -756,6 +756,8 @@ struct phy_device { /* MACsec management functions */ const struct macsec_ops *macsec_ops; #endif + /* For communicate the AN mode setting with phylink framework. */ + u8 cur_link_an_mode; }; /* Generic phy_device::dev_flags */ From patchwork Thu Jun 22 04:19:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13288246 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 256191C26; Thu, 22 Jun 2023 04:20:42 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BBA2170C; Wed, 21 Jun 2023 21:20:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687407634; x=1718943634; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Tt65fYS/ySYaWl/beLbEIOU2XnLdO5QJ0FnXNMR9KLs=; b=VM4OkZhxIa0vOQIdkALnSIc9mvPpD6rJzvDho/KZWs/uPwGNYnqwWlMb QQbTAkHON8IqRMIsfLoDVfiSaOFY+PCAa5DGTb9T39jM3LpeaWY21LHnX OLa+gIetzPMz6ar7BtZGYiUTJqp82Od7VmPFPEpJhojj63SSezEsLYdHx WoFkNRaAirjHULf2wYBhkuHmk6PQsB4VTgugjRhuvrfQCTR43o4T4M0KU 5a97wnupQqdoZP19EHd/fvfoGp/tF/1h1OQRuZTz0NX6J93vdsEZoA+DU rQ2EDqbMXRPA26wGzGxoBQOjamHWBbXGYt7IJ6ZVZ3CL+Ba8nbze0/Gh/ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="363812057" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="363812057" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2023 21:20:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="744453789" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="744453789" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.229.33]) by orsmga008.jf.intel.com with ESMTP; 21 Jun 2023 21:20:21 -0700 From: Choong Yong Liang To: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan, Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann Subject: [PATCH net-next 4/6] net: stmmac: enable Intel mGbE 1G/2.5G auto-negotiation support Date: Thu, 22 Jun 2023 12:19:03 +0800 Message-Id: <20230622041905.629430-5-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> References: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org From: "Tan, Tee Min" Initially, Intel mGbE was only able to configure the overclocking of 2.5 times clock rate to enable 2.5Gbps in the BIOS during boot time. Kernel driver had no access to modify the clock rate for 1G/2.5G mode at runtime. Now, this patch enables the runtime 1G/2.5G auto-negotiation support to gets rid of the dependency on BIOS to change the 1G/2.5G clock rate. This patch adds several new functions below:- - intel_tsn_interface_is_available(): This new function reads FIA lane ownership registers and common lane registers through IPC commands to know which lane the mGbE port is assigned to. - stmmac_mac_prepare(): To obtain the latest PHY interface from phylink during initialization and call intel_config_serdes() to proceed with SERDES configuration. - intel_config_serdes(): To configure the SERDES based on the assigned lane and latest PHY interface, it sends IPC command to the PMC through PMC driver/API. The PMC acts as a proxy for R/W on behalf of the driver. - intel_set_reg_access(): Set the register access to the available TSN interface. Signed-off-by: Tan, Tee Min Signed-off-by: Choong Yong Liang --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 134 +++++++++++++++++- .../net/ethernet/stmicro/stmmac/dwmac-intel.h | 79 +++++++++++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 20 +++ include/linux/stmmac.h | 1 + 5 files changed, 231 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 5583f0b055ec..f7d900b8946e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -273,6 +273,7 @@ config DWMAC_INTEL default X86 depends on X86 && STMMAC_ETH && PCI depends on COMMON_CLK + select INTEL_PMC_CORE help This selects the Intel platform specific bus support for the stmmac driver. This driver is used for Intel Quark/EHL/TGL. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index ab9f876b6df7..36c91dcb7a78 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "dwmac-intel.h" #include "dwmac4.h" #include "stmmac.h" @@ -14,6 +15,9 @@ struct intel_priv_data { int mdio_adhoc_addr; /* mdio address for serdes & etc */ unsigned long crossts_adj; bool is_pse; + const int *tsn_lane_registers; + int max_tsn_lane_registers; + int pid_modphy; }; /* This struct is used to associate PCI Function of MAC controller on a board, @@ -93,7 +97,7 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) data &= ~SERDES_RATE_MASK; data &= ~SERDES_PCLK_MASK; - if (priv->plat->max_speed == 2500) + if (priv->plat->phy_interface == PHY_INTERFACE_MODE_2500BASEX) data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; else @@ -415,6 +419,106 @@ static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv, } } +#if IS_ENABLED(CONFIG_INTEL_PMC_CORE) +static bool intel_tsn_interface_is_available(struct net_device *ndev, + struct intel_priv_data *intel_priv) +{ + struct stmmac_priv *priv = netdev_priv(ndev); + struct pmc_ipc_cmd tmp = {0}; + u32 rbuf[4] = {0}; + int ret, i, j; + + if (priv->plat->serdes_powerup) { + tmp.cmd = IPC_SOC_REGISTER_ACCESS; + tmp.sub_cmd = IPC_SOC_SUB_CMD_READ; + + for (i = 0; i < 5; i++) { + tmp.wbuf[0] = R_PCH_FIA_15_PCR_LOS1_REG_BASE + i; + + ret = intel_pmc_core_ipc(&tmp, rbuf); + if (ret < 0) { + netdev_info(priv->dev, + "Failed to read from PMC.\n"); + return false; + } + + for (j = 0; j <= intel_priv->max_tsn_lane_registers; j++) + if ((rbuf[0] >> + (4 * (intel_priv->tsn_lane_registers[j] % 8)) & + B_PCH_FIA_PCR_L0O) == 0xB) + return true; + } + } + return false; +} + +static int intel_set_reg_access(const struct pmc_serdes_regs *regs, int max_regs) +{ + int ret = 0, i; + + for (i = 0; i < max_regs; i++) { + struct pmc_ipc_cmd tmp = {0}; + u32 buf[4] = {0}; + + tmp.cmd = IPC_SOC_REGISTER_ACCESS; + tmp.sub_cmd = IPC_SOC_SUB_CMD_WRITE; + tmp.wbuf[0] = (u32)regs[i].index; + tmp.wbuf[1] = regs[i].val; + + ret = intel_pmc_core_ipc(&tmp, buf); + if (ret < 0) + return ret; + } + + return ret; +} + +static int intel_config_serdes(struct net_device *ndev, void *intel_data) +{ + struct intel_priv_data *intel_priv = intel_data; + struct stmmac_priv *priv = netdev_priv(ndev); + int ret = 0; + + if (!intel_tsn_interface_is_available(ndev, intel_priv)) { + netdev_info(priv->dev, + "No TSN interface available to set the registers.\n"); + goto pmc_read_error; + } + + if (intel_priv->pid_modphy == PID_MODPHY1) { + if (priv->plat->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + ret = intel_set_reg_access(pid_modphy1_2p5g_regs, + ARRAY_SIZE(pid_modphy1_2p5g_regs)); + } else { + ret = intel_set_reg_access(pid_modphy1_1g_regs, + ARRAY_SIZE(pid_modphy1_1g_regs)); + } + } else { + if (priv->plat->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + ret = intel_set_reg_access(pid_modphy3_2p5g_regs, + ARRAY_SIZE(pid_modphy3_2p5g_regs)); + } else { + ret = intel_set_reg_access(pid_modphy3_1g_regs, + ARRAY_SIZE(pid_modphy3_1g_regs)); + } + } + + if (ret < 0) + goto pmc_read_error; + +pmc_read_error: + intel_serdes_powerdown(ndev, intel_priv); + intel_serdes_powerup(ndev, intel_priv); + + return ret; +} +#else +static int intel_config_serdes(struct net_device *ndev, void *intel_data) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_INTEL_PMC_CORE */ + static void common_default_data(struct plat_stmmacenet_data *plat) { plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ @@ -626,6 +730,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, static int ehl_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->rx_queues_to_use = 8; plat->tx_queues_to_use = 8; plat->use_phy_wol = 1; @@ -640,20 +746,28 @@ static int ehl_common_data(struct pci_dev *pdev, plat->safety_feat_cfg->prtyen = 0; plat->safety_feat_cfg->tmouten = 0; + intel_priv->tsn_lane_registers = ehl_tsn_lane_registers; + intel_priv->max_tsn_lane_registers = ARRAY_SIZE(ehl_tsn_lane_registers); + return intel_mgbe_common_data(pdev, plat); } static int ehl_sgmii_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->bus_id = 1; plat->phy_interface = PHY_INTERFACE_MODE_SGMII; - plat->speed_mode_2500 = intel_speed_mode_2500; + plat->max_speed = SPEED_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; + plat->config_serdes = intel_config_serdes; plat->clk_ptp_rate = 204800000; + intel_priv->pid_modphy = PID_MODPHY3; + return ehl_common_data(pdev, plat); } @@ -706,10 +820,16 @@ static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->phy_interface = PHY_INTERFACE_MODE_SGMII; - plat->speed_mode_2500 = intel_speed_mode_2500; + plat->max_speed = SPEED_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; + plat->config_serdes = intel_config_serdes; + + intel_priv->pid_modphy = PID_MODPHY1; + return ehl_pse0_common_data(pdev, plat); } @@ -747,10 +867,16 @@ static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->phy_interface = PHY_INTERFACE_MODE_SGMII; - plat->speed_mode_2500 = intel_speed_mode_2500; + plat->max_speed = SPEED_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; + plat->config_serdes = intel_config_serdes; + + intel_priv->pid_modphy = PID_MODPHY1; + return ehl_pse1_common_data(pdev, plat); } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index 0a37987478c1..75a336cf8af1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -50,4 +50,83 @@ #define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0) #define PCH_PTP_CLK_FREQ_200MHZ (0) +#define PID_MODPHY1 0xAA +#define PID_MODPHY3 0xA8 + +#if IS_ENABLED(CONFIG_INTEL_PMC_CORE) +struct pmc_serdes_regs { + u8 index; + u32 val; +}; + +/* Modphy Register index */ +#define R_PCH_FIA_15_PCR_LOS1_REG_BASE 8 +#define R_PCH_FIA_15_PCR_LOS2_REG_BASE 9 +#define R_PCH_FIA_15_PCR_LOS3_REG_BASE 10 +#define R_PCH_FIA_15_PCR_LOS4_REG_BASE 11 +#define R_PCH_FIA_15_PCR_LOS5_REG_BASE 12 +#define B_PCH_FIA_PCR_L0O GENMASK(3, 0) +#define PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0 13 +#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2 14 +#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7 15 +#define PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10 16 +#define PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30 17 +#define PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0 18 +#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2 19 +#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7 20 +#define PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10 21 +#define PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30 22 + +#define B_MODPHY_PCR_LCPLL_DWORD0_1G 0x46AAAA41 +#define N_MODPHY_PCR_LCPLL_DWORD2_1G 0x00000139 +#define N_MODPHY_PCR_LCPLL_DWORD7_1G 0x002A0003 +#define N_MODPHY_PCR_LPPLL_DWORD10_1G 0x00170008 +#define N_MODPHY_PCR_CMN_ANA_DWORD30_1G 0x0000D4AC +#define B_MODPHY_PCR_LCPLL_DWORD0_2P5G 0x58555551 +#define N_MODPHY_PCR_LCPLL_DWORD2_2P5G 0x0000012D +#define N_MODPHY_PCR_LCPLL_DWORD7_2P5G 0x001F0003 +#define N_MODPHY_PCR_LPPLL_DWORD10_2P5G 0x00170008 +#define N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G 0x8200ACAC + +static const struct pmc_serdes_regs pid_modphy3_1g_regs[] = { + { PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G }, + { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G }, + { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G }, + { PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G }, + { PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G }, + {} +}; + +static const struct pmc_serdes_regs pid_modphy3_2p5g_regs[] = { + { PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G }, + { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G }, + { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G }, + { PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G }, + { PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G }, + {} +}; + +static const struct pmc_serdes_regs pid_modphy1_1g_regs[] = { + { PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G }, + { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G }, + { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G }, + { PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G }, + { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G }, + {} +}; + +static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = { + { PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G }, + { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G }, + { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G }, + { PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G }, + { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G }, + {} +}; + +static const int ehl_tsn_lane_registers[] = {7, 8, 9, 10, 11}; +#else +static const int ehl_tsn_lane_registers[] = {}; +#endif /* CONFIG_INTEL_PMC_CORE */ + #endif /* __DWMAC_INTEL_H__ */ diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 5c645b6d5660..a1b8e7cb8447 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1094,11 +1094,31 @@ static void stmmac_mac_link_up(struct phylink_config *config, stmmac_fpe_link_state_handle(priv, true); } +#if IS_ENABLED(CONFIG_INTEL_PMC_CORE) +static int stmmac_mac_prepare(struct phylink_config *config, unsigned int mode, + phy_interface_t interface) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct stmmac_priv *priv = netdev_priv(ndev); + int ret = 0; + + priv->plat->phy_interface = interface; + + if (priv->plat->config_serdes) + ret = priv->plat->config_serdes(ndev, priv->plat->bsp_priv); + + return ret; +} +#endif + static const struct phylink_mac_ops stmmac_phylink_mac_ops = { .mac_select_pcs = stmmac_mac_select_pcs, .mac_config = stmmac_mac_config, .mac_link_down = stmmac_mac_link_down, .mac_link_up = stmmac_mac_link_up, +#if IS_ENABLED(CONFIG_INTEL_PMC_CORE) + .mac_prepare = stmmac_mac_prepare, +#endif }; /** diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 225751a8fd8e..10e45f18fa22 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -245,6 +245,7 @@ struct plat_stmmacenet_data { int (*serdes_powerup)(struct net_device *ndev, void *priv); void (*serdes_powerdown)(struct net_device *ndev, void *priv); void (*speed_mode_2500)(struct net_device *ndev, void *priv); + int (*config_serdes)(struct net_device *ndev, void *priv); void (*ptp_clk_freq_config)(void *priv); int (*init)(struct platform_device *pdev, void *priv); void (*exit)(struct platform_device *pdev, void *priv); From patchwork Thu Jun 22 04:19:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13288247 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 483CD1C02; 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21 Jun 2023 21:20:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="744453877" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="744453877" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.229.33]) by orsmga008.jf.intel.com with ESMTP; 21 Jun 2023 21:20:33 -0700 From: Choong Yong Liang To: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan, Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann Subject: [PATCH net-next 5/6] stmmac: intel: Separate driver_data of ADL-N from TGL Date: Thu, 22 Jun 2023 12:19:04 +0800 Message-Id: <20230622041905.629430-6-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> References: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org From: Michael Sit Wei Hong Separates the driver_data of ADL-N from TGL as a preparation to handle the differences. No functional changes in this commit. Signed-off-by: Michael Sit Wei Hong Signed-off-by: Choong Yong Liang --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 36c91dcb7a78..1ffa03451d26 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -962,6 +962,21 @@ static int adls_sgmii_phy1_data(struct pci_dev *pdev, static struct stmmac_pci_info adls_sgmii1g_phy1_info = { .setup = adls_sgmii_phy1_data, }; + +static int adln_sgmii_phy0_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + plat->bus_id = 1; + plat->phy_interface = PHY_INTERFACE_MODE_SGMII; + plat->serdes_powerup = intel_serdes_powerup; + plat->serdes_powerdown = intel_serdes_powerdown; + return tgl_common_data(pdev, plat); +} + +static struct stmmac_pci_info adln_sgmii1g_phy0_info = { + .setup = adln_sgmii_phy0_data, +}; + static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { { .func = 6, @@ -1344,7 +1359,7 @@ static const struct pci_device_id intel_eth_pci_id_table[] = { { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) }, { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) }, { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) }, - { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) }, + { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &adln_sgmii1g_phy0_info) }, { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) }, {} }; From patchwork Thu Jun 22 04:19:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13288248 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A03DC1C02; Thu, 22 Jun 2023 04:21:02 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E72DE1BE5; Wed, 21 Jun 2023 21:20:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687407657; x=1718943657; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LGc33bAqtZims+Z8ZWCPakULdlqRvmto6XOz1iabewY=; b=mzaHTrEdnuf0LF8cC5q/9Lf0kh6TxV0nMuI7o7vtLD8fCR1UyL1J09SL IsmBLai4klOp/Fx8VOPQc/py3GsZZbi8OE8MG8m8RjN9dyapSBkeD6JTT AYoi+jnds48oGynUNz/wsoJlS2ujqrxuOWsk8k03MpjYyd8niJud7ph2y d1ga/8aIWfs/p1pe3QGOkC1crQGixevGNVA35qceW6glf6kfXmrKwiPQh RHFKSmshtgw/wP7DnVcEPG+RwGk9PAnYEjTw5yE4NYnpWldpYkg1Dy3hB eBZl3e65AkkqG4wpUFXw3PBsIi5y+vqZVuOgnqpFw5jObae60LvYO/UFH w==; X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="363812331" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="363812331" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2023 21:20:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="744453913" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="744453913" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.229.33]) by orsmga008.jf.intel.com with ESMTP; 21 Jun 2023 21:20:45 -0700 From: Choong Yong Liang To: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan, Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann Subject: [PATCH net-next 6/6] net: stmmac: Add 1G/2.5G auto-negotiation support for ADL-N Date: Thu, 22 Jun 2023 12:19:05 +0800 Message-Id: <20230622041905.629430-7-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> References: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add modphy register lane to have 1G/2.5G auto-negotiation support for ADL-N. Signed-off-by: Choong Yong Liang --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 34 ++++++++++++++++++- .../net/ethernet/stmicro/stmmac/dwmac-intel.h | 2 ++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 1ffa03451d26..024f436b276e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -963,14 +963,46 @@ static struct stmmac_pci_info adls_sgmii1g_phy1_info = { .setup = adls_sgmii_phy1_data, }; +static int adln_common_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + struct intel_priv_data *intel_priv = plat->bsp_priv; + + plat->rx_queues_to_use = 6; + plat->tx_queues_to_use = 4; + plat->clk_ptp_rate = 204800000; + + plat->safety_feat_cfg->tsoee = 1; + plat->safety_feat_cfg->mrxpee = 0; + plat->safety_feat_cfg->mestee = 1; + plat->safety_feat_cfg->mrxee = 1; + plat->safety_feat_cfg->mtxee = 1; + plat->safety_feat_cfg->epsi = 0; + plat->safety_feat_cfg->edpp = 0; + plat->safety_feat_cfg->prtyen = 0; + plat->safety_feat_cfg->tmouten = 0; + + intel_priv->tsn_lane_registers = adln_tsn_lane_registers; + intel_priv->max_tsn_lane_registers = ARRAY_SIZE(adln_tsn_lane_registers); + + return intel_mgbe_common_data(pdev, plat); +} + static int adln_sgmii_phy0_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->bus_id = 1; plat->phy_interface = PHY_INTERFACE_MODE_SGMII; + plat->max_speed = SPEED_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; - return tgl_common_data(pdev, plat); + plat->config_serdes = intel_config_serdes; + + intel_priv->pid_modphy = PID_MODPHY1; + + return adln_common_data(pdev, plat); } static struct stmmac_pci_info adln_sgmii1g_phy0_info = { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index 75a336cf8af1..349c160c17b3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -124,8 +124,10 @@ static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = { {} }; +static const int adln_tsn_lane_registers[] = {6}; static const int ehl_tsn_lane_registers[] = {7, 8, 9, 10, 11}; #else +static const int adln_tsn_lane_registers[] = {}; static const int ehl_tsn_lane_registers[] = {}; #endif /* CONFIG_INTEL_PMC_CORE */