From patchwork Thu Jun 22 05:08:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13288263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41277EB64D8 for ; Thu, 22 Jun 2023 05:16:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD7B710E4C2; Thu, 22 Jun 2023 05:16:01 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9756910E4C2 for ; Thu, 22 Jun 2023 05:16:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687410960; x=1718946960; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=cCLPgXZNjrj/AX7Hh2dDFzOsMA3YfS1DpUB2Z3+/LkI=; b=In223yas3KJ4rp4A4CaDCUKViNfSQDtsler+lT71IIXhc58dOElVRtkS 6xeDSqanS02v1G+3zzlzQVks24IyRsMnkkuUqToVmiuLnJkO+yXLqAF0Q GVm6+85S0RKKPiZjEXz4nGV6cEKgvywESANYDMCTuv9IceZlOkDUm8eyf qyfqidYe/u1qRIbVzcQb+x8647zgrmP55eKpYFWH9qNV4pLSzJxkMEh8r ezNvFG6V1W6l/sd05lq46zrJ1L4L99VJFCMnhXd8GNHOgg3U4dbUaWEuF VD9JF6gtg3v7d2JOQUFrMVTmYUXLbay7qcBPamOgigTmLz0Jk7dmi82zg w==; X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="360407700" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="360407700" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2023 22:15:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="804641774" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="804641774" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by FMSMGA003.fm.intel.com with ESMTP; 21 Jun 2023 22:15:58 -0700 From: Arun R Murthy To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Jun 2023 10:38:30 +0530 Message-Id: <20230622050830.1145626-1-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [DO_NOT_REVIEW PATCH] drm/i915/display/dp: On AUX xfer timeout restart freshly X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" At the beginning of the aux transfer a check for aux control busy bit is done. Then as per the spec on aux transfer timeout, need to retry freshly for 3 times with a delay which is taken care by the control register. On each of these 3 trials a check for busy has to be done so as to start freshly. v2: updated the commit message v4: check for SEND_BUSY after write (Imre) v5: reverted the send_ctl to the while loop (Jani) v6: Fixed the BAT failure Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 36 ++++++++++++++------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 197c6e81db14..bebe9a337e37 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -37,7 +37,7 @@ static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) } static u32 -intel_dp_aux_wait_done(struct intel_dp *intel_dp) +intel_dp_aux_wait_for(struct intel_dp *intel_dp, u32 mask, u32 val) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); @@ -45,8 +45,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) u32 status; int ret; - ret = __intel_de_wait_for_register(i915, ch_ctl, - DP_AUX_CH_CTL_SEND_BUSY, 0, + ret = __intel_de_wait_for_register(i915, ch_ctl, mask, val, 2, timeout_ms, &status); if (ret == -ETIMEDOUT) @@ -321,13 +320,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, /* Send the command and wait for it to complete */ intel_de_write(i915, ch_ctl, send_ctl); - status = intel_dp_aux_wait_done(intel_dp); - - /* Clear done status and any errors */ - intel_de_write(i915, ch_ctl, - status | DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR); + status = intel_dp_aux_wait_for(intel_dp, + DP_AUX_CH_CTL_DONE, 1); /* * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 @@ -335,15 +329,33 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, * Timeout errors from the HW already meet this * requirement so skip to next iteration */ - if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { + /* Clear the timeout error */ + intel_de_rmw(i915, ch_ctl, DP_AUX_CH_CTL_TIME_OUT_ERROR, 0); + + /* Clear all errors */ + status = intel_de_read(i915, ch_ctl); + intel_de_write(i915, ch_ctl, status); continue; + } if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { + /* Clear the reveive error */ + intel_de_rmw(i915, ch_ctl, DP_AUX_CH_CTL_RECEIVE_ERROR, 0); usleep_range(400, 500); + /* Clear all errors */ + status = intel_de_read(i915, ch_ctl); + intel_de_write(i915, ch_ctl, status); continue; } - if (status & DP_AUX_CH_CTL_DONE) + if (status & DP_AUX_CH_CTL_DONE) { + /* Clear aux done */ + intel_de_rmw(i915, ch_ctl, DP_AUX_CH_CTL_DONE, 0); + /* Clear all errors */ + status = intel_de_read(i915, ch_ctl); + intel_de_write(i915, ch_ctl, status); goto done; + } } }