From patchwork Sat Jun 24 13:16:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13291669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43579EB64DC for ; Sat, 24 Jun 2023 13:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230342AbjFXNRF (ORCPT ); Sat, 24 Jun 2023 09:17:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229452AbjFXNRE (ORCPT ); Sat, 24 Jun 2023 09:17:04 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4607BA9; Sat, 24 Jun 2023 06:17:03 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f9c532fa45so16440875e9.2; Sat, 24 Jun 2023 06:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687612621; x=1690204621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x4HOHpTuxkhDI1uIn7GRBULu0rY5eOvyg0W/1k8C9T4=; b=rUrqWapO4pYhvePnS7Vq1czHnSJ9zPSgqsffqLURJUNHIlAZ8ys2Si7q8pQzxZ74tt FBZszCa8TucARVI8q8sZ9Avu+4Lj6Ctpu46rODvpVqB85qOYaTwYqiX6LQlZb+GFLdXi nW9isyDNnVfiAdioaHD73UdoRS6Hzlo3qFVh2wPjkV/LjRolMt26XqzDM9xRpUkXeV0P a1D+kktEkyFfedDfIJFTLbpXVq1Sv/peqNNlFZGEGDc1PsG8gDz5zzBWi5Q2u+8RNkf7 /m2w4STUaHct/MJ2jp2F/Xb8cf5To/tikiCVX745Mml/Wtkd+V3xnDjwHz4NJZWDiild GNgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687612621; x=1690204621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x4HOHpTuxkhDI1uIn7GRBULu0rY5eOvyg0W/1k8C9T4=; b=YrkOYko+1pWjCS4qQgaqmuX3nFHfLWi+ALVzt5E983Ho+M5Ie8FtuvJ85FYbl83/vf 8DfV3LzI7dvmiO6sImQoatFl/h/7Q8W5PFS1VRIv1MCCiK1s5U9eBAqBz684q7Rf0HRY C1Dr/dZ9LzEDTqdbSbEyWv7ZwxCQzdISGHXH9OH0P/PSTbmT5n2dOolu+UmOUMU0iWIv hCbwc+j8OiRcrCk9SZKZ5g5LN18eyIhWcEo/ju2TEwjfyWB3U9Po1EmLM4iyE54FnuHw ifr8IH01LxD7YUofd8jtslGV1GdfmEQrErxs6RDf1n+6IQnEeNF+NrcIXHXTYhHXCVdZ ZA0A== X-Gm-Message-State: AC+VfDzUne0Ay/v8L/LY4uzDoUOyvprXM1vnpeOVGT8rxvEvtM9TDiEF xo+Xk/HW2X48DJbSlwJDaf2id4CH6it0ZuQm X-Google-Smtp-Source: ACHHUZ7xACTfdartW6THNtoCrYALyLgEq0fwWG5cJD775ZZVWt6/8PJrOTn9k1ZPAJRW/uUOUStIWQ== X-Received: by 2002:a1c:f70a:0:b0:3f7:34dc:ed0d with SMTP id v10-20020a1cf70a000000b003f734dced0dmr16795214wmh.25.1687612620714; Sat, 24 Jun 2023 06:17:00 -0700 (PDT) Received: from user-PC.. ([92.51.95.194]) by smtp.gmail.com with ESMTPSA id l1-20020a1ced01000000b003f9b0830107sm5107428wmh.41.2023.06.24.06.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jun 2023 06:17:00 -0700 (PDT) From: Maksim Kiselev To: linux-spi@vger.kernel.org Cc: Maksim Kiselev , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Mark Brown , Andre Przywara , Cristian Ciocaltea , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/3] spi: sun6i: add quirk for dual and quad SPI modes support Date: Sat, 24 Jun 2023 16:16:22 +0300 Message-Id: <20230624131632.2972546-2-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230624131632.2972546-1-bigunclemax@gmail.com> References: <20230624131632.2972546-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org New Allwinner's SPI controllers can support dual and quad SPI modes. To enable one of these modes, we should set the corresponding bit in the SUN6I_BURST_CTL_CNT_REG register. DRM (28 bits) for dual mode and Quad_EN (29 bits) for quad transmission. Signed-off-by: Maksim Kiselev --- drivers/spi/spi-sun6i.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 30d541612253..cec2747235ab 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -83,6 +83,9 @@ #define SUN6I_XMIT_CNT_REG 0x34 #define SUN6I_BURST_CTL_CNT_REG 0x38 +#define SUN6I_BURST_CTL_CNT_STC_MASK GENMASK(23, 0) +#define SUN6I_BURST_CTL_CNT_DRM BIT(28) +#define SUN6I_BURST_CTL_CNT_QUAD_EN BIT(29) #define SUN6I_TXDATA_REG 0x200 #define SUN6I_RXDATA_REG 0x300 @@ -90,6 +93,7 @@ struct sun6i_spi_cfg { unsigned long fifo_depth; bool has_clk_ctl; + u32 mode_bits; }; struct sun6i_spi { @@ -266,7 +270,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, unsigned int div, div_cdr1, div_cdr2, timeout; unsigned int start, end, tx_time; unsigned int trig_level; - unsigned int tx_len = 0, rx_len = 0; + unsigned int tx_len = 0, rx_len = 0, nbits = 0; bool use_dma; int ret = 0; u32 reg; @@ -418,13 +422,29 @@ static int sun6i_spi_transfer_one(struct spi_master *master, sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); /* Setup the transfer now... */ - if (sspi->tx_buf) + if (sspi->tx_buf) { tx_len = tfr->len; + nbits = tfr->tx_nbits; + } else if (tfr->rx_buf) { + nbits = tfr->rx_nbits; + } + + switch (nbits) { + case SPI_NBITS_DUAL: + reg = SUN6I_BURST_CTL_CNT_DRM; + break; + case SPI_NBITS_QUAD: + reg = SUN6I_BURST_CTL_CNT_QUAD_EN; + break; + case SPI_NBITS_SINGLE: + default: + reg = FIELD_PREP(SUN6I_BURST_CTL_CNT_STC_MASK, tx_len); + } /* Setup the counters */ + sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg); sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len); - sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len); if (!use_dma) { /* Fill the TX FIFO */ @@ -623,7 +643,8 @@ static int sun6i_spi_probe(struct platform_device *pdev) master->set_cs = sun6i_spi_set_cs; master->transfer_one = sun6i_spi_transfer_one; master->num_chipselect = 4; - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | + sspi->cfg->mode_bits; master->bits_per_word_mask = SPI_BPW_MASK(8); master->dev.of_node = pdev->dev.of_node; master->auto_runtime_pm = true; From patchwork Sat Jun 24 13:16:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13291670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3753EEB64DC for ; Sat, 24 Jun 2023 13:17:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231203AbjFXNRO (ORCPT ); Sat, 24 Jun 2023 09:17:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231375AbjFXNRN (ORCPT ); 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([92.51.95.194]) by smtp.gmail.com with ESMTPSA id l1-20020a1ced01000000b003f9b0830107sm5107428wmh.41.2023.06.24.06.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jun 2023 06:17:07 -0700 (PDT) From: Maksim Kiselev To: linux-spi@vger.kernel.org Cc: Maksim Kiselev , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Mark Brown , Andre Przywara , Cristian Ciocaltea , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/3] spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s Date: Sat, 24 Jun 2023 16:16:23 +0300 Message-Id: <20230624131632.2972546-3-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230624131632.2972546-1-bigunclemax@gmail.com> References: <20230624131632.2972546-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Listed SoCs have SPI controllers that can operate in dual or quad modes. This patch adds dual/quad mode bits for spi_master on these SoCS. Signed-off-by: Maksim Kiselev --- drivers/spi/spi-sun6i.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index cec2747235ab..e9144d76bcdb 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -761,6 +761,7 @@ static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = { static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = { .fifo_depth = SUN8I_FIFO_DEPTH, + .mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD, }; static const struct of_device_id sun6i_spi_match[] = { From patchwork Sat Jun 24 13:16:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13291671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D424BC0015E for ; Sat, 24 Jun 2023 13:17:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231375AbjFXNRV (ORCPT ); Sat, 24 Jun 2023 09:17:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232981AbjFXNRT (ORCPT ); Sat, 24 Jun 2023 09:17:19 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDE771FF0; Sat, 24 Jun 2023 06:17:17 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3fa71e253f2so25207285e9.0; Sat, 24 Jun 2023 06:17:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687612636; x=1690204636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KAYPGxSTFPjM3RqhwW9I/u0fjI7Fx45EUbdLcf3Fbbk=; b=RTqZRv+kicZW7QzVJK3ZagJlTPPID3erCQjK8DbAaVPTMWw3b0mjuGV5SQVg3A7Hfp kTP3MO1AV9lx1/fyLW3WpWXj4HmKkLq3zsShiKr+AZkRpIUvDHPemFoM8d6lYuJBkhVf VwXLSS0PvzKxnzoIXhwxmKBAloifepGmC78ZDgEmk5MbVTY+UmUcnQs8jnP7jUKTgQ1t ovA2xPB5nkCELrRww6By/LY2lIhiGufo89h+gKofzrfcx/6CnBLsCo++cVmYMzLAiVW3 P2v56HjmRyol/JePLMkvownV0cd+4jPAN3a3PkXbpyjqgTMgtriUwWMRfhDtyahMiisK i7jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687612636; x=1690204636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KAYPGxSTFPjM3RqhwW9I/u0fjI7Fx45EUbdLcf3Fbbk=; b=QRKD+Pcjcox3UgNNFPsHHsErRw05pwQlA5aFgg2lrkjnHOaiW8jNI3epDvb+hbZIvR mzn0HJVDjNnoEQ3M2wV/5ANgsp+BrDSzui9LnUvWkBH3vDqg4TKOS6/W/IUUjnLQjbpi XWuApkkTQbTPnwqfbej4iQ+pcGZlc9fuC/Xc2VxVUEFNQ3UL6MhUpBnHsc3NQa4vvNUh 8QGjED63Ox8cspJ9uHgGNy5FUH77edXVPz2Lz2HJ5PyF+Uyh6aNM/8airSMBYk4tNXZp rK7VrQ6hdFaW5eKALm0Eh6KdPR0cihUYX71IKepAYW3tiAIKJXupeou6cn0b0Vs7phhF txAw== X-Gm-Message-State: AC+VfDwxtLs+KRi5Yb1csUX86kdX12gINmYMrA74eZvh1JE8poJSwM7d gOwxfhwLovEEZ1BBArP74osk/Ucw+0tJDWW3 X-Google-Smtp-Source: ACHHUZ6AxRD4qR+dRoN7S7SE01tpvdTdIi7AeyJugnitjFY045wLn75ojjvOMv78elsfe85Qmldkag== X-Received: by 2002:a05:600c:245:b0:3fa:838d:adbd with SMTP id 5-20020a05600c024500b003fa838dadbdmr1749644wmj.1.1687612635438; Sat, 24 Jun 2023 06:17:15 -0700 (PDT) Received: from user-PC.. ([92.51.95.194]) by smtp.gmail.com with ESMTPSA id l1-20020a1ced01000000b003f9b0830107sm5107428wmh.41.2023.06.24.06.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jun 2023 06:17:15 -0700 (PDT) From: Maksim Kiselev To: linux-spi@vger.kernel.org Cc: Maksim Kiselev , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Mark Brown , Cristian Ciocaltea , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port Date: Sat, 24 Jun 2023 16:16:24 +0300 Message-Id: <20230624131632.2972546-4-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230624131632.2972546-1-bigunclemax@gmail.com> References: <20230624131632.2972546-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add pinmux node that describes pins on PC port which required for QSPI mode. Signed-off-by: Maksim Kiselev Acked-by: Jernej Skrabec --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 1bb1e5cae602..9f754dd03d85 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + qspi0_pc_pins: qspi0-pc-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", + "PC7"; + function = "spi0"; + }; }; ccu: clock-controller@2001000 {