From patchwork Sat Jun 24 17:17:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13291687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E101DEB64DC for ; Sat, 24 Jun 2023 17:18:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 67BC210E1AF; Sat, 24 Jun 2023 17:18:03 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFD4310E056; Sat, 24 Jun 2023 17:17:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687627079; x=1719163079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TK8Gb7f2BDs9GOuCBaWtGKVA75KBpqbPu5MicNEzqLA=; b=CmcvhvfChTOGgOygKnJXBDudlrPF1qgGNpScqP0Ufrjrr6psmm5R9aOr b1proc98XyKNj4ndoryCDnkBjvjpLdfbF5iZRvfFoxRaJvnrd7YDlAEsg W/WD8iw7iIheH3aa2ilvFMw1RcKJgfQdEjq6D5WNGp2QUWosnq66NcxMt V3uXfpSwE2nXLfRpeT0gn6Y0BGf+FEJ4fwnnQYQ626zFTleCafKkuLT5t jP24EMW2wA3pp1MqjdII6qSYPfimYKy7dn33LcT2z3XIu+uEOTPRv1ElP HV1PcXMalbEW8t4/q/3OZBmiYWB8OoSk+edmsokcYaeApuoCs2y4sTuyb Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="340557467" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="340557467" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="1045977413" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="1045977413" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:58 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 1/6] drm/i915/gt: Move wal_get_fw_for_rmw() Date: Sat, 24 Jun 2023 10:17:52 -0700 Message-Id: <20230624171757.3906095-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230624171757.3906095-1-lucas.demarchi@intel.com> References: <20230624171757.3906095-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , Kenneth Graunke , Matt Roper , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Move helper function to get all the forcewakes required by the wa list to the top, so it can be re-used by other functions. Signed-off-by: Lucas De Marchi Reviewed-by: Kenneth Graunke --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 01807a7dd2c1..8f8346df3c18 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -123,6 +123,22 @@ static void wa_init_finish(struct i915_wa_list *wal) wal->wa_count, wal->name, wal->engine_name); } +static enum forcewake_domains +wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) +{ + enum forcewake_domains fw = 0; + struct i915_wa *wa; + unsigned int i; + + for (i = 0, wa = wal->list; i < wal->count; i++, wa++) + fw |= intel_uncore_forcewake_for_reg(uncore, + wa->reg, + FW_REG_READ | + FW_REG_WRITE); + + return fw; +} + static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) { unsigned int addr = i915_mmio_reg_offset(wa->reg); @@ -1859,22 +1875,6 @@ void intel_gt_init_workarounds(struct intel_gt *gt) wa_init_finish(wal); } -static enum forcewake_domains -wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) -{ - enum forcewake_domains fw = 0; - struct i915_wa *wa; - unsigned int i; - - for (i = 0, wa = wal->list; i < wal->count; i++, wa++) - fw |= intel_uncore_forcewake_for_reg(uncore, - wa->reg, - FW_REG_READ | - FW_REG_WRITE); - - return fw; -} - static bool wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, const char *name, const char *from) From patchwork Sat Jun 24 17:17:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13291685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2AF26EB64DD for ; Sat, 24 Jun 2023 17:18:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3EA5010E07D; Sat, 24 Jun 2023 17:18:02 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 07AE210E009; Sat, 24 Jun 2023 17:18:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687627080; x=1719163080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c30KrreN7/GB/ngoSIdSdI0DuqnFwW6/O3MZAv+wURU=; b=ZD8aLHkY2/wxtyENNdHV3VFTeGKe4XbCT08oNE1mPSCkh597ewCa8TNB R/ozGNR5iCqqPp//cN2J/yn5EsncweHoxjP5VjnnWHllAKm1mpOG0XbCM 8LBgIT0ceWXthoZkbJy1gKhKANbHj2N3I6y01qFchxcnj8m/t+Cogon4P iGkfPX+KA48H4NOV7HKNYpOEif+62vMr8dPyQvNzwifZqmS+MTa3sghbt A0JiZl3me/8zVqMrszVhuAEzz5cYIg87ECO0UkDH/VphiNRDBHAWoq4f7 J5+MjnYWhc9FwK8Y0cii5M9BqmlbVOR9yfgEVVYhvBxUlB1p5jUrayDcB A==; X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="340557470" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="340557470" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="1045977418" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="1045977418" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:58 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 2/6] drm/i915/gt: Clear all bits from GEN12_FF_MODE2 Date: Sat, 24 Jun 2023 10:17:53 -0700 Message-Id: <20230624171757.3906095-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230624171757.3906095-1-lucas.demarchi@intel.com> References: <20230624171757.3906095-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , Kenneth Graunke , Matt Roper , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Right now context workarounds don't do a rmw and instead only write to the register. Since 2 separate programmings to the same register are coalesced into a single write, this is not problematic for GEN12_FF_MODE2 since both TDS and GS timer are going to be written together and the other remaining bits be zeroed. However in order to fix other workarounds that may want to preserve the unrelated bits in the same register, context workarounds need to be changed to a rmw. To prepare for that, move the programming of GEN12_FF_MODE2 to a single place so the value passed for "clear" can be all the bits. Otherwise the second workaround would be dropped as it'd be detected as overwriting a previously programmed workaround. Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 51 +++++++-------------- 1 file changed, 17 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 8f8346df3c18..7d48bd57b6ef 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -693,40 +693,11 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 0, false); } -/* - * These settings aren't actually workarounds, but general tuning settings that - * need to be programmed on several platforms. - */ -static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, - struct i915_wa_list *wal) -{ - /* - * Although some platforms refer to it as Wa_1604555607, we need to - * program it even on those that don't explicitly list that - * workaround. - * - * Note that the programming of this register is further modified - * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. - * Wa_1608008084 tells us the FF_MODE2 register will return the wrong - * value when read. The default value for this register is zero for all - * fields and there are no bit masks. So instead of doing a RMW we - * should just write TDS timer value. For the same reason read - * verification is ignored. - */ - wa_add(wal, - GEN12_FF_MODE2, - FF_MODE2_TDS_TIMER_MASK, - FF_MODE2_TDS_TIMER_128, - 0, false); -} - static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct drm_i915_private *i915 = engine->i915; - gen12_ctx_gt_tuning_init(engine, wal); - /* * Wa_1409142259:tgl,dg1,adl-p * Wa_1409347922:tgl,dg1,adl-p @@ -748,15 +719,27 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); /* - * Wa_16011163337 + * Wa_16011163337 - GS_TIMER + * + * TDS_TIMER: Although some platforms refer to it as Wa_1604555607, we + * need to program it even on those that don't explicitly list that + * workaround. + * + * Note that the programming of GEN12_FF_MODE2 is further modified + * according to the FF_MODE2 guidance given by Wa_1608008084. + * Wa_1608008084 tells us the FF_MODE2 register will return the wrong + * value when read from the CPU. * - * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due - * to Wa_1608008084. + * The default value for this register is zero for all fields. + * So instead of doing a RMW we should just write the desired values + * for TDS and GS timers. Note that since the readback can't be trusted, + * the clear mask is just set to ~0 to make sure other bits are not + * inadvertently set. For the same reason read verification is ignored. */ wa_add(wal, GEN12_FF_MODE2, - FF_MODE2_GS_TIMER_MASK, - FF_MODE2_GS_TIMER_224, + ~0, + FF_MODE2_TDS_TIMER_128 | FF_MODE2_GS_TIMER_224, 0, false); if (!IS_DG1(i915)) { From patchwork Sat Jun 24 17:17:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13291689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6A1AEB64DA for ; Sat, 24 Jun 2023 17:18:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 344E210E150; Sat, 24 Jun 2023 17:18:03 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19DF310E059; Sat, 24 Jun 2023 17:18:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687627080; x=1719163080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BK2i3uF8Mp1d8mtepKV6VDyQ8iqxwT8putwYzVYSo2k=; b=A2hlGKPOj0iT0sLPz9w2ekgXrJYJ+MG8OjZOh+VWzqkCVs+gY/aZj1Yl qLZ4s57EJs3ZvUtZwcyVmoH0ROqks9fwXjNVNotvYOZJQYFbLXLMWPp99 MCnXyBVAcrSwEqJRPqGL/WgDjcmzcKyauZPZbza7pT0lM4pydIvUkSyj3 rM5/xbl1cvCZVb1UNIWZL6z1IOYiTZnTOa2QZMd/Y/YcxiaSnpTK6TQV+ OLxWR4NJ5oX4FEtrEyX7+ptgiTfI6si6ayzHUP35X6yBYobKwZf1gUuuP a7+bBFMcuKdZETQWcgefrSQuVQh0SlEieqIDlwtoupyB1aFG/x9hLNNqs Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="340557472" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="340557472" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="1045977421" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="1045977421" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:59 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 3/6] drm/i915/gt: Fix context workarounds with non-masked regs Date: Sat, 24 Jun 2023 10:17:54 -0700 Message-Id: <20230624171757.3906095-4-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230624171757.3906095-1-lucas.demarchi@intel.com> References: <20230624171757.3906095-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , Kenneth Graunke , Matt Roper , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Most of the context workarounds tweak masked registers, but not all. For masked registers, when writing the value it's sufficient to just write the wa->set_bits since that will take care of both the clr and set bits as well as not overwriting other bits. However there are some workarounds, the registers are non-masked. Up until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the set_bits to program the register via the GPU in the WA bb. This has the side effect of overwriting the content of the register outside of bits that should be set and also doesn't handle the bits that should be cleared. Kenneth reported that on DG2, mesa was seeing a weird behavior due to the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With the GPU idle, that register could be read via intel_reg as 0x00e001ff, but during a 3D workload it would change to 0x0000007f. So the programming of that tuning was affecting more than the bits in L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the context workarounds due to the use of MI_LOAD_REGISTER_IMM. So, for registers that are not masked, read its value via mmio, modify and then set it in the buffer to be written by the GPU. This should take care in a simple way of programming just the bits required by the tuning/workaround. If in future there are registers that involved that can't be read by the CPU, a more complex approach may be required like a) issuing additional instructions to read and modify; or b) scan the golden context and patch it in place before saving it; or something else. But for now this should suffice. Scanning the context workarounds for all platforms, these are the impacted ones with the respective registers mtl: DRAW_WATERMARK mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2 ICL has some non-masked registers in the context workarounds: GEN8_L3CNTLREG, IVB_FBC_RT_BASE and VB_FBC_RT_BASE_UPPER, but there shouldn't be an impact. The first is already being manually read and the other 2 are intentionally overwriting the entire register. Same reasoning applies to GEN12_FF_MODE2: the WA is intentionally overwriting all the bits to avoid a read-modify-write. v2: Reword commit message wrt GEN12_FF_MODE2 and the changed behavior on preparatory patches. Cc: Kenneth Graunke Cc: Matt Roper Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23783#note_1968971 Signed-off-by: Lucas De Marchi Reviewed-by: Kenneth Graunke --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 7d48bd57b6ef..9291c2b4ca0e 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -986,6 +986,9 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) int intel_engine_emit_ctx_wa(struct i915_request *rq) { struct i915_wa_list *wal = &rq->engine->ctx_wa_list; + struct intel_uncore *uncore = rq->engine->uncore; + enum forcewake_domains fw; + unsigned long flags; struct i915_wa *wa; unsigned int i; u32 *cs; @@ -1002,13 +1005,35 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) if (IS_ERR(cs)) return PTR_ERR(cs); + fw = wal_get_fw_for_rmw(uncore, wal); + + intel_gt_mcr_lock(wal->gt, &flags); + spin_lock(&uncore->lock); + intel_uncore_forcewake_get__locked(uncore, fw); + *cs++ = MI_LOAD_REGISTER_IMM(wal->count); for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { + u32 val; + + if (wa->masked_reg || wa->set == U32_MAX) { + val = wa->set; + } else { + val = wa->is_mcr ? + intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) : + intel_uncore_read_fw(uncore, wa->reg); + val &= ~wa->clr; + val |= wa->set; + } + *cs++ = i915_mmio_reg_offset(wa->reg); - *cs++ = wa->set; + *cs++ = val; } *cs++ = MI_NOOP; + intel_uncore_forcewake_put__locked(uncore, fw); + spin_unlock(&uncore->lock); + intel_gt_mcr_unlock(wal->gt, flags); + intel_ring_advance(rq, cs); ret = rq->engine->emit_flush(rq, EMIT_BARRIER); From patchwork Sat Jun 24 17:17:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13291688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C4B5EB64DC for ; Sat, 24 Jun 2023 17:18:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3ED010E134; Sat, 24 Jun 2023 17:18:02 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2D9AF10E07D; Sat, 24 Jun 2023 17:18:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687627080; x=1719163080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EnzMAs93HE4/VbPPBqLe1SLEbsU1YIjB3MLZiLNtOu8=; b=NpqemAqfAjpVLkGD88tnDWvoJJRW6g3iGX4fQ/l6RuRoOWAa+PshnEnI RcWkQ7lS8IrSuZq/gBVSQdlaCiHGEpOVJa2OnARYePA4btzfy8s1lnXnA hmWLHCxvwPFRWbTK0AIrcfPFafLjNfKOmMw61jRflmIICCa26huNtKuRN VvXXn1x/iaNmVPl1YK5vZt3pFJQhZj9d3qxy6dDDwfqLiHDaU2TV+RE9p r0JrFYnyb1Ml4/PtI+4YmIhNGdCfBGXbBnpCJ26Vn/VRUOMYLcjOCSwpO A1hAPqqyxb3el+Em5m+20/7b6lyAfC0PixPCdVkvo+Yhfqzi/Ff10yKiS Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="340557474" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="340557474" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="1045977424" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="1045977424" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:59 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 4/6] drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround Date: Sat, 24 Jun 2023 10:17:55 -0700 Message-Id: <20230624171757.3906095-5-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230624171757.3906095-1-lucas.demarchi@intel.com> References: <20230624171757.3906095-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , Kenneth Graunke , Matt Roper , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now that non-masked registers are already read before programming the context reads, the additional read became redudant, so remove it. Signed-off-by: Lucas De Marchi Reviewed-by: Kenneth Graunke --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 9291c2b4ca0e..8ec3d14dcb08 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -637,10 +637,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { /* Wa_1406697149 (WaDisableBankHangMode:icl) */ - wa_write(wal, - GEN8_L3CNTLREG, - intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | - GEN8_ERRDETBCTRL); + wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL); /* WaForceEnableNonCoherent:icl * This is not the same workaround as in early Gen9 platforms, where From patchwork Sat Jun 24 17:17:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13291686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 302DDEB64DC for ; Sat, 24 Jun 2023 17:18:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D225410E133; Sat, 24 Jun 2023 17:18:02 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47C6F10E056; Sat, 24 Jun 2023 17:18:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687627080; x=1719163080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pAYoh1LVoLdb5D8B77xFqwkY1qGH/zC9UKyHXrH/2y4=; b=bw/eRyITph3/3LThr0Wn5sh0O4BxGpZl4UYjxaWjQ0yLR79V3+dt/Ff0 0Tprd2EY6j+C2/EfphQHH+3b/nibTRjtFLSaXtUw4dyUNcsHv9/1oJlMP Ji8NzNXdSYLWbvQR2MgwdU5PovaRaoLsjkgU0lhluH4LE6xqhNo6lgq2M MPLMs2M/b5WKWHL2059om1yo+W4y7tfpZwsPE7bDgWj0/LmellkuQTDZx 3I3DH5Z2wZ3E0EojcGvEIXA8K2445wFDKzdsTGKWxu5WcJ9CPPhl7+D4W JbcegJ52R0qxSScjfHn4/XAB/QEMuDfYsL6tU4FY1UDcNuxIXU540ta6G Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="340557476" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="340557476" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:18:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="1045977427" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="1045977427" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:17:59 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 5/6] drm/i915/gt: Enable read back on XEHP_FF_MODE2 Date: Sat, 24 Jun 2023 10:17:56 -0700 Message-Id: <20230624171757.3906095-6-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230624171757.3906095-1-lucas.demarchi@intel.com> References: <20230624171757.3906095-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , Kenneth Graunke , Matt Roper , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Contrary to GEN12_FF_MODE2, platforms using XEHP_FF_MODE2 are not affected by Wa_1608008084, hence read back can be enabled. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 8ec3d14dcb08..848519b58e45 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -683,11 +683,8 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); - wa_mcr_add(wal, - XEHP_FF_MODE2, - FF_MODE2_TDS_TIMER_MASK, - FF_MODE2_TDS_TIMER_128, - 0, false); + wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK, + FF_MODE2_TDS_TIMER_128); } static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, From patchwork Sat Jun 24 17:17:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13291691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23CCDC0015E for ; Sat, 24 Jun 2023 17:18:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9642410E1BB; Sat, 24 Jun 2023 17:18:09 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id BB88B10E009; Sat, 24 Jun 2023 17:18:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687627080; x=1719163080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/exRLLCCIJ+SCYmv1qZD/7JAXfhDLR/kzhGGpYwNrSQ=; b=T542cwk9og0vFXUL6YsUKFW7+2SAGkVfGrVaQXEANmdVNIksAtCPG5WM XCa2BC4nwIDSHa6nisHWZ34S1idrpNSm+nhrB+SNKE4DzS0sRDI42kZwK tLDDgvwMYmuYuagXxauZVMscg1wFJlFKIU/mfnDnI2kRoEvp6enKTujaX jZ5MfJf92CRBXIqi2tb2dufqLqebYpc0knB71jFAs7lnecblKfaB1XrLE R658n1KWjv9BscmkcvaDdKrGokTotFw7SeoOen0RJtoe4H5cx2/5UeMO2 BdRnuOZosHBXR4sFv8LvPUOFzxy0r0z6bLoGitl2a3a6jrUOnB13sxuyg A==; X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="340557478" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="340557478" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:18:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10751"; a="1045977430" X-IronPort-AV: E=Sophos;i="6.01,155,1684825200"; d="scan'208";a="1045977430" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2023 10:18:00 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 6/6] drm/i915/gt: Remove bogus comment on IVB_FBC_RT_BASE_UPPER Date: Sat, 24 Jun 2023 10:17:57 -0700 Message-Id: <20230624171757.3906095-7-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230624171757.3906095-1-lucas.demarchi@intel.com> References: <20230624171757.3906095-1-lucas.demarchi@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , Kenneth Graunke , Matt Roper , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The comment on the parameter being 0 to avoid the read back doesn't apply as this is not a call to wa_mcr_add(), but rather to wa_mcr_clr_set(). So, this register is actually checked and it's according to the Bspec that the register is RW, not RO. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 848519b58e45..5fe85fad91c1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -666,7 +666,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_1604278689:icl,ehl */ wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, - 0, /* write-only register; skip validation */ + 0, 0xFFFFFFFF); /* Wa_1406306137:icl,ehl */