From patchwork Tue Jun 27 08:23:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandr Shubin X-Patchwork-Id: 13294181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 951C4EB64DC for ; Tue, 27 Jun 2023 08:24:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yF1+fojP6Gf83TAF1+lv8TUYjDjn4TSE5GHl8snhfCY=; b=zM/lKT64iLU7xJ f4qAiUV+Sxs6z1lv9ad7ItPWmW/zUVxed5lfUPQJUizcXXw+VVkR0UvCLEvdiTbrta7BWEwYURJSU YQ+8Th0l9awzW4z4faXpPH4byMSnkSi9lUvUa1DDT9k+NA3xdcmkDZWa7L1kKU0GY/Ue7V3U8Qx3f JClcy9FH2UbaeiKVKXJVZDRgWCQrEv7i5RfiyqqTAPliexsSgEkFsEd0aI2aFd7Z6TW6yzv/Fvdl1 MGK6uk/JNf+rpTAOiO0dYPmz7plufXakFNvOktJDBd1+tmuMwbzCpxwA3i42WVReri6Q6Tsz37rnU 96TkSQB+RU55MQDJ1GvQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qE3zb-00CYfJ-2x; Tue, 27 Jun 2023 08:24:07 +0000 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qE3zY-00CYeB-0o; Tue, 27 Jun 2023 08:24:05 +0000 Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4fb7769f15aso2543468e87.0; Tue, 27 Jun 2023 01:24:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687854242; x=1690446242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UR637DGW7U+8J1v52/3DiqPM0xg6ESr2sC1jjmXcP0A=; b=BLDWoUFtt3Bo7ljQfBO5wWhIJ0UQ+3mJWwUnIuj1QstxE8M9wCvdk6Jwe7Jexayq6s NOaJj0eh7j+IfOFIGatQd7NG8+2z5bbNyq0V19seJ+Umk7Tt+PnycA+dYggdsH58q6gq xRhpDRXCfASOONUgw7UqeoY+fYWrQzPqUlBScflYOUPXb4KRr580QFiaWzwOiWFMH2Bh 41iGVHf4sWkdAkkC3onjqB8hNJ9kaS8Bp8VQc4K24+1xN+4qC3fVxiX9GzQmaSuMI6hf FqYY1+S8qhrDbuBaabF+blZVJq48f21E8x536x7kQSe00BMrkvxHzZ0/eAtp0L2f7J+R Yrrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687854242; x=1690446242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UR637DGW7U+8J1v52/3DiqPM0xg6ESr2sC1jjmXcP0A=; b=GzdE/2tu7XViuxIVXVeD8JcSSNO7Uw9jQpfPFafSePGLeqFFhm+392fhSXKkAOUlcm JGieOvFiSl2DZowXuAxZj+spbQoAwlQHFDkBm2RZaJaT879YI3V6mc8MhVJLrrCe/Uuj /5sLDnoCHy4jTC8jQu+NM2+D75P8gYAP0TQo8fMLWxVt05F1oWsWpoEwOSyVD7Vp3rb1 BtAB2qvBynr2/swuGvCfFTJ+Op5fdq9rcF1ABqiMOmTiFKAkCI29zy/bXh6ZhBt7yBAm sHAqYfdcP7iFlTc76TWPP7tGUvxtXszWrisvtqWfvcktxR6kXLtSIuaZ6HACTAW1dFC0 84+A== X-Gm-Message-State: AC+VfDzLhU7HHz9WMz4ENUJt5vgR11KjMvJejTSaWNslNP/Z0Chznt7K 7AJAkcN/ETgtfeZ4m1B83A== X-Google-Smtp-Source: ACHHUZ54diBm0xcGDbn6+u2ecv13BQULswvrHhNEltJ8WhUHoJS0f4ce4RpKx+kLppmCy2ddaOrRKQ== X-Received: by 2002:a19:5057:0:b0:4f9:5396:ed1b with SMTP id z23-20020a195057000000b004f95396ed1bmr12121804lfj.28.1687854242296; Tue, 27 Jun 2023 01:24:02 -0700 (PDT) Received: from localhost.localdomain (mail.pulsar-telecom.ru. [94.181.180.60]) by smtp.gmail.com with ESMTPSA id i12-20020a056512006c00b004eb12329053sm1420673lfo.256.2023.06.27.01.24.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 01:24:01 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Andre Przywara , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v3 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Date: Tue, 27 Jun 2023 11:23:24 +0300 Message-Id: <20230627082334.1253020-2-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230627082334.1253020-1-privatesub2@gmail.com> References: <20230627082334.1253020-1-privatesub2@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230627_012404_293455_1137A5A7 X-CRM114-Status: GOOD ( 15.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i. The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense. The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels. D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one). Add a device tree binding for them. Signed-off-by: Aleksandr Shubin Reviewed-by: Conor Dooley --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file mode 100644 index 000000000000..4e6eaa18f342 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Aleksandr Shubin + +properties: + compatible: + oneOf: + - const: allwinner,sun20i-d1-pwm + - items: + - const: allwinner,sun20i-r329-pwm + - const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: 24 MHz oscillator + - description: Bus Clock + + clock-names: + items: + - const: hosc + - const: bus + + resets: + maxItems: 1 + + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9] + +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + const: allwinner,sun20i-r329-pwm + + then: + required: + - allwinner,pwm-channels + + else: + not: + required: + - allwinner,pwm-channels + +unevaluatedProperties: false + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + +examples: + - | + #include + #include + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <0x3>; + }; + +... From patchwork Tue Jun 27 08:23:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandr Shubin X-Patchwork-Id: 13294182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CDB0EB64DD for ; Tue, 27 Jun 2023 08:24:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7K4JHSw7kzGFh1Nz8mFNDBLDRqKQBUo3/CxWVHLMXBc=; b=IfA8wOUK34rkdq KIW3Z7nbeb0b5T/qsRqTRTTezv5/GeIsaia8sF6/yh1vIKDxUbVxIQOjph9LcFVY/f2ukAnUSy4+q l+seygLJ8THEKSqiHkdG5TGi2c1pj76lOgdgUnSj4yssH7Wr+EhAaV2YsrbhLX1v3kDQI6fwluvax Xo4xQD22hTPAO1ON2+JzudPpJ4NEzS5PqRoI7IBTgLEZPSFg7Il/Lfck558VNUGxnK93H0RNqGRwF rmhhz25nv4cuIbshZPs6ti4xjWeDuaPUqHKf3Q+KVe9Du4/Vtn8ZZypxa45EJ/xnag+QgP8Ux0IN7 ajNOAkEWyFOS7LndjU8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qE3zp-00CYjw-1I; Tue, 27 Jun 2023 08:24:21 +0000 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qE3zl-00CYhe-1c; Tue, 27 Jun 2023 08:24:19 +0000 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2b4826ba943so58277551fa.0; Tue, 27 Jun 2023 01:24:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687854253; x=1690446253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mVgwEWqV1/QLEQ3WdNfF1TarAqhtogY8yI7ZYRgdsLc=; b=VIQTiGRFBHa89JJk77fcoM96LBohuQmcvYyqiYiQ0ypG2WYkouuybQR5wcY5ltUp0C YlZcHAcrRTfXTG4CwmDG5HuHmfzo2rQSaKiaDfviqBBxm32Uh4xrt4oHe5G7VsvAD7Nr 6Tqcu5wSyTCu5F81Cg6QEuQlumxg2bttOz+l5vZwJbh9zSzoM8YVMYeNmrEvQRgVz2YV LtaulQ+6PGLLNJvbSNJekeAFJ3WPyv210VG7n4c576e8mFlxqDXwF5aKY6fzyALF1Tp/ BtP5vQO/cnFrwl8mSKGe0ymB+D4cYn+/SvHikRHqoEUw0b0DxoGyQoVVh3B9OIKsihxn hxeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687854253; x=1690446253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mVgwEWqV1/QLEQ3WdNfF1TarAqhtogY8yI7ZYRgdsLc=; b=ZUfVN9BJlcAWALZgsQ/BczK3ob6Jgpt3aheF+Ny/mfx12PTQ+72qOIu+1StM3bzdiJ id6wzqX76BJ6xpqY7VR+V4A+628pBB9F2awZdeAsHb8N4WfgincL/qltaLrHRFJUCg4F 15sE4nV/nbNHACtQx8ojLegLba3/PMrdbgIez80nMWRa5Ann/7sCQdP88TNy61i6Xx3p 3jJFSuIkysi2pPEGCrchap8e1gAGhpRag0EFSX+/ZiwRH1syNpiPgG97b9vMk3C5HTLX VtTWzSxXR8VFsQFCFuHkim8vA2moAT9oRqcCWAWN7et0cEl15z9m743PCxQh+pxtkRqw m2rQ== X-Gm-Message-State: AC+VfDwNvr/gHloRcdmsFIdQGpMTpdVnrqtcvNNIZdpU4JNOy7wNrfkY i9ktxgbucb00pssGLJbDag== X-Google-Smtp-Source: ACHHUZ5H7Tk/7UDpaGZFl4JT+tAMpcCS1R68o2Hmq3AzZyGcLoFGEc5p8iV9eMGdnaX1oqvQKMMu0g== X-Received: by 2002:a05:6512:15aa:b0:4fb:74d6:6154 with SMTP id bp42-20020a05651215aa00b004fb74d66154mr3569982lfb.37.1687854253119; Tue, 27 Jun 2023 01:24:13 -0700 (PDT) Received: from localhost.localdomain (mail.pulsar-telecom.ru. [94.181.180.60]) by smtp.gmail.com with ESMTPSA id i12-20020a056512006c00b004eb12329053sm1420673lfo.256.2023.06.27.01.24.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 01:24:12 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Greg Kroah-Hartman , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v3 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support Date: Tue, 27 Jun 2023 11:23:25 +0300 Message-Id: <20230627082334.1253020-3-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230627082334.1253020-1-privatesub2@gmail.com> References: <20230627082334.1253020-1-privatesub2@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230627_012417_547286_FA6A039E X-CRM114-Status: GOOD ( 31.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Allwinner's D1, T113-S3 and R329 SoCs have a quite different PWM controllers with ones supported by pwm-sun4i driver. This patch adds a PWM controller driver for Allwinner's D1, T113-S3 and R329 SoCs. The main difference between these SoCs is the number of channels defined by the DT property. Signed-off-by: Aleksandr Shubin --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sun20i.c | 322 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 333 insertions(+) create mode 100644 drivers/pwm/pwm-sun20i.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8df861b1f4a3..05c48a36969e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -594,6 +594,16 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. +config PWM_SUN20I + tristate "Allwinner D1/T113s/R329 PWM support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on COMMON_CLK + help + Generic PWM framework driver for Allwinner D1/T113s/R329 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sun20i. + config PWM_SUNPLUS tristate "Sunplus PWM support" depends on ARCH_SUNPLUS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 19899b912e00..cea872e22c78 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o +obj-$(CONFIG_PWM_SUN20I) += pwm-sun20i.o obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o diff --git a/drivers/pwm/pwm-sun20i.c b/drivers/pwm/pwm-sun20i.c new file mode 100644 index 000000000000..63e9c64e0e18 --- /dev/null +++ b/drivers/pwm/pwm-sun20i.c @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM Controller Driver for sunxi platforms (D1, T113-S3 and R329) + * + * Limitations: + * - When the parameters change, current running period will not be completed + * and run new settings immediately. + * - It output HIGH-Z state when PWM channel disabled. + * + * Copyright (c) 2023 Aleksandr Shubin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_CLK_CFG_REG(chan) (0x20 + (((chan) >> 1) * 0x4)) +#define PWM_CLK_SRC GENMASK(8, 7) +#define PWM_CLK_DIV_M GENMASK(3, 0) + +#define PWM_CLK_GATE_REG 0x40 +#define PWM_CLK_BYPASS(chan) BIT((chan) - 16) +#define PWM_CLK_GATING(chan) BIT(chan) + +#define PWM_ENABLE_REG 0x80 +#define PWM_EN(chan) BIT(chan) + +#define PWM_CTL_REG(chan) (0x100 + (chan) * 0x20) +#define PWM_ACT_STA BIT(8) +#define PWM_PRESCAL_K GENMASK(7, 0) + +#define PWM_PERIOD_REG(chan) (0x104 + (chan) * 0x20) +#define PWM_ENTIRE_CYCLE GENMASK(31, 16) +#define PWM_ACT_CYCLE GENMASK(15, 0) + +struct sun20i_pwm_chip { + struct pwm_chip chip; + struct clk *clk_bus, *clk_hosc; + struct reset_control *rst; + void __iomem *base; + /* Mutex to protect pwm apply state */ + struct mutex mutex; +}; + +static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct sun20i_pwm_chip, chip); +} + +static inline u32 sun20i_pwm_readl(struct sun20i_pwm_chip *chip, + unsigned long offset) +{ + return readl(chip->base + offset); +} + +static inline void sun20i_pwm_writel(struct sun20i_pwm_chip *chip, + u32 val, unsigned long offset) +{ + writel(val, chip->base + offset); +} + +static int sun20i_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sun20i_pwm_chip *sun20i_chip = to_sun20i_pwm_chip(chip); + u64 clk_rate, tmp; + u32 val; + u16 ent_cycle, act_cycle; + u8 prescal, div_id; + + mutex_lock(&sun20i_chip->mutex); + + val = sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG_REG(pwm->hwpwm)); + div_id = FIELD_GET(PWM_CLK_DIV_M, val); + if (FIELD_GET(PWM_CLK_SRC, val) == 0) + clk_rate = clk_get_rate(sun20i_chip->clk_hosc); + else + clk_rate = clk_get_rate(sun20i_chip->clk_bus); + + val = sun20i_pwm_readl(sun20i_chip, PWM_CTL_REG(pwm->hwpwm)); + state->polarity = (PWM_ACT_STA & val) ? PWM_POLARITY_NORMAL : PWM_POLARITY_INVERSED; + + prescal = FIELD_GET(PWM_PRESCAL_K, val) + 1; + + val = sun20i_pwm_readl(sun20i_chip, PWM_ENABLE_REG); + state->enabled = (PWM_EN(pwm->hwpwm) & val) ? true : false; + + val = sun20i_pwm_readl(sun20i_chip, PWM_PERIOD_REG(pwm->hwpwm)); + act_cycle = FIELD_GET(PWM_ACT_CYCLE, val); + ent_cycle = FIELD_GET(PWM_ENTIRE_CYCLE, val); + if (act_cycle > ent_cycle) + act_cycle = ent_cycle; + + tmp = (u64)(act_cycle) * prescal * (1U << div_id) * NSEC_PER_SEC; + state->duty_cycle = DIV_ROUND_UP_ULL(tmp, clk_rate); + tmp = (u64)(ent_cycle) * prescal * (1U << div_id) * NSEC_PER_SEC; + state->period = DIV_ROUND_UP_ULL(tmp, clk_rate); + mutex_unlock(&sun20i_chip->mutex); + + return 0; +} + +static int sun20i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + int ret = 0; + u32 clk_gate, clk_cfg, pwm_en, ctl, period; + u64 bus_rate, hosc_rate, clk_div, val; + u16 prescaler, div_m; + bool use_bus_clk, calc_div_m; + struct sun20i_pwm_chip *sun20i_chip = to_sun20i_pwm_chip(chip); + + mutex_lock(&sun20i_chip->mutex); + + pwm_en = sun20i_pwm_readl(sun20i_chip, PWM_ENABLE_REG); + + if (state->enabled != pwm->state.enabled) + clk_gate = sun20i_pwm_readl(sun20i_chip, PWM_CLK_GATE_REG); + + if (state->enabled != pwm->state.enabled && !state->enabled) { + clk_gate &= ~PWM_CLK_GATING(pwm->hwpwm); + pwm_en &= ~PWM_EN(pwm->hwpwm); + sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE_REG); + sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE_REG); + } + + if (state->polarity != pwm->state.polarity || + state->duty_cycle != pwm->state.duty_cycle || + state->period != pwm->state.period) { + ctl = sun20i_pwm_readl(sun20i_chip, PWM_CTL_REG(pwm->hwpwm)); + clk_cfg = sun20i_pwm_readl(sun20i_chip, PWM_CLK_CFG_REG(pwm->hwpwm)); + hosc_rate = clk_get_rate(sun20i_chip->clk_hosc); + bus_rate = clk_get_rate(sun20i_chip->clk_bus); + if (pwm_en & PWM_EN(pwm->hwpwm ^ 1)) { + /* if the neighbor channel is enable, check period only */ + use_bus_clk = FIELD_GET(PWM_CLK_SRC, clk_cfg) != 0; + if (use_bus_clk) + val = state->period * bus_rate; + else + val = state->period * hosc_rate; + do_div(val, NSEC_PER_SEC); + + div_m = FIELD_GET(PWM_CLK_DIV_M, clk_cfg); + calc_div_m = false; + } else { + /* check period and select clock source */ + use_bus_clk = false; + val = state->period * hosc_rate; + do_div(val, NSEC_PER_SEC); + if (val <= 1) { + use_bus_clk = true; + val = state->period * bus_rate; + do_div(val, NSEC_PER_SEC); + if (val <= 1) { + ret = -EINVAL; + goto unlock_mutex; + } + } + div_m = 0; + calc_div_m = true; + + /* set up the CLK_DIV_M and clock CLK_SRC */ + clk_cfg = FIELD_PREP(PWM_CLK_DIV_M, div_m); + clk_cfg |= FIELD_PREP(PWM_CLK_SRC, use_bus_clk ? 1 : 0); + + sun20i_pwm_writel(sun20i_chip, clk_cfg, PWM_CLK_CFG_REG(pwm->hwpwm)); + } + + /* calculate prescaler, M factor, PWM entire cycle */ + clk_div = val; + for (prescaler = 0;; prescaler++) { + if (prescaler >= 256) { + if (calc_div_m) { + prescaler = 0; + div_m++; + if (div_m >= 9) { + ret = -EINVAL; + goto unlock_mutex; + } + } else { + ret = -EINVAL; + goto unlock_mutex; + } + } + + clk_div = val >> div_m; + do_div(clk_div, prescaler + 1); + if (clk_div <= 65534) + break; + } + + period = FIELD_PREP(PWM_ENTIRE_CYCLE, clk_div); + + /* set duty cycle */ + if (use_bus_clk) + val = state->duty_cycle * bus_rate; + else + val = state->duty_cycle * hosc_rate; + do_div(val, NSEC_PER_SEC); + clk_div = val >> div_m; + do_div(clk_div, prescaler + 1); + + if (state->duty_cycle == state->period) + clk_div++; + period |= FIELD_PREP(PWM_ACT_CYCLE, clk_div); + sun20i_pwm_writel(sun20i_chip, period, PWM_PERIOD_REG(pwm->hwpwm)); + + ctl = FIELD_PREP(PWM_PRESCAL_K, prescaler); + if (state->polarity == PWM_POLARITY_NORMAL) + ctl |= PWM_ACT_STA; + + sun20i_pwm_writel(sun20i_chip, ctl, PWM_CTL_REG(pwm->hwpwm)); + } + + if (state->enabled != pwm->state.enabled && state->enabled) { + clk_gate &= ~PWM_CLK_BYPASS(pwm->hwpwm); + clk_gate |= PWM_CLK_GATING(pwm->hwpwm); + pwm_en |= PWM_EN(pwm->hwpwm); + sun20i_pwm_writel(sun20i_chip, pwm_en, PWM_ENABLE_REG); + sun20i_pwm_writel(sun20i_chip, clk_gate, PWM_CLK_GATE_REG); + } + +unlock_mutex: + mutex_unlock(&sun20i_chip->mutex); + + return ret; +} + +static const struct pwm_ops sun20i_pwm_ops = { + .get_state = sun20i_pwm_get_state, + .apply = sun20i_pwm_apply, + .owner = THIS_MODULE, +}; + +static const struct of_device_id sun20i_pwm_dt_ids[] = { + { .compatible = "allwinner,sun20i-d1-pwm" }, + { }, +}; +MODULE_DEVICE_TABLE(of, sun20i_pwm_dt_ids); + +static int sun20i_pwm_probe(struct platform_device *pdev) +{ + struct sun20i_pwm_chip *sun20i_chip; + int ret; + + sun20i_chip = devm_kzalloc(&pdev->dev, sizeof(*sun20i_chip), GFP_KERNEL); + if (!sun20i_chip) + return -ENOMEM; + + sun20i_chip->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sun20i_chip->base)) + return PTR_ERR(sun20i_chip->base); + + sun20i_chip->clk_bus = devm_clk_get_enabled(&pdev->dev, "bus"); + if (IS_ERR(sun20i_chip->clk_bus)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_bus), + "failed to get bus clock\n"); + + sun20i_chip->clk_hosc = devm_clk_get_enabled(&pdev->dev, "hosc"); + if (IS_ERR(sun20i_chip->clk_hosc)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_hosc), + "failed to get hosc clock\n"); + + sun20i_chip->rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(sun20i_chip->rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->rst), + "failed to get bus reset\n"); + + ret = of_property_read_u32(pdev->dev.of_node, "allwinner,pwm-channels", + &sun20i_chip->chip.npwm); + if (ret) + sun20i_chip->chip.npwm = 8; + + /* Deassert reset */ + ret = reset_control_deassert(sun20i_chip->rst); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to deassert reset\n"); + + sun20i_chip->chip.dev = &pdev->dev; + sun20i_chip->chip.ops = &sun20i_pwm_ops; + + mutex_init(&sun20i_chip->mutex); + + ret = pwmchip_add(&sun20i_chip->chip); + if (ret < 0) { + reset_control_assert(sun20i_chip->rst); + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); + } + + platform_set_drvdata(pdev, sun20i_chip); + + return 0; +} + +static void sun20i_pwm_remove(struct platform_device *pdev) +{ + struct sun20i_pwm_chip *sun20i_chip = platform_get_drvdata(pdev); + + pwmchip_remove(&sun20i_chip->chip); + + reset_control_assert(sun20i_chip->rst); +} + +static struct platform_driver sun20i_pwm_driver = { + .driver = { + .name = "sun20i-pwm", + .of_match_table = sun20i_pwm_dt_ids, + }, + .probe = sun20i_pwm_probe, + .remove_new = sun20i_pwm_remove, +}; +module_platform_driver(sun20i_pwm_driver); + +MODULE_AUTHOR("Aleksandr Shubin "); +MODULE_DESCRIPTION("Allwinner sun20i PWM driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Jun 27 08:23:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandr Shubin X-Patchwork-Id: 13294183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1027EB64D9 for ; Tue, 27 Jun 2023 08:24:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WPUWlrQPHxOgk0sVU6xTpsjHLCdfobkuQ/4OHTuKRhQ=; b=q110dj2u7ZIzVs YW/BO6AbeR71zr70ZWOg/0xo/xM1iZARkCCT3F22hkiuuGZDJjdhTWCyfoWRIlqMKpHTN2fKtrIKU 9iRrjpwG69TK832MNDVo4vtAViDFtLCzY1KHmx4T96Ip9/hT+WuM/llrN/f8LMDr8cAbwJPY73LHD 9HIxm03GVGUqsHIOpuCmVaVwJg8nkQC/KoxiSNN9qqOx2XjD9RoJFdsi69xQXAVUwgn4R34vqdHQj POwLcIooYsioPtIt9m2xk3T4CfYmxplMlq8Cb6dl6D2Tf5d/VoGMweK6gOSSPWMY4d6ef+WhGz1et 53s6cT8Ai+IYkVMPPqAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qE3zz-00CYoK-1S; Tue, 27 Jun 2023 08:24:31 +0000 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qE3zu-00CYlI-25; Tue, 27 Jun 2023 08:24:27 +0000 Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4f76a0a19d4so5798009e87.2; Tue, 27 Jun 2023 01:24:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687854265; x=1690446265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9pjgEmaLZWbZLKm+zTsTjeEOP7/LCJvRIUhdiZyAT1I=; b=TE7f+u5TbI/yG0U+0SyVxyNL4Hk/MPzSwlErkUfNEC8YTRK3M1Vh7mPhmv0rZ7kfQU eRR7Ws9gTUZrwfagnu/E8dW7m7MXunWK65JTfquV2cc9qrwQW9GAqTjFQ/sBJX/ptFFK p9Awmdhm1YRA+PHkhZwDZI2+y9MP6ZXjxD5pgJe/MN5RqTZsvtkZufqCVro47pOi1WjH t6wKmtgRLmGI322xF27HOIye6IcvL+bV0LnBKHknVOKOxDAC+tLsgqxWFGRXVehVaDvD RWxTDMdvb8628zNsTAS7lxudN343CwebXvd50Aox32mctKzNVLexHf6BPNPJ39cBB48T vc2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687854265; x=1690446265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9pjgEmaLZWbZLKm+zTsTjeEOP7/LCJvRIUhdiZyAT1I=; b=HirstDXTsOowa8FHPlCLsDeH4cB71bmuKWRnuJu0RGU1sIVK2sDbYE6lngUkefsyBW jfoxENJX9XbbDcJ8n6iBkpGoK3gDAoA1xOFNeAXaND1wcWSICUlcJ3szpP3IKZmZyHg7 sHo8JpbeP7XEwvftBw0JgvOWk8oNpe7shwAkndIZQU3X4x80nSK8Wcn6YEof8a1iuHmS Uz+I2Xy+/Rg/rOdjFXo8y7mFL+icQ4VjTwuUIWbLvjkdiA5iE54vuB0gRTceEq5DopwT n+ml+eVl9ieMkBWGS20Xgr/HryNVrWndgWq8KgMWIrJfXq008btaNIgx7EjOTxq4yhrd /8Qg== X-Gm-Message-State: AC+VfDxWUmFSE1K8iNiJAAVnm8QDgapYRBbc66KUaa8j/+2TvYq2hUn+ bBf7PIgxCkp5xSYZ5MPhBw== X-Google-Smtp-Source: ACHHUZ4vz531eTh8MoQqbWPlqMxY7J/X7ms73AZisnK4IJIfmP73nvAIsdUP/6rmmWoOTpA9+n88FQ== X-Received: by 2002:a19:434a:0:b0:4f8:6e1d:cf98 with SMTP id m10-20020a19434a000000b004f86e1dcf98mr13755647lfj.66.1687854264719; Tue, 27 Jun 2023 01:24:24 -0700 (PDT) Received: from localhost.localdomain (mail.pulsar-telecom.ru. [94.181.180.60]) by smtp.gmail.com with ESMTPSA id i12-20020a056512006c00b004eb12329053sm1420673lfo.256.2023.06.27.01.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 01:24:24 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Andre Przywara , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/3] riscv: dts: allwinner: d1: Add pwm node Date: Tue, 27 Jun 2023 11:23:26 +0300 Message-Id: <20230627082334.1253020-4-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230627082334.1253020-1-privatesub2@gmail.com> References: <20230627082334.1253020-1-privatesub2@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230627_012426_684374_EA36C131 X-CRM114-Status: GOOD ( 11.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org D1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun20i-pwm driver. Add a device tree node for it. Signed-off-by: Aleksandr Shubin --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 922e8e0e2c09..e24543b6aff7 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -127,6 +127,17 @@ uart3_pb_pins: uart3-pb-pins { }; }; + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, + <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + status = "disabled"; + #pwm-cells = <0x3>; + }; + ccu: clock-controller@2001000 { compatible = "allwinner,sun20i-d1-ccu"; reg = <0x2001000 0x1000>;