From patchwork Thu Jun 29 06:27:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= X-Patchwork-Id: 13296645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 554BCEB64D9 for ; Thu, 29 Jun 2023 06:27:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=mvPLhsFtem87T9hKxqJWP4/Po2YBkkw89S7ILJdVcJQ=; b=AZzTNE/HCV9bbV EtpC998XgW8gxGJx/23EF3ibU9gPKZBX+5jWdrzdW7YbCF6Ytcuq+AfdDMU4EiakmYOYaK2bk6Qu/ QpZ2mN6JHIhNWez+0We4pimXjlP+b3u2sAN+RuP8NU7HpUqXdIvpblzTaY3lsOihCgcV10ZoFXkVx Etay/fEKdnap7JhLvoDGPeXgTUWRpx8gD2mnyDo3pJHyhqARzgb+HFI220mdMlDJt0HROmPXl4L2Z Iyn4G8obn3xUbnUkrprYZx8YdQdl9TppziIJ6F7lbOoDeMxZTvtEl7YbVEvKnOZtF17zmiY3VMM8M KxKnhVgSDwjvVmhhNB4Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qEl82-0006KE-0C; Thu, 29 Jun 2023 06:27:42 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qEl7y-0006JF-2P for linux-riscv@lists.infradead.org; Thu, 29 Jun 2023 06:27:40 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4470A61492; Thu, 29 Jun 2023 06:27:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 299C7C433C8; Thu, 29 Jun 2023 06:27:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1688020057; bh=YQhuBQ3j9NEc7Bo7uyfWxsU+RoSkYIM6Un+O+o02yNs=; h=From:To:Cc:Subject:Date:From; b=cP051lzRT7C0TFbto2MNtQweDI2SV7bTfB3NWG1Z/1EupqLqJ/CaA3IX1ktNKgb33 YUvDm45rLg6NfT1gpm2ur6hJWTGvVbqUHdrpJ4zXqLIzMhaRk33/HZzkTkxOzRWFK8 42BOLaDhgD1s37sWxWV3TtwtFvyzPm9IBgrhWywoT8pUnD52ECgcBZ/jyzozJSrRIy 4S2S4/JrHdwSe2cvBaARUn/L74WIL58VVxNfB4sb/BIvO3rhlg7Xa29kmeSISaqe/Q BEbbdPW+IcUa+n0ir3tldKu/VDDytX5Ay9l+j3ueELp/hWspZ5J4pYmdy5bZw1IOXS 9DmFiTgRVP/5A== From: =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, Andy Chiu Cc: =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , linux-kernel@vger.kernel.org, linux@rivosinc.com, Palmer Dabbelt , =?utf-8?q?R=C3=A9mi_Denis-Courmont?= , Darius Rad Subject: [PATCH v3] riscv: Discard vector state on syscalls Date: Thu, 29 Jun 2023 08:27:30 +0200 Message-Id: <20230629062730.985184-1-bjorn@kernel.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230628_232738_861146_F812EEB3 X-CRM114-Status: GOOD ( 11.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Björn Töpel The RISC-V vector specification states: Executing a system call causes all caller-saved vector registers (v0-v31, vl, vtype) and vstart to become unspecified. The vector registers are set to all 1s, vill is set (invalid), and the vector status is set to Dirty. That way we can prevent userspace from accidentally relying on the stated save. Rémi pointed out [1] that writing to the registers might be superfluous, and setting vill is sufficient. Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1] Suggested-by: Darius Rad Suggested-by: Palmer Dabbelt Suggested-by: Rémi Denis-Courmont Signed-off-by: Björn Töpel --- v2->v3: Set state to Dirty after discard, for proper ptrace() handling (Andy) v1->v2: Proper register restore for initial state (Andy) Set registers to 1s, and not 0s (Darius) --- arch/riscv/include/asm/vector.h | 33 +++++++++++++++++++++++++++++++++ arch/riscv/kernel/traps.c | 2 ++ 2 files changed, 35 insertions(+) base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3 diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 04c0b07bf6cd..0b23056503c5 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -33,6 +33,11 @@ static inline void __riscv_v_vstate_clean(struct pt_regs *regs) regs->status = (regs->status & ~SR_VS) | SR_VS_CLEAN; } +static inline void __riscv_v_vstate_dirty(struct pt_regs *regs) +{ + regs->status = (regs->status & ~SR_VS) | SR_VS_DIRTY; +} + static inline void riscv_v_vstate_off(struct pt_regs *regs) { regs->status = (regs->status & ~SR_VS) | SR_VS_OFF; @@ -128,6 +133,34 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_disable(); } +static inline void __riscv_v_vstate_discard(void) +{ + unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1); + + riscv_v_enable(); + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vmv.v.i v0, -1\n\t" + "vmv.v.i v8, -1\n\t" + "vmv.v.i v16, -1\n\t" + "vmv.v.i v24, -1\n\t" + "vsetvl %0, x0, %1\n\t" + ".option pop\n\t" + : "=&r" (vl) : "r" (vtype_inval) : "memory"); + riscv_v_disable(); +} + +static inline void riscv_v_vstate_discard(struct pt_regs *regs) +{ + if ((regs->status & SR_VS) == SR_VS_OFF) + return; + + __riscv_v_vstate_discard(); + __riscv_v_vstate_dirty(regs); +} + static inline void riscv_v_vstate_save(struct task_struct *task, struct pt_regs *regs) { diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 5158961ea977..5ff63a784a6d 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -296,6 +296,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) regs->epc += 4; regs->orig_a0 = regs->a0; + riscv_v_vstate_discard(regs); + syscall = syscall_enter_from_user_mode(regs, syscall); if (syscall < NR_syscalls)