From patchwork Thu Jun 29 20:11:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13297286 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7E7BEB64DD for ; Thu, 29 Jun 2023 20:12:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.557071.870110 (Exim 4.92) (envelope-from ) id 1qExzM-0005sw-Tg; Thu, 29 Jun 2023 20:11:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 557071.870110; Thu, 29 Jun 2023 20:11:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzM-0005sp-Qt; Thu, 29 Jun 2023 20:11:36 +0000 Received: by outflank-mailman (input) for mailman id 557071; Thu, 29 Jun 2023 20:11:35 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzL-0005dv-EL for xen-devel@lists.xenproject.org; Thu, 29 Jun 2023 20:11:35 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzL-0006l4-7y; Thu, 29 Jun 2023 20:11:35 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qExzK-0000KI-Vw; Thu, 29 Jun 2023 20:11:35 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=M6dL6+xvQ08WsYJRT4gNYr41k53D+4zoHoNEXSx9M1c=; b=s9pmGW+Ymm5wP8Q1LWJeF6zT3u 2YvTX51hdiRO9hoY/pkxfrIeVMSRGCCOwd3aakXWEe+4LOLZgqYD0B6Wxu9xoILsKQXWIH+6Ht+WG Q2vLD9CWYTlv/V3m7R+J4mJ+xsTiKkucOUnNbeZJ94XrhBkqBUcbKm9VrliD51Um1J/o=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall Subject: [v2 1/4] xen/arm64: head: Don't map too much in boot_third Date: Thu, 29 Jun 2023 21:11:26 +0100 Message-Id: <20230629201129.12934-2-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629201129.12934-1-julien@xen.org> References: <20230629201129.12934-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall At the moment, we are mapping the size of the reserved area for Xen (i.e. 2MB) even if the binary is smaller. We don't exactly know what's after Xen, so it is not a good idea to map more than necessary for a couple of reasons: * We would need to use break-before-make if the extra PTE needs to be updated to point to another region * The extra area mapped may be mapped again by Xen with different memory attribute. This would result to attribute mismatch. Therefore, rework the logic in create_page_tables() to map only what's necessary. To simplify the logic, we also want to make sure _end is page-aligned. So align the symbol in the linker and add an assert to catch any change. Lastly, take the opportunity to confirm that _start is equal to XEN_VIRT_START as the assembly is using both interchangeably. Signed-off-by: Julien Grall Reviewed-by: Henry Wang Reviewed-by: Michal Orzel Reviewed-by: Bertrand Marquis --- Changes in v2: - Fix typo and coding style - Check _start == XEN_VIRT_START --- xen/arch/arm/arm64/head.S | 15 ++++++++++++++- xen/arch/arm/xen.lds.S | 9 +++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index c0e03755bb10..5e9562a22240 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -572,6 +572,19 @@ create_page_tables: create_table_entry boot_first, boot_second, x0, 1, x1, x2, x3 create_table_entry boot_second, boot_third, x0, 2, x1, x2, x3 + /* + * Find the size of Xen in pages and multiply by the size of a + * PTE. This will then be compared in the mapping loop below. + * + * Note the multiplication is just to avoid using an extra + * register/instruction per iteration. + */ + ldr x0, =_start /* x0 := vaddr(_start) */ + ldr x1, =_end /* x1 := vaddr(_end) */ + sub x0, x1, x0 /* x0 := effective size of Xen */ + lsr x0, x0, #PAGE_SHIFT /* x0 := Number of pages for Xen */ + lsl x0, x0, #3 /* x0 := Number of pages * PTE size */ + /* Map Xen */ adr_l x4, boot_third @@ -585,7 +598,7 @@ create_page_tables: 1: str x2, [x4, x1] /* Map vaddr(start) */ add x2, x2, #PAGE_SIZE /* Next page */ add x1, x1, #8 /* Next slot */ - cmp x1, #(XEN_PT_LPAE_ENTRIES<<3) /* 512 entries per page */ + cmp x1, x0 /* Loop until we map all of Xen */ b.lt 1b /* diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index d36b67708ab1..a3c90ca82316 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -212,6 +212,7 @@ SECTIONS . = ALIGN(POINTER_ALIGN); __bss_end = .; } :text + . = ALIGN(PAGE_SIZE); _end = . ; /* Section for the device tree blob (if any). */ @@ -226,6 +227,12 @@ SECTIONS ELF_DETAILS_SECTIONS } +/* + * The assembly code use _start and XEN_VIRT_START interchangeably to + * match the context. + */ +ASSERT(_start == XEN_VIRT_START, "_start != XEN_VIRT_START") + /* * We require that Xen is loaded at a page boundary, so this ensures that any * code running on the identity map cannot cross a section boundary. @@ -241,4 +248,6 @@ ASSERT(IS_ALIGNED(__init_begin, 4), "__init_begin is misaligned") ASSERT(IS_ALIGNED(__init_end, 4), "__init_end is misaligned") ASSERT(IS_ALIGNED(__bss_start, POINTER_ALIGN), "__bss_start is misaligned") ASSERT(IS_ALIGNED(__bss_end, POINTER_ALIGN), "__bss_end is misaligned") +/* To simplify the logic in head.S, we want to _end to be page aligned */ +ASSERT(IS_ALIGNED(_end, PAGE_SIZE), "_end is not page aligned") ASSERT((_end - _start) <= XEN_VIRT_SIZE, "Xen is too big") From patchwork Thu Jun 29 20:11:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13297284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CAFDEB64DD for ; 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Thu, 29 Jun 2023 20:11:36 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qExzL-0000KI-SW; Thu, 29 Jun 2023 20:11:36 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=E0WEULIH7RKlj8ag6umBkV++f/zxydmEZbbsLJob028=; b=hOoV+7GxYhfQWP2/hhMX5h/ZAj sZ2e3BkFuGve2UvNM9ypBgS2PvqyOkG170PkinZQ0knEMO/hWpf9HtK69rNnvBbVO98+x+cGb16xT oz74dMXH6TdVwMBa4WFYBuezAL/SGTwa7LHZVzr0teiZrFHXpXd470E1aMriWkZOZAp4=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall Subject: [v2 2/4] xen/arm32: head: Don't map too much in boot_third Date: Thu, 29 Jun 2023 21:11:27 +0100 Message-Id: <20230629201129.12934-3-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629201129.12934-1-julien@xen.org> References: <20230629201129.12934-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall At the moment, we are mapping the size of the reserved area for Xen (i.e. 2MB) even if the binary is smaller. We don't exactly know what's after Xen, so it is not a good idea to map more than necessary for a couple of reasons: * We would need to use break-before-make if the extra PTE needs to be updated to point to another region * The extra area mapped may be mapped again by Xen with different memory attribute. This would result to attribute mismatch. Therefore, rework the logic in create_page_tables() to map only what's necessary. To simplify the logic, we also want to make sure _end is page-aligned. So align the symbol in the linker and add an assert to catch any change. Signed-off-by: Julien Grall Reviewed-by: Michal Orzel Reviewed-by: Henry Wang Reviewed-by: Bertrand Marquis --- Changes in v2: - Fix typo - Add Michal's reviewed-by tag --- xen/arch/arm/arm32/head.S | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 1ad981b67460..5e3692eb3abf 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -459,6 +459,19 @@ create_page_tables: create_table_entry boot_pgtable, boot_second, r0, 1 create_table_entry boot_second, boot_third, r0, 2 + /* + * Find the size of Xen in pages and multiply by the size of a + * PTE. This will then be compared in the mapping loop below. + * + * Note the multiplication is just to avoid using an extra + * register/instruction per iteration. + */ + mov_w r0, _start /* r0 := vaddr(_start) */ + mov_w r1, _end /* r1 := vaddr(_end) */ + sub r0, r1, r0 /* r0 := effective size of Xen */ + lsr r0, r0, #PAGE_SHIFT /* r0 := Number of pages for Xen */ + lsl r0, r0, #3 /* r0 := Number of pages * PTE size */ + /* Setup boot_third: */ adr_l r4, boot_third @@ -473,7 +486,7 @@ create_page_tables: 1: strd r2, r3, [r4, r1] /* Map vaddr(start) */ add r2, r2, #PAGE_SIZE /* Next page */ add r1, r1, #8 /* Next slot */ - cmp r1, #(XEN_PT_LPAE_ENTRIES<<3) /* 512*8-byte entries per page */ + cmp r1, r0 /* Loop until we map all of Xen */ blo 1b /* From patchwork Thu Jun 29 20:11:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13297285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3472EB64D9 for ; Thu, 29 Jun 2023 20:12:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.557073.870125 (Exim 4.92) (envelope-from ) id 1qExzO-0006AY-FP; Thu, 29 Jun 2023 20:11:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 557073.870125; Thu, 29 Jun 2023 20:11:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzO-0006A6-92; Thu, 29 Jun 2023 20:11:38 +0000 Received: by outflank-mailman (input) for mailman id 557073; Thu, 29 Jun 2023 20:11:37 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzN-00060s-7L for xen-devel@lists.xenproject.org; Thu, 29 Jun 2023 20:11:37 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzN-0006lQ-3S; Thu, 29 Jun 2023 20:11:37 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qExzM-0000KI-PA; Thu, 29 Jun 2023 20:11:37 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=Zgzk7zn0RDSvuGHlpIz7mQ/VwFGZ850f+cML2adUXv0=; b=FJ60LX9iKISlp/h/7knZyJXVi1 MnLfFUczLYxZPUO0RKeJSE0o+JM7eyTAwG3abcAk86lJVprwv4FlcfR4zHLiUQCaB5bIWEcCsepZP JNzVzaBCPFCUAb1sevGQbrdI0g1HYTasZnMALCXLOjk7ZZv+/QPHc+dOowTy+L2FVo/c=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall Subject: [v2 3/4] xen/arm: Rework the code mapping Xen to avoid relying on the size of Xen Date: Thu, 29 Jun 2023 21:11:28 +0100 Message-Id: <20230629201129.12934-4-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629201129.12934-1-julien@xen.org> References: <20230629201129.12934-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall At the moment, the maximum size of Xen binary we can support is 2MB. This is what we reserved in the virtual address but also what all the code in Xen relies on as we only allocate one L3 page-table. When feature like UBSAN (will be enabled in a follow-up patch) and GCOV are enabled, the binary will be way over 2MB. The code is now reworked so it doesn't rely on a specific size but will instead look at the reversed size and compute the number of page-table to allocate/map. While at it, replace any reference to 4KB mappings with a more generic word because the page-size may change in the future. Also fix the typo s/tlb/tbl/ in code move in arm32/head.S Signed-off-by: Julien Grall Reviewed-by: Michal Orzel Reviewed-by: Bertrand Marquis --- Changes in v2: - Fix typoes - Remove comments that don't apply - Reword the explanation for DEFINE_BOOT_PAGE_TABLE{,S} - Be more consistent with the way to from the virtual address to map in mm.c --- xen/arch/arm/arm32/head.S | 64 +++++++++++++++++++++++-------- xen/arch/arm/arm64/head.S | 54 ++++++++++++++++++++------ xen/arch/arm/include/asm/config.h | 1 + xen/arch/arm/include/asm/lpae.h | 10 +++-- xen/arch/arm/mm.c | 24 +++++++----- 5 files changed, 110 insertions(+), 43 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 5e3692eb3abf..cfc542b55973 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -141,8 +141,7 @@ /* * This must be the very first address in the loaded image. * It should be linked at XEN_VIRT_START, and loaded at any - * 4K-aligned address. All of text+data+bss must fit in 2MB, - * or the initial pagetable code below will need adjustment. + * 4K-aligned address. */ GLOBAL(start) /* @@ -373,7 +372,35 @@ ENDPROC(cpu_init) .endm /* - * Macro to create a page table entry in \ptbl to \tbl + * Macro to create a page table entry in \ptbl to \tbl (physical + * address) + * + * ptbl: table symbol where the entry will be created + * tbl: physical address of the table to point to + * virt: virtual address + * lvl: page-table level + * + * Preserves \virt + * Clobbers \tbl, r1 - r3 + * + * Note that \tbl and \virt should be in a register other than r1 - r3 + */ +.macro create_table_entry_from_paddr, ptbl, tbl, virt, lvl + get_table_slot r1, \virt, \lvl /* r1 := slot in \tbl */ + lsl r1, r1, #3 /* r1 := slot offset in \tbl */ + + movw r2, #PT_PT /* r2:r3 := right for linear PT */ + orr r2, r2, \tbl /* + \tbl paddr */ + mov r3, #0 + + adr_l \tbl, \ptbl /* \tbl := (v,p)addr of \ptbl */ + + strd r2, r3, [\tbl, r1] +.endm + + +/* + * Macro to create a page table entry in \ptbl to \tbl (symbol) * * ptbl: table symbol where the entry will be created * tbl: table symbol to point to @@ -388,19 +415,9 @@ ENDPROC(cpu_init) * Note that \virt should be in a register other than r1 - r4 */ .macro create_table_entry, ptbl, tbl, virt, lvl - get_table_slot r1, \virt, \lvl /* r1 := slot in \tlb */ - lsl r1, r1, #3 /* r1 := slot offset in \tlb */ - load_paddr r4, \tbl - - movw r2, #PT_PT /* r2:r3 := right for linear PT */ - orr r2, r2, r4 /* + \tlb paddr */ - mov r3, #0 - - adr_l r4, \ptbl - - strd r2, r3, [r4, r1] -.endm + create_table_entry_from_paddr \ptbl, r4, \virt, \lvl + .endm /* * Macro to create a mapping entry in \tbl to \paddr. Only mapping in 3rd @@ -451,13 +468,26 @@ ENDPROC(cpu_init) * Output: * r12: Was a temporary mapping created? * - * Clobbers r0 - r4 + * Clobbers r0 - r5 */ create_page_tables: /* Prepare the page-tables for mapping Xen */ mov_w r0, XEN_VIRT_START create_table_entry boot_pgtable, boot_second, r0, 1 - create_table_entry boot_second, boot_third, r0, 2 + + /* + * We need to use a stash register because + * create_table_entry_paddr() will clobber the register storing + * the physical address of the table to point to. + */ + load_paddr r5, boot_third + mov_w r4, XEN_VIRT_START +.rept XEN_NR_ENTRIES(2) + mov r0, r5 /* r0 := paddr(l3 table) */ + create_table_entry_from_paddr boot_second, r0, r4, 2 + add r4, r4, #XEN_PT_LEVEL_SIZE(2) /* r4 := Next vaddr */ + add r5, r5, #PAGE_SIZE /* r5 := Next table */ +.endr /* * Find the size of Xen in pages and multiply by the size of a diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 5e9562a22240..ad9e0ba87a29 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -146,8 +146,7 @@ * * This must be the very first address in the loaded image. * It should be linked at XEN_VIRT_START, and loaded at any - * 4K-aligned address. All of text+data+bss must fit in 2MB, - * or the initial pagetable code below will need adjustment. + * 4K-aligned address. */ GLOBAL(start) @@ -490,6 +489,31 @@ ENDPROC(cpu_init) ubfx \slot, \virt, #XEN_PT_LEVEL_SHIFT(\lvl), #XEN_PT_LPAE_SHIFT .endm +/* + * Macro to create a page table entry in \ptbl to \tbl + * ptbl: table symbol where the entry will be created + * tbl: physical address of the table to point to + * virt: virtual address + * lvl: page-table level + * tmp1: scratch register + * tmp2: scratch register + * + * Preserves \virt + * Clobbers \tbl, \tmp1, \tmp2 + * + * Note that all parameters using registers should be distinct. + */ +.macro create_table_entry_from_paddr, ptbl, tbl, virt, lvl, tmp1, tmp2 + get_table_slot \tmp1, \virt, \lvl /* \tmp1 := slot in \tbl */ + + mov \tmp2, #PT_PT /* \tmp2 := right for linear PT */ + orr \tmp2, \tmp2, \tbl /* + \tbl */ + + adr_l \tbl, \ptbl /* \tbl := address(\ptbl) */ + + str \tmp2, [\tbl, \tmp1, lsl #3] +.endm + /* * Macro to create a page table entry in \ptbl to \tbl * @@ -509,15 +533,8 @@ ENDPROC(cpu_init) * Note that all parameters using registers should be distinct. */ .macro create_table_entry, ptbl, tbl, virt, lvl, tmp1, tmp2, tmp3 - get_table_slot \tmp1, \virt, \lvl /* \tmp1 := slot in \tlb */ - - load_paddr \tmp2, \tbl - mov \tmp3, #PT_PT /* \tmp3 := right for linear PT */ - orr \tmp3, \tmp3, \tmp2 /* + \tlb paddr */ - - adr_l \tmp2, \ptbl - - str \tmp3, [\tmp2, \tmp1, lsl #3] + load_paddr \tmp1, \tbl + create_table_entry_from_paddr \ptbl, \tmp1, \virt, \lvl, \tmp2, \tmp3 .endm /* @@ -570,7 +587,20 @@ create_page_tables: ldr x0, =XEN_VIRT_START create_table_entry boot_pgtable, boot_first, x0, 0, x1, x2, x3 create_table_entry boot_first, boot_second, x0, 1, x1, x2, x3 - create_table_entry boot_second, boot_third, x0, 2, x1, x2, x3 + + /* + * We need to use a stash register because + * create_table_entry_paddr() will clobber the register storing + * the physical address of the table to point to. + */ + load_paddr x4, boot_third + ldr x1, =XEN_VIRT_START +.rept XEN_NR_ENTRIES(2) + mov x0, x4 /* x0 := paddr(l3 table) */ + create_table_entry_from_paddr boot_second, x0, x1, 2, x2, x3 + add x1, x1, #XEN_PT_LEVEL_SIZE(2) /* x1 := Next vaddr */ + add x4, x4, #PAGE_SIZE /* x4 := Next table */ +.endr /* * Find the size of Xen in pages and multiply by the size of a diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/config.h index c969e6da589d..6d246ab23c48 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -125,6 +125,7 @@ #endif #define XEN_VIRT_SIZE _AT(vaddr_t, MB(2)) +#define XEN_NR_ENTRIES(lvl) (XEN_VIRT_SIZE / XEN_PT_LEVEL_SIZE(lvl)) #define FIXMAP_VIRT_START (XEN_VIRT_START + XEN_VIRT_SIZE) #define FIXMAP_VIRT_SIZE _AT(vaddr_t, MB(2)) diff --git a/xen/arch/arm/include/asm/lpae.h b/xen/arch/arm/include/asm/lpae.h index 7d2f6fd1bd5a..4a1679cb3334 100644 --- a/xen/arch/arm/include/asm/lpae.h +++ b/xen/arch/arm/include/asm/lpae.h @@ -267,15 +267,17 @@ lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned int attr); /* * Macros to define page-tables: - * - DEFINE_BOOT_PAGE_TABLE is used to define page-table that are used - * in assembly code before BSS is zeroed. + * - DEFINE_BOOT_PAGE_TABLE{,S} are used to define one or multiple + * page-table that are used in assembly code before BSS is zeroed. * - DEFINE_PAGE_TABLE{,S} are used to define one or multiple * page-tables to be used after BSS is zeroed (typically they are only used * in C). */ -#define DEFINE_BOOT_PAGE_TABLE(name) \ +#define DEFINE_BOOT_PAGE_TABLES(name, nr) \ lpae_t __aligned(PAGE_SIZE) __section(".data.page_aligned") \ - name[XEN_PT_LPAE_ENTRIES] + name[XEN_PT_LPAE_ENTRIES * (nr)] + +#define DEFINE_BOOT_PAGE_TABLE(name) DEFINE_BOOT_PAGE_TABLES(name, 1) #define DEFINE_PAGE_TABLES(name, nr) \ lpae_t __aligned(PAGE_SIZE) name[XEN_PT_LPAE_ENTRIES * (nr)] diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 0a3e1f3b64b6..fff6d7a4d37a 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -53,8 +53,8 @@ mm_printk(const char *fmt, ...) {} * to the CPUs own pagetables. * * These pagetables have a very simple structure. They include: - * - 2MB worth of 4K mappings of xen at XEN_VIRT_START, boot_first and - * boot_second are used to populate the tables down to boot_third + * - XEN_VIRT_SIZE worth of L3 mappings of xen at XEN_VIRT_START, boot_first + * and boot_second are used to populate the tables down to boot_third * which contains the actual mapping. * - a 1:1 mapping of xen at its current physical address. This uses a * section mapping at whichever of boot_{pgtable,first,second} @@ -79,7 +79,7 @@ DEFINE_BOOT_PAGE_TABLE(boot_first_id); DEFINE_BOOT_PAGE_TABLE(boot_second_id); DEFINE_BOOT_PAGE_TABLE(boot_third_id); DEFINE_BOOT_PAGE_TABLE(boot_second); -DEFINE_BOOT_PAGE_TABLE(boot_third); +DEFINE_BOOT_PAGE_TABLES(boot_third, XEN_NR_ENTRIES(2)); /* Main runtime page tables */ @@ -115,7 +115,7 @@ DEFINE_BOOT_PAGE_TABLE(xen_fixmap); * Third level page table used to map Xen itself with the XN bit set * as appropriate. */ -static DEFINE_PAGE_TABLE(xen_xenmap); +static DEFINE_PAGE_TABLES(xen_xenmap, XEN_NR_ENTRIES(2)); /* Non-boot CPUs use this to find the correct pagetables. */ uint64_t init_ttbr; @@ -518,15 +518,15 @@ void __init setup_pagetables(unsigned long boot_phys_offset) p[0].pt.table = 1; p[0].pt.xn = 0; - /* Break up the Xen mapping into 4k pages and protect them separately. */ - for ( i = 0; i < XEN_PT_LPAE_ENTRIES; i++ ) + /* Break up the Xen mapping into pages and protect them separately. */ + for ( i = 0; i < XEN_NR_ENTRIES(3); i++ ) { vaddr_t va = XEN_VIRT_START + (i << PAGE_SHIFT); if ( !is_kernel(va) ) break; pte = pte_of_xenaddr(va); - pte.pt.table = 1; /* 4k mappings always have this bit set */ + pte.pt.table = 1; /* third level mappings always have this bit set */ if ( is_kernel_text(va) || is_kernel_inittext(va) ) { pte.pt.xn = 0; @@ -539,10 +539,14 @@ void __init setup_pagetables(unsigned long boot_phys_offset) /* Initialise xen second level entries ... */ /* ... Xen's text etc */ + for ( i = 0; i < XEN_NR_ENTRIES(2); i++ ) + { + vaddr_t va = XEN_VIRT_START + (i << XEN_PT_LEVEL_SHIFT(2)); - pte = pte_of_xenaddr((vaddr_t)xen_xenmap); - pte.pt.table = 1; - xen_second[second_table_offset(XEN_VIRT_START)] = pte; + pte = pte_of_xenaddr((vaddr_t)(xen_xenmap + i * XEN_PT_LPAE_ENTRIES)); + pte.pt.table = 1; + xen_second[second_table_offset(va)] = pte; + } /* ... Fixmap */ pte = pte_of_xenaddr((vaddr_t)xen_fixmap); From patchwork Thu Jun 29 20:11:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13297283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2440DC001B0 for ; Thu, 29 Jun 2023 20:11:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.557074.870134 (Exim 4.92) (envelope-from ) id 1qExzP-0006MX-19; Thu, 29 Jun 2023 20:11:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 557074.870134; Thu, 29 Jun 2023 20:11:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzO-0006LF-RH; Thu, 29 Jun 2023 20:11:38 +0000 Received: by outflank-mailman (input) for mailman id 557074; Thu, 29 Jun 2023 20:11:38 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzO-000686-4o for xen-devel@lists.xenproject.org; Thu, 29 Jun 2023 20:11:38 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qExzO-0006la-0K; Thu, 29 Jun 2023 20:11:38 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qExzN-0000KI-Ot; Thu, 29 Jun 2023 20:11:37 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=/jdx3egdYMGcVcThBa+BLos4+OXw1gDLyp5YfV1/oUM=; b=xaAZRgPF3+z/GpC7TjxSIseKlC 7t9Kd8yXMSvBP3u8WLx8NeQQI8KyIDSAgzdTFSUd2ioCwLszDafJ7ExldM7+wGTYYk/xIVUiIkTuf 0Dhc9EGq7wI6qh201tJc9addkPMXLKXACyUlbEfpLbzkKD97X+pErfe0ZtqlaC6ObmEc=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall Subject: [v2 4/4] xen/arm: Allow the user to build Xen with UBSAN Date: Thu, 29 Jun 2023 21:11:29 +0100 Message-Id: <20230629201129.12934-5-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629201129.12934-1-julien@xen.org> References: <20230629201129.12934-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall UBSAN has been enabled a few years ago on x86 but was never enabled on Arm because the final binary is bigger than 2MB ( the maximum we can currently handled). With the recent rework, it is now possible to grow Xen over 2MB. So there is no more roadblock to enable Xen other than increasing the reserved area. On my setup, for arm32, the final binaray was very close to 4MB. Furthermore, one may want to enable UBSAN and GCOV which would put the binary well-over 4MB (both features require for some space). Therefore, increase the size to 8MB which should us some margin. Signed-off-by: Julien Grall Reviewed-by: Henry Wang Reviewed-by: Michal Orzel Reviewed-by: Bertrand Marquis --- The drawback with this approach is that we are adding 6 new page-table (3 for boot and 3 for runtime) that are statically allocated. So the final Xen binary will be 24KB bigger when neither UBSAN nor GCOV. If this is not considered acceptable, then we could make the size of configurable in the Kconfig and decide it based on the features enabled. Changes in v2: - Fix typoes - Add Michal's reviewed-by tag - Add Henry's reviewed-by tag - Add a comment regarding the reserved size for Xen --- xen/arch/arm/Kconfig | 1 + xen/arch/arm/include/asm/config.h | 22 +++++++++++++--------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 61e581b8c2b0..06b5ff755c95 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -17,6 +17,7 @@ config ARM select HAS_PASSTHROUGH select HAS_PDX select HAS_PMAP + select HAS_UBSAN select IOMMU_FORCE_PT_SHARE config ARCH_DEFCONFIG diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/config.h index 6d246ab23c48..cc32802ad0e9 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -74,10 +74,10 @@ /* * ARM32 layout: * 0 - 2M Unmapped - * 2M - 4M Xen text, data, bss - * 4M - 6M Fixmap: special-purpose 4K mapping slots - * 6M - 10M Early boot mapping of FDT - * 10M - 12M Livepatch vmap (if compiled in) + * 2M - 10M Xen text, data, bss + * 10M - 12M Fixmap: special-purpose 4K mapping slots + * 12M - 16M Early boot mapping of FDT + * 16M - 18M Livepatch vmap (if compiled in) * * 32M - 128M Frametable: 32 bytes per page for 12GB of RAM * 256M - 1G VMAP: ioremap and early_ioremap use this virtual address @@ -94,10 +94,10 @@ * 0x0000020000000000 - 0x0000027fffffffff (512GB, L0 slot [4]) * (Relative offsets) * 0 - 2M Unmapped - * 2M - 4M Xen text, data, bss - * 4M - 6M Fixmap: special-purpose 4K mapping slots - * 6M - 10M Early boot mapping of FDT - * 10M - 12M Livepatch vmap (if compiled in) + * 2M - 10M Xen text, data, bss + * 10M - 12M Fixmap: special-purpose 4K mapping slots + * 12M - 16M Early boot mapping of FDT + * 16M - 18M Livepatch vmap (if compiled in) * * 1G - 2G VMAP: ioremap and early_ioremap * @@ -124,7 +124,11 @@ #define XEN_VIRT_START (SLOT0(4) + _AT(vaddr_t, MB(2))) #endif -#define XEN_VIRT_SIZE _AT(vaddr_t, MB(2)) +/* + * Reserve enough space so both UBSAN and GCOV can be enabled together + * plus some slack for future growth. + */ +#define XEN_VIRT_SIZE _AT(vaddr_t, MB(8)) #define XEN_NR_ENTRIES(lvl) (XEN_VIRT_SIZE / XEN_PT_LEVEL_SIZE(lvl)) #define FIXMAP_VIRT_START (XEN_VIRT_START + XEN_VIRT_SIZE)