From patchwork Fri Jun 30 16:58:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298504 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2350171A1 for ; Fri, 30 Jun 2023 16:58:42 +0000 (UTC) Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E7693C22 for ; Fri, 30 Jun 2023 09:58:39 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3142860734aso182807f8f.1 for ; Fri, 30 Jun 2023 09:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144318; x=1690736318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pvu4fKAQ0tzSA1HLZHWmdOfD3AhGAjrR/Ll1y4HIr3g=; b=ZTG7EzbzilkU/VviLIDwTWEYUHPmJtLqJjYxSV3Crq615ExbprUj2BN8OJSmeArQFf S4DI6Jee3wl8qluqpimjEqax9Jprf9zrbGxPl/1dcqB0bnr4+LR82ExG8EosLZaW7Swf 9kdI8Us2mkMkZtDtJRl8wvWhIlbkj7Kz/JIp8x0kSuFNgyZRRkaruRwmUXF6lLtoPjdO 1nzX6MnThrjiPQLiHrug4GQgWIKzfcZDFMn2qVQ9eEybKy4bfzKqx5VvsT2j630ZMecs b476DIyq7Gq13LdKVtaa/CCZWXUiJDTCakq6S7u6Nrg4hBgAIVS2FYW8TqM8XdG55BEL iNNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688144318; x=1690736318; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pvu4fKAQ0tzSA1HLZHWmdOfD3AhGAjrR/Ll1y4HIr3g=; b=QsdVMM6bPwmdYbKSXvsKyoVrLgvMiVizTBl707bNy39dcF2ebuT6Bk89z9r4bIBaah BM7Tp+kfv/2+bK6A0TNN0UARu1pyDVKhYLIQSl5qwcjH8kw19MdG3+7Q/9RjNOPVMYSR /SG7WQivvCiczzEQEquUfrYXCxH3dpKZc0qfhVw473Mdj8ZG4y+gj09ASYeTi3viZZcv 7PWeiqLqneVOQulCpsreqETpt1F9HlNEVkiXTT736ZS8cch6UF4kPPj2VS/X49eYm1Hy mkWpNCXyQQsKql1G4bv6M2l/ZrXCfCZKwK6wlSaJJe0ch8G85f57QN31PBo72MGHEOKx C+LQ== X-Gm-Message-State: AC+VfDyyNy5nQWnUDPw8Is2N+AMGlbkUe7HdDaueiHajfd8gu1eBpBEk PKMe7dRIPBR/XW9aM87D926sIw== X-Google-Smtp-Source: ACHHUZ5fJLXkeHDlekS99srv8CaNw+1WybS+1I3eAvpIdoFsONKseLREnwiIE5G4NEju+Wz8e4zHNQ== X-Received: by 2002:a5d:4bc3:0:b0:314:99e:af46 with SMTP id l3-20020a5d4bc3000000b00314099eaf46mr8051304wrt.20.1688144317723; Fri, 30 Jun 2023 09:58:37 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:58:37 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:26 +0200 Subject: [PATCH v2 01/15] clk: oxnas: remove obsolete clock driver Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-1-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9036; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=1hf999g5eEtxLqg8V04tUPdGH+Hq91QPzTw+uaq9mYk=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm0FtQDp9YXTDLZeHYHxn9vyusAxAx2Z1sd8aTE pfEkqtCJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtAAKCRB33NvayMhJ0SWoEA C1ki9NvMY6YAJTD7BcigSaZFUnNaU3bNIzzoTSAIyg+6TKBlDoXVdGwTbafVx6QhUhwNO3NhCK5A6a oyCqgHPD4lFTu9ROCWJ2CL278zqVx1VmcSa+uOlpzKK4YYEaWm3vsa7+U5iVGZ8UAOkHyXdnzO8s8w 1Dfqra3pX8U+bPlqDir97EjKWcfUDdAdzCU6sHYH2n3tQOnojyMSPnw0UwLguaknlzQjDPs029ARay XbH6olhY+PTxvnpFJw0Q5HqUuAv4X4Sq4cyUhfV2s/I9v+m0TAwMF+VVAVg1hmYOwWEhzkbiXYY1xg ehVEfeUKR3rsFfUMKYZsyfcHGfn9t+/OKBDm7Zr7tQ6x5e4WWB7R0DuWIdeMDAxJw7hkkP+i86lkor BKAR2oZiZpywLv+E9+kDhrys05V3s2hMWkjZcB54j5x75xihTEOkua+Wl3qE6PQIuvXbWzGychMmgA tBoNJApM2Rh8CFnosbeCabkduja6txGtKlOtxEoTmLmQIDe26HFznjp8yeBoqw9W5yUjj8W8GsTZZM EZ8nbLkV9nJjLOI47CzUJgQbQsZCHsILHByMA8g9mlLN9qs74x5fbf9RtEE9gwQqUTQbHb9eIKjXx7 3fMabs0tQEqq4OPYpGl4GAhLKjcbpCbtNATt6UR9Mu0l878Fs4XmAloBcWDw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 clock driver. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- drivers/clk/Kconfig | 7 -- drivers/clk/Makefile | 1 - drivers/clk/clk-oxnas.c | 251 ------------------------------------------------ 3 files changed, 259 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 93f38a8178ba..59a101e1cf65 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -360,13 +360,6 @@ config COMMON_CLK_PXA help Support for the Marvell PXA SoC. -config COMMON_CLK_OXNAS - bool "Clock driver for the OXNAS SoC Family" - depends on ARCH_OXNAS || COMPILE_TEST - select MFD_SYSCON - help - Support for the OXNAS SoC Family clocks. - config COMMON_CLK_RS9_PCIE tristate "Clock driver for Renesas 9-series PCIe clock generators" depends on I2C diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 7cb000549b61..94155999eba3 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o -obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c deleted file mode 100644 index 584e293156ad..000000000000 --- a/drivers/clk/clk-oxnas.c +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Broadcom - * Copyright (C) 2012 Stephen Warren - * Copyright (C) 2016 Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* Standard regmap gate clocks */ -struct clk_oxnas_gate { - struct clk_hw hw; - unsigned int bit; - struct regmap *regmap; -}; - -struct oxnas_stdclk_data { - struct clk_hw_onecell_data *onecell_data; - struct clk_oxnas_gate **gates; - unsigned int ngates; - struct clk_oxnas_pll **plls; - unsigned int nplls; -}; - -/* Regmap offsets */ -#define CLK_STAT_REGOFFSET 0x24 -#define CLK_SET_REGOFFSET 0x2c -#define CLK_CLR_REGOFFSET 0x30 - -static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw) -{ - return container_of(hw, struct clk_oxnas_gate, hw); -} - -static int oxnas_clk_gate_is_enabled(struct clk_hw *hw) -{ - struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw); - int ret; - unsigned int val; - - ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val); - if (ret < 0) - return ret; - - return val & BIT(std->bit); -} - -static int oxnas_clk_gate_enable(struct clk_hw *hw) -{ - struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw); - - regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit)); - - return 0; -} - -static void oxnas_clk_gate_disable(struct clk_hw *hw) -{ - struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw); - - regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit)); -} - -static const struct clk_ops oxnas_clk_gate_ops = { - .enable = oxnas_clk_gate_enable, - .disable = oxnas_clk_gate_disable, - .is_enabled = oxnas_clk_gate_is_enabled, -}; - -static const char *const osc_parents[] = { - "oscillator", -}; - -static const char *const eth_parents[] = { - "gmacclk", -}; - -#define OXNAS_GATE(_name, _bit, _parents) \ -struct clk_oxnas_gate _name = { \ - .bit = (_bit), \ - .hw.init = &(struct clk_init_data) { \ - .name = #_name, \ - .ops = &oxnas_clk_gate_ops, \ - .parent_names = _parents, \ - .num_parents = ARRAY_SIZE(_parents), \ - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ - }, \ -} - -static OXNAS_GATE(ox810se_leon, 0, osc_parents); -static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents); -static OXNAS_GATE(ox810se_cipher, 2, osc_parents); -static OXNAS_GATE(ox810se_sata, 4, osc_parents); -static OXNAS_GATE(ox810se_audio, 5, osc_parents); -static OXNAS_GATE(ox810se_usbmph, 6, osc_parents); -static OXNAS_GATE(ox810se_etha, 7, eth_parents); -static OXNAS_GATE(ox810se_pciea, 8, osc_parents); -static OXNAS_GATE(ox810se_nand, 9, osc_parents); - -static struct clk_oxnas_gate *ox810se_gates[] = { - &ox810se_leon, - &ox810se_dma_sgdma, - &ox810se_cipher, - &ox810se_sata, - &ox810se_audio, - &ox810se_usbmph, - &ox810se_etha, - &ox810se_pciea, - &ox810se_nand, -}; - -static OXNAS_GATE(ox820_leon, 0, osc_parents); -static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents); -static OXNAS_GATE(ox820_cipher, 2, osc_parents); -static OXNAS_GATE(ox820_sd, 3, osc_parents); -static OXNAS_GATE(ox820_sata, 4, osc_parents); -static OXNAS_GATE(ox820_audio, 5, osc_parents); -static OXNAS_GATE(ox820_usbmph, 6, osc_parents); -static OXNAS_GATE(ox820_etha, 7, eth_parents); -static OXNAS_GATE(ox820_pciea, 8, osc_parents); -static OXNAS_GATE(ox820_nand, 9, osc_parents); -static OXNAS_GATE(ox820_ethb, 10, eth_parents); -static OXNAS_GATE(ox820_pcieb, 11, osc_parents); -static OXNAS_GATE(ox820_ref600, 12, osc_parents); -static OXNAS_GATE(ox820_usbdev, 13, osc_parents); - -static struct clk_oxnas_gate *ox820_gates[] = { - &ox820_leon, - &ox820_dma_sgdma, - &ox820_cipher, - &ox820_sd, - &ox820_sata, - &ox820_audio, - &ox820_usbmph, - &ox820_etha, - &ox820_pciea, - &ox820_nand, - &ox820_etha, - &ox820_pciea, - &ox820_ref600, - &ox820_usbdev, -}; - -static struct clk_hw_onecell_data ox810se_hw_onecell_data = { - .hws = { - [CLK_810_LEON] = &ox810se_leon.hw, - [CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw, - [CLK_810_CIPHER] = &ox810se_cipher.hw, - [CLK_810_SATA] = &ox810se_sata.hw, - [CLK_810_AUDIO] = &ox810se_audio.hw, - [CLK_810_USBMPH] = &ox810se_usbmph.hw, - [CLK_810_ETHA] = &ox810se_etha.hw, - [CLK_810_PCIEA] = &ox810se_pciea.hw, - [CLK_810_NAND] = &ox810se_nand.hw, - }, - .num = ARRAY_SIZE(ox810se_gates), -}; - -static struct clk_hw_onecell_data ox820_hw_onecell_data = { - .hws = { - [CLK_820_LEON] = &ox820_leon.hw, - [CLK_820_DMA_SGDMA] = &ox820_dma_sgdma.hw, - [CLK_820_CIPHER] = &ox820_cipher.hw, - [CLK_820_SD] = &ox820_sd.hw, - [CLK_820_SATA] = &ox820_sata.hw, - [CLK_820_AUDIO] = &ox820_audio.hw, - [CLK_820_USBMPH] = &ox820_usbmph.hw, - [CLK_820_ETHA] = &ox820_etha.hw, - [CLK_820_PCIEA] = &ox820_pciea.hw, - [CLK_820_NAND] = &ox820_nand.hw, - [CLK_820_ETHB] = &ox820_ethb.hw, - [CLK_820_PCIEB] = &ox820_pcieb.hw, - [CLK_820_REF600] = &ox820_ref600.hw, - [CLK_820_USBDEV] = &ox820_usbdev.hw, - }, - .num = ARRAY_SIZE(ox820_gates), -}; - -static struct oxnas_stdclk_data ox810se_stdclk_data = { - .onecell_data = &ox810se_hw_onecell_data, - .gates = ox810se_gates, - .ngates = ARRAY_SIZE(ox810se_gates), -}; - -static struct oxnas_stdclk_data ox820_stdclk_data = { - .onecell_data = &ox820_hw_onecell_data, - .gates = ox820_gates, - .ngates = ARRAY_SIZE(ox820_gates), -}; - -static const struct of_device_id oxnas_stdclk_dt_ids[] = { - { .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data }, - { .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data }, - { } -}; - -static int oxnas_stdclk_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node, *parent_np; - const struct oxnas_stdclk_data *data; - struct regmap *regmap; - int ret; - int i; - - data = of_device_get_match_data(&pdev->dev); - - parent_np = of_get_parent(np); - regmap = syscon_node_to_regmap(parent_np); - of_node_put(parent_np); - if (IS_ERR(regmap)) { - dev_err(&pdev->dev, "failed to have parent regmap\n"); - return PTR_ERR(regmap); - } - - for (i = 0 ; i < data->ngates ; ++i) - data->gates[i]->regmap = regmap; - - for (i = 0; i < data->onecell_data->num; i++) { - if (!data->onecell_data->hws[i]) - continue; - - ret = devm_clk_hw_register(&pdev->dev, - data->onecell_data->hws[i]); - if (ret) - return ret; - } - - return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, - data->onecell_data); -} - -static struct platform_driver oxnas_stdclk_driver = { - .probe = oxnas_stdclk_probe, - .driver = { - .name = "oxnas-stdclk", - .suppress_bind_attrs = true, - .of_match_table = oxnas_stdclk_dt_ids, - }, -}; -builtin_platform_driver(oxnas_stdclk_driver); From patchwork Fri Jun 30 16:58:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298505 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2929C171B2 for ; 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Fri, 30 Jun 2023 09:58:38 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:27 +0200 Subject: [PATCH v2 02/15] dt-bindings: clk: oxnas: remove obsolete bindings Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-2-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Krzysztof Kozlowski , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1711; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=bzno7XM9r0SNC/gStJcrLz6bOxC+B4tnBfXrQVc4AKA=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm08GTlhXUvs7ni+2UnaR66va/P33VZvppd02s3 XjaYa9iJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtAAKCRB33NvayMhJ0fEwD/ 0c8c0kdMcu9cAO6MW+kau0NON/fYuaafAI++DNEg4rOBcbZZ9RNE9EqK8ZG+ERzfrEi1n/fLjJS0x5 E6k5Fj2Q+rGH7PAw1HeAmuECHlLgX2IMHWVF4EDSLWIlzZPUS8XFNz5vIMGCCMLv7Y311cVfmzrTtr IEwejNA/OmS0grIUXEClx8Sp1TinImZI9jHZh3AijGq8XiEW2E0rFGHrATPJHuA9Nx1BwEtrKMecSk wFtJCh+PCDWqm1SNjVQcYLbX3RPFRz0aXKKjET4NB7kZvPtD7T5mNh6cjK1k/keUTjEVplgtjJwA/d HZOrPOQNr1jKROsXy72AQ3XUs4WnPy8g31SX1EQNlXBl9j40MaU14ZEHPTtS5C/iIJrqxM4KNKGFWY 5pBAzHw/vaYt7C5NcrI4LGTpWgGwFPrvhahxuXCgAPHeEaHOAxcdYt3wjfm3obKlDO4bVWFYmnwGYb TFSxRTatfNcT/7G8e/fPR2InfUfImg9Q08gRNTvR0ls0t3P49CYiS1VwFL4cV9dT4CnQvNEWkmLNjf l/K7qlaz1AtLH22wg9bT79EL/ud1qabQeYwF5uFQHItpwMH3bgcoREdJeHPSLbdL4ZTJOzKFoSGJz0 ir6/tIunoN+bjEYP4Voc/7R8Pq+IIgVJ/8ED+SCvmiwkzoJFptWW6NxwIHRg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 clock bindings. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- .../devicetree/bindings/clock/oxnas,stdclk.txt | 28 ---------------------- 1 file changed, 28 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt b/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt deleted file mode 100644 index b652f3fb7796..000000000000 --- a/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt +++ /dev/null @@ -1,28 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family Standard Clocks -================================================ - -Please also refer to clock-bindings.txt in this directory for common clock -bindings usage. - -Required properties: -- compatible: For OX810SE, should be "oxsemi,ox810se-stdclk" - For OX820, should be "oxsemi,ox820-stdclk" -- #clock-cells: 1, see below - -Parent node should have the following properties : -- compatible: For OX810SE, should be - "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - For OX820, should be - "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - stdclk: stdclk { - compatible = "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; -}; From patchwork Fri Jun 30 16:58:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298506 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54FA3171B2 for ; Fri, 30 Jun 2023 16:58:45 +0000 (UTC) Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D776C3C14 for ; Fri, 30 Jun 2023 09:58:42 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3fbc244d307so16349175e9.1 for ; Fri, 30 Jun 2023 09:58:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144321; x=1690736321; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dmOMajD2YZSE+eel7VcvLzIVOnwOse/rnS6+x3C70yU=; b=FyShIEE8ur0fhetXt5zPzBSidrR54AJP5/e2Lw//yreQyw4erZQfmV8a+V/FjlusBq w8I0pbS/rPj775Mz6f2JIvefOIDOXJ5nZDkbsxuiYNYm82CliA0Fe4T5CMTPe+4pj6m9 H0RAW3JW8o5zTswmguMhgLlexP1RDfrlWXQvTK9/l5rWtLXfmNBGk/eb2PqgKRI0y1Bt KCdEqNdhgr5mUpeFZvuyZyhqWLRO8uV6NbbCtwYx3KtXO1iaFUnjCWu61m0zQLORIRua P4sHQFpSstj8NE5tkZ8I6XQnGgrW5O+J2M1Pnmihjo/DOXizWAgltrSKlRNBjh2vtCdu RD/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688144321; x=1690736321; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dmOMajD2YZSE+eel7VcvLzIVOnwOse/rnS6+x3C70yU=; b=ZyC+uzqQs7ZvbpsDpiIHRSD4xsfDTjnDa9YhQTbhK+HUuh5Mv2Cgg3SbWi8YsYr7Wy Wnz3JJtLBs7KSGgx76zgXXDzspiXheVKImPtVP9CiMa9IgOucoh4zjiqSpcj8w3Y6onM Vk0QhwfolKbKG12E148TpeUh2UehHwFvu6fkG8N9npa4XX3CDyNeduCLFc5ShX8ZPKrI 4tmiKLjn6GOu/B4Gjc7rNc8fHaBAIz5vPOS4vxZAu7EUhwZZ30lt9vhYnRtXvNzo+NCY 2LCPOeDiqSLR2U69B57EIwkYf6IirqjNvl6waonvJSAF90GND+KgkIiGR4neZZKTud0i eVCw== X-Gm-Message-State: ABy/qLaCbbpdQfayqBTEPZLg3KeOHLa+/g0RJtODoQi+RCtqLkJAj2uG q5rO1qZ2RSZSmQQ8z4d2PgdDLQ== X-Google-Smtp-Source: APBJJlH+WLO58Dsl5GTbdy9kidf6z2vq4lgBCLoHMljM4mx0veKMawVUIe+m9zc/05aH2be2DXGCOw== X-Received: by 2002:adf:dc84:0:b0:313:e591:94ec with SMTP id r4-20020adfdc84000000b00313e59194ecmr2412436wrj.67.1688144320967; Fri, 30 Jun 2023 09:58:40 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:58:40 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:28 +0200 Subject: [PATCH v2 03/15] clksource: timer-oxnas-rps: remove obsolete timer driver Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-3-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9387; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=OS+eBvSlx7DwBmhrfLY6QF+vMfbdyLJj8rLmG2ne3WQ=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm1abamxIw9Q1cu56fLZ7ZrcsS8fTUVPjdmIPHm 8tI36nqJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtQAKCRB33NvayMhJ0Ug+D/ 9iCGhYuRWDonKOcmDlJ5tRofvt7eO4c5xe+WnpQD0GlxL98f4NbqpB+vI+jQ0hBN6gP5apCF2fNze+ DbTRJZ1XVv44EbFpJ60Hcf95zAF3x4aYpNv0hBC4M/bNZ3FILAkVhPxVxWIIZuaTBNxRmycnLTB10r S81L9sUzDXhmHUSjM9XiDMsNf76LOSt6o2/VMz6becHzPBhy27MptVdUdET3CBa2ZSZHSKs32LBE0k 6L9UJ7QiX3RnZ25PrfUucLceECUeCutDAvoJXB1FMm1tsBBzLK0aQCXLk+b351leW4VJNBoIjgPmj6 2q0HkmSwAhnLgzEZGQZ/ISzLHj+hrc2fNxfx2Bvxk/mKHDsllz0u9s0FBVI77cGxhoza3yxLv48XZp vAw3m46ZiOzFBiaHsnNSCwvP3Y8q6rcTHgHJgUQDV7LkCt6UnNvT9BCXeo/GMHbzthYPIQPlKvTavN pP6uCdH3OvGh6d7Z3+k51mL6s0aEEypFNT6RRHnRbWjDLpt9MthqUiJcq9LUIL+0CjKYq8mRR2tTlx DCgE0wddZ2pIKF1LpncBc+TiRHtVT/lCOWqwQFb9NeDF49v3HlG9A4jK1oRH7AKsswGD9TluRtbIDi euhdRsyZH+fi+P7TeyHZlj5EGlr3kc/MHtKW2fXGj269nr0qVt8PuO2FURyQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 timer. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- drivers/clocksource/Kconfig | 7 - drivers/clocksource/Makefile | 1 - drivers/clocksource/timer-oxnas-rps.c | 288 ---------------------------------- 3 files changed, 296 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c4d671a5a13d..0ba0dc4ecf06 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -461,13 +461,6 @@ config VF_PIT_TIMER help Support for Periodic Interrupt Timer on Freescale Vybrid Family SoCs. -config OXNAS_RPS_TIMER - bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST - select TIMER_OF - select CLKSRC_MMIO - help - This enables support for the Oxford Semiconductor OXNAS RPS timers. - config SYS_SUPPORTS_SH_CMT bool diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5d93c9e3fc55..368c3461dab8 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -54,7 +54,6 @@ obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o obj-$(CONFIG_MTK_CPUX_TIMER) += timer-mediatek-cpux.o obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o -obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o diff --git a/drivers/clocksource/timer-oxnas-rps.c b/drivers/clocksource/timer-oxnas-rps.c deleted file mode 100644 index d514b44e67dd..000000000000 --- a/drivers/clocksource/timer-oxnas-rps.c +++ /dev/null @@ -1,288 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * drivers/clocksource/timer-oxnas-rps.c - * - * Copyright (C) 2009 Oxford Semiconductor Ltd - * Copyright (C) 2013 Ma Haijun - * Copyright (C) 2016 Neil Armstrong - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* TIMER1 used as tick - * TIMER2 used as clocksource - */ - -/* Registers definitions */ - -#define TIMER_LOAD_REG 0x0 -#define TIMER_CURR_REG 0x4 -#define TIMER_CTRL_REG 0x8 -#define TIMER_CLRINT_REG 0xC - -#define TIMER_BITS 24 - -#define TIMER_MAX_VAL (BIT(TIMER_BITS) - 1) - -#define TIMER_PERIODIC BIT(6) -#define TIMER_ENABLE BIT(7) - -#define TIMER_DIV1 (0) -#define TIMER_DIV16 (1 << 2) -#define TIMER_DIV256 (2 << 2) - -#define TIMER1_REG_OFFSET 0 -#define TIMER2_REG_OFFSET 0x20 - -/* Clockevent & Clocksource data */ - -struct oxnas_rps_timer { - struct clock_event_device clkevent; - void __iomem *clksrc_base; - void __iomem *clkevt_base; - unsigned long timer_period; - unsigned int timer_prescaler; - struct clk *clk; - int irq; -}; - -static irqreturn_t oxnas_rps_timer_irq(int irq, void *dev_id) -{ - struct oxnas_rps_timer *rps = dev_id; - - writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG); - - rps->clkevent.event_handler(&rps->clkevent); - - return IRQ_HANDLED; -} - -static void oxnas_rps_timer_config(struct oxnas_rps_timer *rps, - unsigned long period, - unsigned int periodic) -{ - uint32_t cfg = rps->timer_prescaler; - - if (period) - cfg |= TIMER_ENABLE; - - if (periodic) - cfg |= TIMER_PERIODIC; - - writel_relaxed(period, rps->clkevt_base + TIMER_LOAD_REG); - writel_relaxed(cfg, rps->clkevt_base + TIMER_CTRL_REG); -} - -static int oxnas_rps_timer_shutdown(struct clock_event_device *evt) -{ - struct oxnas_rps_timer *rps = - container_of(evt, struct oxnas_rps_timer, clkevent); - - oxnas_rps_timer_config(rps, 0, 0); - - return 0; -} - -static int oxnas_rps_timer_set_periodic(struct clock_event_device *evt) -{ - struct oxnas_rps_timer *rps = - container_of(evt, struct oxnas_rps_timer, clkevent); - - oxnas_rps_timer_config(rps, rps->timer_period, 1); - - return 0; -} - -static int oxnas_rps_timer_set_oneshot(struct clock_event_device *evt) -{ - struct oxnas_rps_timer *rps = - container_of(evt, struct oxnas_rps_timer, clkevent); - - oxnas_rps_timer_config(rps, rps->timer_period, 0); - - return 0; -} - -static int oxnas_rps_timer_next_event(unsigned long delta, - struct clock_event_device *evt) -{ - struct oxnas_rps_timer *rps = - container_of(evt, struct oxnas_rps_timer, clkevent); - - oxnas_rps_timer_config(rps, delta, 0); - - return 0; -} - -static int __init oxnas_rps_clockevent_init(struct oxnas_rps_timer *rps) -{ - ulong clk_rate = clk_get_rate(rps->clk); - ulong timer_rate; - - /* Start with prescaler 1 */ - rps->timer_prescaler = TIMER_DIV1; - rps->timer_period = DIV_ROUND_UP(clk_rate, HZ); - timer_rate = clk_rate; - - if (rps->timer_period > TIMER_MAX_VAL) { - rps->timer_prescaler = TIMER_DIV16; - timer_rate = clk_rate / 16; - rps->timer_period = DIV_ROUND_UP(timer_rate, HZ); - } - if (rps->timer_period > TIMER_MAX_VAL) { - rps->timer_prescaler = TIMER_DIV256; - timer_rate = clk_rate / 256; - rps->timer_period = DIV_ROUND_UP(timer_rate, HZ); - } - - rps->clkevent.name = "oxnas-rps"; - rps->clkevent.features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_DYNIRQ; - rps->clkevent.tick_resume = oxnas_rps_timer_shutdown; - rps->clkevent.set_state_shutdown = oxnas_rps_timer_shutdown; - rps->clkevent.set_state_periodic = oxnas_rps_timer_set_periodic; - rps->clkevent.set_state_oneshot = oxnas_rps_timer_set_oneshot; - rps->clkevent.set_next_event = oxnas_rps_timer_next_event; - rps->clkevent.rating = 200; - rps->clkevent.cpumask = cpu_possible_mask; - rps->clkevent.irq = rps->irq; - clockevents_config_and_register(&rps->clkevent, - timer_rate, - 1, - TIMER_MAX_VAL); - - pr_info("Registered clock event rate %luHz prescaler %x period %lu\n", - clk_rate, - rps->timer_prescaler, - rps->timer_period); - - return 0; -} - -/* Clocksource */ - -static void __iomem *timer_sched_base; - -static u64 notrace oxnas_rps_read_sched_clock(void) -{ - return ~readl_relaxed(timer_sched_base); -} - -static int __init oxnas_rps_clocksource_init(struct oxnas_rps_timer *rps) -{ - ulong clk_rate = clk_get_rate(rps->clk); - int ret; - - /* use prescale 16 */ - clk_rate = clk_rate / 16; - - writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG); - writel_relaxed(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16, - rps->clksrc_base + TIMER_CTRL_REG); - - timer_sched_base = rps->clksrc_base + TIMER_CURR_REG; - sched_clock_register(oxnas_rps_read_sched_clock, - TIMER_BITS, clk_rate); - ret = clocksource_mmio_init(timer_sched_base, - "oxnas_rps_clocksource_timer", - clk_rate, 250, TIMER_BITS, - clocksource_mmio_readl_down); - if (WARN_ON(ret)) { - pr_err("can't register clocksource\n"); - return ret; - } - - pr_info("Registered clocksource rate %luHz\n", clk_rate); - - return 0; -} - -static int __init oxnas_rps_timer_init(struct device_node *np) -{ - struct oxnas_rps_timer *rps; - void __iomem *base; - int ret; - - rps = kzalloc(sizeof(*rps), GFP_KERNEL); - if (!rps) - return -ENOMEM; - - rps->clk = of_clk_get(np, 0); - if (IS_ERR(rps->clk)) { - ret = PTR_ERR(rps->clk); - goto err_alloc; - } - - ret = clk_prepare_enable(rps->clk); - if (ret) - goto err_clk; - - base = of_iomap(np, 0); - if (!base) { - ret = -ENXIO; - goto err_clk_prepare; - } - - rps->irq = irq_of_parse_and_map(np, 0); - if (!rps->irq) { - ret = -EINVAL; - goto err_iomap; - } - - rps->clkevt_base = base + TIMER1_REG_OFFSET; - rps->clksrc_base = base + TIMER2_REG_OFFSET; - - /* Disable timers */ - writel_relaxed(0, rps->clkevt_base + TIMER_CTRL_REG); - writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG); - writel_relaxed(0, rps->clkevt_base + TIMER_LOAD_REG); - writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG); - writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG); - writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG); - - ret = request_irq(rps->irq, oxnas_rps_timer_irq, - IRQF_TIMER | IRQF_IRQPOLL, - "rps-timer", rps); - if (ret) - goto err_iomap; - - ret = oxnas_rps_clocksource_init(rps); - if (ret) - goto err_irqreq; - - ret = oxnas_rps_clockevent_init(rps); - if (ret) - goto err_irqreq; - - return 0; - -err_irqreq: - free_irq(rps->irq, rps); -err_iomap: - iounmap(base); -err_clk_prepare: - clk_disable_unprepare(rps->clk); -err_clk: - clk_put(rps->clk); -err_alloc: - kfree(rps); - - return ret; -} - -TIMER_OF_DECLARE(ox810se_rps, - "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init); -TIMER_OF_DECLARE(ox820_rps, - "oxsemi,ox820-rps-timer", oxnas_rps_timer_init); From patchwork Fri Jun 30 16:58:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298507 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E37D168C5 for ; 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Fri, 30 Jun 2023 09:58:42 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:29 +0200 Subject: [PATCH v2 04/15] dt-bindings: timer: oxsemi,rps-timer: remove obsolete bindings Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-4-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Krzysztof Kozlowski , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1412; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=qERiig5wSYeUoOI63YnahZ6nGdl82BedWKVtaXlIxWs=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm16A/yr4DilaWEdtzFgOEAGl/phXffqIwaLSmt sPsOlVaJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtQAKCRB33NvayMhJ0VDKD/ 47nyBKDAl2AY31ET35jQBTsmpGScqftSs8OcPuDPcN3VCsaWRv6UtgqcnEPJQnrzelrje0S3YGxPwF QcW3X6EWl3afDg0NhSDkHRIoXrVRFWxVUBXS0N3S8LKjVAWZKVkF62qgsGKTGCqhnIXvrtFwkJ1lXm MraxYWnOzHeiIf8ys9fhtGURRlCdkPn5qq1x/ZNCCQ5AwjWVRPg/8aqcvWGK4YVS7fTZcmsG+swmUD /AxQrAUMrJITN3Fsd8amhU2ujq9+quGZY2ch+5l7277ZFDC8kxuuh9szLemh9V31xMCCVd3J3IGJwH 4cckGQPOijSnOTxHF7HwSAWxmnbMCQJqW/S3I79dtFD1/LL5lRZkHCDplu6cDNkNtX3WMwQN7FZdA1 lZOacGLxkVnteC9JDXnxkGKG/NUWe8OPTD7SFm6dlXikbL+qcw3E65Aq2GILG2yK2w7wYTCz88WKT6 Ca9MJTRkvLSpUGvWTVfkDnH3r2oZMZ/c7iyrrHrWcCt96/g4XvyDU81HEg2K69hTCjV6GFQbIcdEHA N35J/1Fc1TMzOTitNRKzN+cyw1K1gnbIDzLODWsLwLk89HSh+6vSzrYp0mDv05ZvqR0WTFMPfWT7FT zwf7ysaGzArnbrJ4b2hsre8VHA6zxuXtL8gxaGy79xMpYSwfDEy55y669tWw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 timer bindings. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- .../devicetree/bindings/timer/oxsemi,rps-timer.txt | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt b/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt deleted file mode 100644 index d191612539e8..000000000000 --- a/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt +++ /dev/null @@ -1,17 +0,0 @@ -Oxford Semiconductor OXNAS SoCs Family RPS Timer -================================================ - -Required properties: -- compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer" -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupts of the two timers -- clocks : The phandle of the timer clock source - -example: - -timer0: timer@200 { - compatible = "oxsemi,ox810se-rps-timer"; - reg = <0x200 0x40>; - clocks = <&rpsclk>; - interrupts = <4 5>; -}; From patchwork Fri Jun 30 16:58:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298508 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99E1E174CE for ; Fri, 30 Jun 2023 16:58:48 +0000 (UTC) Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F4943C01 for ; Fri, 30 Jun 2023 09:58:46 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3fa9850bfebso22110305e9.1 for ; Fri, 30 Jun 2023 09:58:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144324; x=1690736324; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=zLX6nBNdDJugrDB/bEpPIyh5Bk3WxOcHqPGVxflanv0=; b=ZJshyi0t1+m1fWRh4RSn3mPfNlTGCmx81L3tZMHnGArfYhg6HHrT7fkJsgxItykzsw tjQpqSqwOJ7fG4jhR3xEDtR4/04cGDKawNeKlBGM8PfKXCY8v46mMglqxTDP9a3pgS3/ xXE2UFjOCN44q1fmfEp/5pr8VwMLXKFABzvY4bwZH/HXY8xqlaSfidyKSinUJiaKaAcM 0+rz7NTjRUfFvLMI9Z1ecvRAMiClwEBO/jT1sjfWEQDbZl8nMGEWLjaCaRmiYJzK6zE5 yxI6eBZk13vTDUTke52+3CnwwvE0TB/kX5pt44x9k4bL0erd+p8et1wcGaDpKnP+GEJq Qzeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688144324; x=1690736324; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zLX6nBNdDJugrDB/bEpPIyh5Bk3WxOcHqPGVxflanv0=; b=fjZ03yPNIVFZSUJPWuk2G9easF7nYAgW3auNLa221CFEclWg7O8SGfCE8EpYzxh36d JWRGPxY+VOYhnR/7N+zkkNL08/uBXz69mBKAISMMGjG9RgGz+pdgvh4MkPxRrIENhkh1 /XLBF/xCXsl4ZIpSeK684rz9GFbJ1oRTk6qGO0Bule6ShZ6/HuguxC5wbDyroHo2RUFw BNRKeI68wewnrrB5GNt1KYAraiHXYKq9eWQBNZH+57U/9Y1xEolc1yuWRgWMEYBjzIYx eoMNwCyBNFzkb5ul6+fJlz8oWRk7pnDxikcrc/HK8E60gDMLxgqi0+Ciq4/JgByoYNMA GpVQ== X-Gm-Message-State: AC+VfDxyXcwAHQ+P6HEMBQJL8w6E7nZxynKcL/1h8jVFmWlXNtEquiLl bTUkdZgMeyPIF4NvGBrEQbRFDQ== X-Google-Smtp-Source: ACHHUZ7sLazNkS5hMB5t8MZsO4t0md2cj2Mnsc0FoY8HRuFayoCgx/4smWdsoKAUnjWfPgjREkHWvg== X-Received: by 2002:a05:600c:2219:b0:3fb:c217:7243 with SMTP id z25-20020a05600c221900b003fbc2177243mr2743100wml.18.1688144324582; Fri, 30 Jun 2023 09:58:44 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:58:43 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:30 +0200 Subject: [PATCH v2 05/15] nand: oxnas_nand: remove obsolete raw nand driver Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-5-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7464; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=7dsGUntkBvgK9uJ6n7pA2u8tn+a0H9twzokCuaVvts0=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm1Oj0vMGvH0O5R6AWEiekxCYAhBP79UYq8vavO 6hSf6XGJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtQAKCRB33NvayMhJ0YtrEA DELLHsyVja0JZ9+9NAqqxKxiIFJ+WvtNaveSgdefeOSaEFmDD5DqUs/U/ZvYSBhKv6nbnlPKBR412z jsRR6sX7nzNSYPdX+ckwEWSX1Q2pGOFUqrHEQuOiuvLGBlC/AlfJIyCmRIujDiU7GeI8o8mALeSpdJ dEGJlcO9eg2h1D7FC+CcTxOZPgBSaWal5tjwV24BjAiBnl0neqRE/TrVz7dpr62TQf662kibEmDhzI pQM7M6JLpCn7skYtYXyVkOm0r1HhTZHQrlYBro0LmVEjjyFjZzPQ+4CuQpa3liMeSq+ehFsEr+ldxE oWhGqQLNsa3QRWznq/Lq0UFwqscynT5CYWtQS72EyEZsG9Z/y1lhBK2hJs7cPP+ubGz3hHCkGJpdHO VD5Y7ivWGN1fQRqV/YGohAQKJjbvo4XYWNqlfBXmBErGB6nkLkPDLoPllO8fEF8azo/lDIoWCJk1lk vUGqCC6Z7gTT1l8XFTIg3mCV2WzAHQS2DyLa2Mg4SkOzvvHsR/Sf0Q14D1+m4A6RlUDQ9AVOsBWI1r rfGfajgw3ca5+I0PAO9REG9MjoosN1yQlLQPEo+73hQ1dXFxQi66lExAkqV0OO1JYQcZpbkIjmyEQ6 oX0CJ/WRIoGnA56cF1huCNfoc2uc2ilsIlFtxqBbzuhFUWMBI7ibq7A6YFkA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 nand. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Miquel Raynal --- drivers/mtd/nand/raw/Kconfig | 7 -- drivers/mtd/nand/raw/Makefile | 1 - drivers/mtd/nand/raw/oxnas_nand.c | 209 -------------------------------------- 3 files changed, 217 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b523354dfb00..5b871e2f5c5e 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -204,13 +204,6 @@ config MTD_NAND_BCM47XXNFLASH registered by bcma as platform devices. This enables driver for NAND flash memories. For now only BCM4706 is supported. -config MTD_NAND_OXNAS - tristate "Oxford Semiconductor NAND controller" - depends on ARCH_OXNAS || COMPILE_TEST - depends on HAS_IOMEM - help - This enables the NAND flash controller on Oxford Semiconductor SoCs. - config MTD_NAND_MPC5121_NFC tristate "MPC5121 NAND controller" depends on PPC_MPC512x diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index d93e861d8ba7..25120a4afada 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_MTD_NAND_MARVELL) += marvell_nand.o obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o -obj-$(CONFIG_MTD_NAND_OXNAS) += oxnas_nand.o obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o diff --git a/drivers/mtd/nand/raw/oxnas_nand.c b/drivers/mtd/nand/raw/oxnas_nand.c deleted file mode 100644 index e3c9807df1cd..000000000000 --- a/drivers/mtd/nand/raw/oxnas_nand.c +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Oxford Semiconductor OXNAS NAND driver - - * Copyright (C) 2016 Neil Armstrong - * Heavily based on plat_nand.c : - * Author: Vitaly Wool - * Copyright (C) 2013 Ma Haijun - * Copyright (C) 2012 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Nand commands */ -#define OXNAS_NAND_CMD_ALE BIT(18) -#define OXNAS_NAND_CMD_CLE BIT(19) - -#define OXNAS_NAND_MAX_CHIPS 1 - -struct oxnas_nand_ctrl { - struct nand_controller base; - void __iomem *io_base; - struct clk *clk; - struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS]; - unsigned int nchips; -}; - -static uint8_t oxnas_nand_read_byte(struct nand_chip *chip) -{ - struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); - - return readb(oxnas->io_base); -} - -static void oxnas_nand_read_buf(struct nand_chip *chip, u8 *buf, int len) -{ - struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); - - ioread8_rep(oxnas->io_base, buf, len); -} - -static void oxnas_nand_write_buf(struct nand_chip *chip, const u8 *buf, - int len) -{ - struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); - - iowrite8_rep(oxnas->io_base, buf, len); -} - -/* Single CS command control */ -static void oxnas_nand_cmd_ctrl(struct nand_chip *chip, int cmd, - unsigned int ctrl) -{ - struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); - - if (ctrl & NAND_CLE) - writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE); - else if (ctrl & NAND_ALE) - writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE); -} - -/* - * Probe for the NAND device. - */ -static int oxnas_nand_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *nand_np; - struct oxnas_nand_ctrl *oxnas; - struct nand_chip *chip; - struct mtd_info *mtd; - int count = 0; - int err = 0; - int i; - - /* Allocate memory for the device structure (and zero it) */ - oxnas = devm_kzalloc(&pdev->dev, sizeof(*oxnas), - GFP_KERNEL); - if (!oxnas) - return -ENOMEM; - - nand_controller_init(&oxnas->base); - - oxnas->io_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(oxnas->io_base)) - return PTR_ERR(oxnas->io_base); - - oxnas->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(oxnas->clk)) - oxnas->clk = NULL; - - /* Only a single chip node is supported */ - count = of_get_child_count(np); - if (count > 1) - return -EINVAL; - - err = clk_prepare_enable(oxnas->clk); - if (err) - return err; - - device_reset_optional(&pdev->dev); - - for_each_child_of_node(np, nand_np) { - chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), - GFP_KERNEL); - if (!chip) { - err = -ENOMEM; - goto err_release_child; - } - - chip->controller = &oxnas->base; - - nand_set_flash_node(chip, nand_np); - nand_set_controller_data(chip, oxnas); - - mtd = nand_to_mtd(chip); - mtd->dev.parent = &pdev->dev; - mtd->priv = chip; - - chip->legacy.cmd_ctrl = oxnas_nand_cmd_ctrl; - chip->legacy.read_buf = oxnas_nand_read_buf; - chip->legacy.read_byte = oxnas_nand_read_byte; - chip->legacy.write_buf = oxnas_nand_write_buf; - chip->legacy.chip_delay = 30; - - /* Scan to find existence of the device */ - err = nand_scan(chip, 1); - if (err) - goto err_release_child; - - err = mtd_device_register(mtd, NULL, 0); - if (err) - goto err_cleanup_nand; - - oxnas->chips[oxnas->nchips++] = chip; - } - - /* Exit if no chips found */ - if (!oxnas->nchips) { - err = -ENODEV; - goto err_clk_unprepare; - } - - platform_set_drvdata(pdev, oxnas); - - return 0; - -err_cleanup_nand: - nand_cleanup(chip); -err_release_child: - of_node_put(nand_np); - - for (i = 0; i < oxnas->nchips; i++) { - chip = oxnas->chips[i]; - WARN_ON(mtd_device_unregister(nand_to_mtd(chip))); - nand_cleanup(chip); - } - -err_clk_unprepare: - clk_disable_unprepare(oxnas->clk); - return err; -} - -static void oxnas_nand_remove(struct platform_device *pdev) -{ - struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev); - struct nand_chip *chip; - int i; - - for (i = 0; i < oxnas->nchips; i++) { - chip = oxnas->chips[i]; - WARN_ON(mtd_device_unregister(nand_to_mtd(chip))); - nand_cleanup(chip); - } - - clk_disable_unprepare(oxnas->clk); -} - -static const struct of_device_id oxnas_nand_match[] = { - { .compatible = "oxsemi,ox820-nand" }, - {}, -}; -MODULE_DEVICE_TABLE(of, oxnas_nand_match); - -static struct platform_driver oxnas_nand_driver = { - .probe = oxnas_nand_probe, - .remove_new = oxnas_nand_remove, - .driver = { - .name = "oxnas_nand", - .of_match_table = oxnas_nand_match, - }, -}; - -module_platform_driver(oxnas_nand_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Neil Armstrong "); -MODULE_DESCRIPTION("Oxnas NAND driver"); -MODULE_ALIAS("platform:oxnas_nand"); From patchwork Fri Jun 30 16:58:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298509 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 745E3174CE for ; Fri, 30 Jun 2023 16:58:50 +0000 (UTC) Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 031E83C35 for ; Fri, 30 Jun 2023 09:58:48 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3fa9850bfebso22110765e9.1 for ; Fri, 30 Jun 2023 09:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144326; 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Fri, 30 Jun 2023 09:58:46 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:58:45 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:31 +0200 Subject: [PATCH v2 06/15] dt-bindings: mtd: oxnas-nand: remove obsolete bindings Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-6-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Krzysztof Kozlowski , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1834; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=38rvOQ5JzytmoL2e8XQMRnUMzYw1/Raq4YBpYNRm4dw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm2BW8UwSX3d9Pq718ni0310vOQ0HNcYv2IvLHm CF9ZdzKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtgAKCRB33NvayMhJ0Z6yEA DQB8ET5EMV67bFiwvw6CHMW/yDZltqA2FQRkT6U0VMXkLspqXbvM5YCSVAJhE0aCOEuSp86cn+sn6B fWYyhHNqZR/5Y90GsYVlPN/uNgiwV7djdZJcv8Hr7dPiSDl9hpicmk/oMOjbbFk2/KsZEk4/D8hL52 m4IUWBoCJlfxhDkSxtZFzKva3EJAGRdSXqKgBs6YFkjMklmRCCde69vPew6/N3svQGqbofvbgY1pcx qEn3jwLXNAv/R3f8+pMwEnhekYBxCSGhJZ0QKi2x1b4NC2YUnXjuF96hUl5KnjeNbekLihkL+Zixgl qNIiEuLWuFXKNCqbzpVgy3DM+VAkjyQ42Hc3PG31OYbYWTnLSrdi9m4LOcuBUEcETWUuBEIdKz8qgn uIIfwD/QwhkEqppN4NSnquwiHhfE/O0qsSOVji2MLteguNXuK2nFacu8zRElULaoSvez4BkfP3E0Hx 6Qk6g08mNZi9io9R1ZtfGcNJ59QnSZPgbu/iCZpDuGGufzmA0BMF7Hv9Y/aDSO51z947Gg9kG8gxD6 5/7/Li9DDTGcigSq41lgglOTJqSnGHn/8GoZIqTpQyxBSiJa/VRJv0Fp6XxxEee8EmIUwV12YGJgmk xB17WN5EDw0VCkcayM+CD9hpDPnRn8ZJCsjJ3wabBHR4HQ8BcT8pvuxHAm5A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the for OX810 and OX820 nand bindings. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Miquel Raynal --- .../devicetree/bindings/mtd/oxnas-nand.txt | 41 ---------------------- 1 file changed, 41 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt deleted file mode 100644 index 2ba07fc8b79c..000000000000 --- a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Oxford Semiconductor OXNAS NAND Controller - -Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings. - -Required properties: - - compatible: "oxsemi,ox820-nand" - - reg: Base address and length for NAND mapped memory. - -Optional Properties: - - clocks: phandle to the NAND gate clock if needed. - - resets: phandle to the NAND reset control if needed. - -Example: - -nandc: nand-controller@41000000 { - compatible = "oxsemi,ox820-nand"; - reg = <0x41000000 0x100000>; - clocks = <&stdclk CLK_820_NAND>; - resets = <&reset RESET_NAND>; - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - read-only; - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; From patchwork Fri Jun 30 16:58:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298510 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7C2B174CE for ; Fri, 30 Jun 2023 16:58:53 +0000 (UTC) Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A815C3C24 for ; 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Fri, 30 Jun 2023 09:58:47 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:32 +0200 Subject: [PATCH v2 07/15] net: stmmac: dwmac-oxnas: remove obsolete dwmac glue driver Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-7-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9143; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=ejAz1IAJoZ72AsGfMantZn1z4aUBu8ItOfmfHHeZV44=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm2VumAiS88SMnmjtsiebP+hoRV9So6UYEBjYMz JLbm4f6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtgAKCRB33NvayMhJ0fFoD/ 4923BNV/pVrdOwyik5/XtouR/Jlvt2gqmGEwEHrrLa9vkPleS9mo6rFBzrMKzub/3s8c0Nr8QGy9QX +ITgdAz3hadwdg6WD+pKQmzwLr5SKeq4Ompojznza9M1D2ah0zwnaqriC16RPkG1RVd+yHb+vvad44 hEomE8lC0Fp8nJasBuzOIhGWqpmkdS4b2C+xrwoXbS1GGO2wMEX/1g1EoRXC+ntNgxjcL6pRnrYaZF s8s/YQvObMyhIAxq3i7JOy9pGZqwN1tvk8Vbf0R5EqttAQXu2KCd5SELFBQ8wGQl/Byf3ffNsUi6sO 5+QyzsJ8RAQXIBJl+0rkLowTnsVe8drEo+VvVZYq4XasdenxbljLuxYlBD0sDgTteI8waV+7lWfORa wCLKAhLDXnOIGcCQSyhfia/noLqc3yJfrFgtgAG1DAdx89/WN2JJKXpxe0+hW3WDx8PzdfRmwW0HMe 2ZnzPiJnTfeZUGsuw9gaKmmaPst2kgi1p9ap02/RB4dnRnRwSFVc8T/zWwPwFF5rT1ftWWLcRCo+TP ZpDESoAgNFIdfafkjaFeyNwqnzIypqe54Fm12UQO0BeDNGH+nMauN2ZDkw1V47DNwcS4hqcB3rykP2 B8r4+4oRQfgq78z6eBgoDKvoxAxBrKjMsBceQDGiSyuaKHNNYRYR4VgR9deA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 ethernet. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 - drivers/net/ethernet/stmicro/stmmac/Makefile | 1 - drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c | 245 ---------------------- 3 files changed, 257 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 5583f0b055ec..06c6871f8788 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -121,17 +121,6 @@ config DWMAC_MESON the stmmac device driver. This driver is used for Meson6, Meson8, Meson8b and GXBB SoCs. -config DWMAC_OXNAS - tristate "Oxford Semiconductor OXNAS dwmac support" - default ARCH_OXNAS - depends on OF && COMMON_CLK && (ARCH_OXNAS || COMPILE_TEST) - select MFD_SYSCON - help - Support for Ethernet controller on Oxford Semiconductor OXNAS SoCs. - - This selects the Oxford Semiconductor OXNASSoC glue layer support for - the stmmac device driver. This driver is used for OX820. - config DWMAC_QCOM_ETHQOS tristate "Qualcomm ETHQOS support" default ARCH_QCOM diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index 7dd3d388068b..5b57aee19267 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-mediatek.o obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o -obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c deleted file mode 100644 index 42954020de2c..000000000000 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Oxford Semiconductor OXNAS DWMAC glue layer - * - * Copyright (C) 2016 Neil Armstrong - * Copyright (C) 2014 Daniel Golle - * Copyright (C) 2013 Ma Haijun - * Copyright (C) 2012 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "stmmac_platform.h" - -/* System Control regmap offsets */ -#define OXNAS_DWMAC_CTRL_REGOFFSET 0x78 -#define OXNAS_DWMAC_DELAY_REGOFFSET 0x100 - -/* Control Register */ -#define DWMAC_CKEN_RX_IN 14 -#define DWMAC_CKEN_RXN_OUT 13 -#define DWMAC_CKEN_RX_OUT 12 -#define DWMAC_CKEN_TX_IN 10 -#define DWMAC_CKEN_TXN_OUT 9 -#define DWMAC_CKEN_TX_OUT 8 -#define DWMAC_RX_SOURCE 7 -#define DWMAC_TX_SOURCE 6 -#define DWMAC_LOW_TX_SOURCE 4 -#define DWMAC_AUTO_TX_SOURCE 3 -#define DWMAC_RGMII 2 -#define DWMAC_SIMPLE_MUX 1 -#define DWMAC_CKEN_GTX 0 - -/* Delay register */ -#define DWMAC_TX_VARDELAY_SHIFT 0 -#define DWMAC_TXN_VARDELAY_SHIFT 8 -#define DWMAC_RX_VARDELAY_SHIFT 16 -#define DWMAC_RXN_VARDELAY_SHIFT 24 -#define DWMAC_TX_VARDELAY(d) ((d) << DWMAC_TX_VARDELAY_SHIFT) -#define DWMAC_TXN_VARDELAY(d) ((d) << DWMAC_TXN_VARDELAY_SHIFT) -#define DWMAC_RX_VARDELAY(d) ((d) << DWMAC_RX_VARDELAY_SHIFT) -#define DWMAC_RXN_VARDELAY(d) ((d) << DWMAC_RXN_VARDELAY_SHIFT) - -struct oxnas_dwmac; - -struct oxnas_dwmac_data { - int (*setup)(struct oxnas_dwmac *dwmac); -}; - -struct oxnas_dwmac { - struct device *dev; - struct clk *clk; - struct regmap *regmap; - const struct oxnas_dwmac_data *data; -}; - -static int oxnas_dwmac_setup_ox810se(struct oxnas_dwmac *dwmac) -{ - unsigned int value; - int ret; - - ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); - if (ret < 0) - return ret; - - /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */ - value |= BIT(DWMAC_CKEN_GTX) | - /* Use simple mux for 25/125 Mhz clock switching */ - BIT(DWMAC_SIMPLE_MUX); - - regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); - - return 0; -} - -static int oxnas_dwmac_setup_ox820(struct oxnas_dwmac *dwmac) -{ - unsigned int value; - int ret; - - ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); - if (ret < 0) - return ret; - - /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */ - value |= BIT(DWMAC_CKEN_GTX) | - /* Use simple mux for 25/125 Mhz clock switching */ - BIT(DWMAC_SIMPLE_MUX) | - /* set auto switch tx clock source */ - BIT(DWMAC_AUTO_TX_SOURCE) | - /* enable tx & rx vardelay */ - BIT(DWMAC_CKEN_TX_OUT) | - BIT(DWMAC_CKEN_TXN_OUT) | - BIT(DWMAC_CKEN_TX_IN) | - BIT(DWMAC_CKEN_RX_OUT) | - BIT(DWMAC_CKEN_RXN_OUT) | - BIT(DWMAC_CKEN_RX_IN); - regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); - - /* set tx & rx vardelay */ - value = DWMAC_TX_VARDELAY(4) | - DWMAC_TXN_VARDELAY(2) | - DWMAC_RX_VARDELAY(10) | - DWMAC_RXN_VARDELAY(8); - regmap_write(dwmac->regmap, OXNAS_DWMAC_DELAY_REGOFFSET, value); - - return 0; -} - -static int oxnas_dwmac_init(struct platform_device *pdev, void *priv) -{ - struct oxnas_dwmac *dwmac = priv; - int ret; - - /* Reset HW here before changing the glue configuration */ - ret = device_reset(dwmac->dev); - if (ret) - return ret; - - ret = clk_prepare_enable(dwmac->clk); - if (ret) - return ret; - - ret = dwmac->data->setup(dwmac); - if (ret) - clk_disable_unprepare(dwmac->clk); - - return ret; -} - -static void oxnas_dwmac_exit(struct platform_device *pdev, void *priv) -{ - struct oxnas_dwmac *dwmac = priv; - - clk_disable_unprepare(dwmac->clk); -} - -static int oxnas_dwmac_probe(struct platform_device *pdev) -{ - struct plat_stmmacenet_data *plat_dat; - struct stmmac_resources stmmac_res; - struct oxnas_dwmac *dwmac; - int ret; - - ret = stmmac_get_platform_resources(pdev, &stmmac_res); - if (ret) - return ret; - - plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - - dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); - if (!dwmac) { - ret = -ENOMEM; - goto err_remove_config_dt; - } - - dwmac->data = (const struct oxnas_dwmac_data *)of_device_get_match_data(&pdev->dev); - if (!dwmac->data) { - ret = -EINVAL; - goto err_remove_config_dt; - } - - dwmac->dev = &pdev->dev; - plat_dat->bsp_priv = dwmac; - plat_dat->init = oxnas_dwmac_init; - plat_dat->exit = oxnas_dwmac_exit; - - dwmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "oxsemi,sys-ctrl"); - if (IS_ERR(dwmac->regmap)) { - dev_err(&pdev->dev, "failed to have sysctrl regmap\n"); - ret = PTR_ERR(dwmac->regmap); - goto err_remove_config_dt; - } - - dwmac->clk = devm_clk_get(&pdev->dev, "gmac"); - if (IS_ERR(dwmac->clk)) { - ret = PTR_ERR(dwmac->clk); - goto err_remove_config_dt; - } - - ret = oxnas_dwmac_init(pdev, plat_dat->bsp_priv); - if (ret) - goto err_remove_config_dt; - - ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); - if (ret) - goto err_dwmac_exit; - - - return 0; - -err_dwmac_exit: - oxnas_dwmac_exit(pdev, plat_dat->bsp_priv); -err_remove_config_dt: - stmmac_remove_config_dt(pdev, plat_dat); - - return ret; -} - -static const struct oxnas_dwmac_data ox810se_dwmac_data = { - .setup = oxnas_dwmac_setup_ox810se, -}; - -static const struct oxnas_dwmac_data ox820_dwmac_data = { - .setup = oxnas_dwmac_setup_ox820, -}; - -static const struct of_device_id oxnas_dwmac_match[] = { - { - .compatible = "oxsemi,ox810se-dwmac", - .data = &ox810se_dwmac_data, - }, - { - .compatible = "oxsemi,ox820-dwmac", - .data = &ox820_dwmac_data, - }, - { } -}; -MODULE_DEVICE_TABLE(of, oxnas_dwmac_match); - -static struct platform_driver oxnas_dwmac_driver = { - .probe = oxnas_dwmac_probe, - .remove_new = stmmac_pltfr_remove, - .driver = { - .name = "oxnas-dwmac", - .pm = &stmmac_pltfr_pm_ops, - .of_match_table = oxnas_dwmac_match, - }, -}; -module_platform_driver(oxnas_dwmac_driver); - -MODULE_AUTHOR("Neil Armstrong "); -MODULE_DESCRIPTION("Oxford Semiconductor OXNAS DWMAC glue layer"); -MODULE_LICENSE("GPL v2"); From patchwork Fri Jun 30 16:58:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298511 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAB1D174CE for ; Fri, 30 Jun 2023 16:58:54 +0000 (UTC) Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6872F4204 for ; Fri, 30 Jun 2023 09:58:51 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3113dabc549so2508551f8f.1 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2150; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=TLDrcb0mzwLI06ByewFdMOz8nc1IDfSB9k98JAwmgYI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm3h8ExnMBya+L7ppxVXE2kolWWvQzXeql91gvK 3+FRKWOJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtwAKCRB33NvayMhJ0TcTD/ 49DmQNUye4umPLTMTCCVgbCtNVJnEqPD1yc38kQmygaiwUUL4p3pz0vbeCvj4ah6wu6WO+XRXqO0gQ 3k854on6XQUHo9WrsI6NjE6HooFs84KtwrRG00j4Q1eOa0jGdK0HBjP0Py8hGuEHOQlmE3k+HF40+T b+T0qeWwVShG9ulHY3KNZdNF4NaQxia8Hc6gD2wxvqa9v/0OQ5zeGclkMBLecEFnQ9fJWqbyK0Smil f+UYvCvqSZnJ+kJjTx/C4uMU3yKJAAN2ZBioc/NYQTfd9Ao7We+j131ZZdxzbbiPZk10JdshwTWIVw hHEBPbng8MZ+L+DixJfbqX1+7EOZJbtrFZQZ/nhXrV11IGac36jlbj6qx66dR4pKpR7gk4vTTlnrU+ 5FYspLKqZwbP1JP4QcJzm4UI1moYpO/7HQTM7duxBYz05ojPgMch2OsmFWan4Vijea0dkux5MWOA3W k+D/2E1Rq7qy6FRLDZQpRs3mJyOv0xO3NUbrSxKol//M/yMsNBGEXZrZpWAUUfIrOee3adJp+CdL82 P5q00RhvgockGnpC1hG5wKP0yRKgORY5nFDbWDIwuGhzUDBMhVT7MUujUqLyipH2e/Z8ZUMImThizb JOwoQ062na9BGzhuWa3S2u3m9KYCZD8xurvT7t19cdpUO0lWiIRLKh2RgE/w== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 dwmac glue. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Conor Dooley --- .../devicetree/bindings/net/oxnas-dwmac.txt | 41 ---------------------- 1 file changed, 41 deletions(-) diff --git a/Documentation/devicetree/bindings/net/oxnas-dwmac.txt b/Documentation/devicetree/bindings/net/oxnas-dwmac.txt deleted file mode 100644 index 27db496f1ce8..000000000000 --- a/Documentation/devicetree/bindings/net/oxnas-dwmac.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Oxford Semiconductor OXNAS DWMAC Ethernet controller - -The device inherits all the properties of the dwmac/stmmac devices -described in the file stmmac.txt in the current directory with the -following changes. - -Required properties on all platforms: - -- compatible: For the OX820 SoC, it should be : - - "oxsemi,ox820-dwmac" to select glue - - "snps,dwmac-3.512" to select IP version. - For the OX810SE SoC, it should be : - - "oxsemi,ox810se-dwmac" to select glue - - "snps,dwmac-3.512" to select IP version. - -- clocks: Should contain phandles to the following clocks -- clock-names: Should contain the following: - - "stmmaceth" for the host clock - see stmmac.txt - - "gmac" for the peripheral gate clock - -- oxsemi,sys-ctrl: a phandle to the system controller syscon node - -Example : - -etha: ethernet@40400000 { - compatible = "oxsemi,ox820-dwmac", "snps,dwmac-3.512"; - reg = <0x40400000 0x2000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - mac-address = [000000000000]; /* Filled in by U-Boot */ - phy-mode = "rgmii"; - - clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; - clock-names = "gmac", "stmmaceth"; - resets = <&reset RESET_MAC>; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - -}; From patchwork Fri Jun 30 16:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298512 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 919FF17725 for ; Fri, 30 Jun 2023 16:59:02 +0000 (UTC) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 935F6422E for ; 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Fri, 30 Jun 2023 09:58:50 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:34 +0200 Subject: [PATCH v2 09/15] pinctrl: pinctrl-oxnas: remove obsolete pinctrl driver Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-9-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=41138; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=0F3ViCZzMXLvzHUyUuJcin8s65eC9Y61ySet6oy0B5s=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm30b2exmFhKIOhECYo/VV5bgmGaGZpMWK2981X n/50bNSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JtwAKCRB33NvayMhJ0RhmD/ 9jq+nfR8ZZbsssVkdwvPV30mOsQNTSLyTmIGA5ksob657XPpc6WdiU+X6Zmxh1TS4wp+hZUZ2UmCEz JRnOb6A7XYgGm2xLvbLvnNfWZjQp9BUhE+olXQiPMa0TUNZ38tJPObNJtP0S16wjGWR3FYzHAemG3k 9ToRzAqArVRgB0DBPAzC1eu7fjwUwV5Qm2WWp0td/j0Z4NyGJoJ1UNhdN8wGnsPX1+8+easUFw1Y2t ZxEAliyybvYotHegZX9+fAQrTqGc4sc146SeR15HE9+dyS9APgYUQ3KzGzd2ZA97QYhMb1r1yIJQHS 1O8qNszovNWuOtnel+KL/tD4QA+rtioJNh4+JtAfDutRW73aeaEueYXqyiMY0BnIH28IDEERhjS4jk P/UpQXHrJ1G2Ry5YvEynovkD01U0ybiYL3fj+H7u7nwm6yu9pgY3I1fwlxzShVw6R9TbOAFyVeDKTR WlaWMSsvzaVTWPJkkiaeO5Pnp1iHi12936d9b5pZAMIdY7KZE7YpPR2pCK3l3bXUPWozHkrj3nGiDy KDRmc8ds3BrfwLwM7gxu08DIg9HkAcyshQ9gdsMklN1SRdtjxPd5iPJdD7v+fu2N4JCm6MgI5ayeaf oJEOnG0DGquLJLJkr4qLpZxeD2dW1afJPpQzsRx14gUcEyzCSv945DhHqv1g== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 pinctrl & gpio. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- drivers/pinctrl/Kconfig | 11 - drivers/pinctrl/Makefile | 1 - drivers/pinctrl/pinctrl-oxnas.c | 1292 --------------------------------------- 3 files changed, 1304 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 57d57af1f624..7dfb7190580e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -355,17 +355,6 @@ config PINCTRL_OCELOT If conpiled as a module, the module name will be pinctrl-ocelot. -config PINCTRL_OXNAS - bool - depends on OF - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB - select OF_GPIO - select GPIOLIB_IRQCHIP - select MFD_SYSCON - config PINCTRL_PALMAS tristate "Pinctrl driver for the PALMAS Series MFD devices" depends on OF && MFD_PALMAS diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 482b391b5deb..dd6cda270294 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o -obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c deleted file mode 100644 index fb10a8473ebe..000000000000 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ /dev/null @@ -1,1292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Oxford Semiconductor OXNAS SoC Family pinctrl driver - * - * Copyright (C) 2016 Neil Armstrong - * - * Based on pinctrl-pic32.c - * Joshua Henderson, - * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-utils.h" - -#define PINS_PER_BANK 32 - -#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) - -/* OX810 Regmap Offsets */ -#define PINMUX_810_PRIMARY_SEL0 0x0c -#define PINMUX_810_SECONDARY_SEL0 0x14 -#define PINMUX_810_TERTIARY_SEL0 0x8c -#define PINMUX_810_PRIMARY_SEL1 0x10 -#define PINMUX_810_SECONDARY_SEL1 0x18 -#define PINMUX_810_TERTIARY_SEL1 0x90 -#define PINMUX_810_PULLUP_CTRL0 0xac -#define PINMUX_810_PULLUP_CTRL1 0xb0 - -/* OX820 Regmap Offsets */ -#define PINMUX_820_BANK_OFFSET 0x100000 -#define PINMUX_820_SECONDARY_SEL 0x14 -#define PINMUX_820_TERTIARY_SEL 0x8c -#define PINMUX_820_QUATERNARY_SEL 0x94 -#define PINMUX_820_DEBUG_SEL 0x9c -#define PINMUX_820_ALTERNATIVE_SEL 0xa4 -#define PINMUX_820_PULLUP_CTRL 0xac - -/* GPIO Registers */ -#define INPUT_VALUE 0x00 -#define OUTPUT_EN 0x04 -#define IRQ_PENDING 0x0c -#define OUTPUT_SET 0x14 -#define OUTPUT_CLEAR 0x18 -#define OUTPUT_EN_SET 0x1c -#define OUTPUT_EN_CLEAR 0x20 -#define RE_IRQ_ENABLE 0x28 -#define FE_IRQ_ENABLE 0x2c - -struct oxnas_function { - const char *name; - const char * const *groups; - unsigned int ngroups; -}; - -struct oxnas_pin_group { - const char *name; - unsigned int pin; - unsigned int bank; - struct oxnas_desc_function *functions; -}; - -struct oxnas_desc_function { - const char *name; - unsigned int fct; -}; - -struct oxnas_gpio_bank { - void __iomem *reg_base; - struct gpio_chip gpio_chip; - struct irq_chip irq_chip; - unsigned int id; -}; - -struct oxnas_pinctrl { - struct regmap *regmap; - struct device *dev; - struct pinctrl_dev *pctldev; - const struct oxnas_function *functions; - unsigned int nfunctions; - const struct oxnas_pin_group *groups; - unsigned int ngroups; - struct oxnas_gpio_bank *gpio_banks; - unsigned int nbanks; -}; - -struct oxnas_pinctrl_data { - struct pinctrl_desc *desc; - struct oxnas_pinctrl *pctl; -}; - -static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = { - PINCTRL_PIN(0, "gpio0"), - PINCTRL_PIN(1, "gpio1"), - PINCTRL_PIN(2, "gpio2"), - PINCTRL_PIN(3, "gpio3"), - PINCTRL_PIN(4, "gpio4"), - PINCTRL_PIN(5, "gpio5"), - PINCTRL_PIN(6, "gpio6"), - PINCTRL_PIN(7, "gpio7"), - PINCTRL_PIN(8, "gpio8"), - PINCTRL_PIN(9, "gpio9"), - PINCTRL_PIN(10, "gpio10"), - PINCTRL_PIN(11, "gpio11"), - PINCTRL_PIN(12, "gpio12"), - PINCTRL_PIN(13, "gpio13"), - PINCTRL_PIN(14, "gpio14"), - PINCTRL_PIN(15, "gpio15"), - PINCTRL_PIN(16, "gpio16"), - PINCTRL_PIN(17, "gpio17"), - PINCTRL_PIN(18, "gpio18"), - PINCTRL_PIN(19, "gpio19"), - PINCTRL_PIN(20, "gpio20"), - PINCTRL_PIN(21, "gpio21"), - PINCTRL_PIN(22, "gpio22"), - PINCTRL_PIN(23, "gpio23"), - PINCTRL_PIN(24, "gpio24"), - PINCTRL_PIN(25, "gpio25"), - PINCTRL_PIN(26, "gpio26"), - PINCTRL_PIN(27, "gpio27"), - PINCTRL_PIN(28, "gpio28"), - PINCTRL_PIN(29, "gpio29"), - PINCTRL_PIN(30, "gpio30"), - PINCTRL_PIN(31, "gpio31"), - PINCTRL_PIN(32, "gpio32"), - PINCTRL_PIN(33, "gpio33"), - PINCTRL_PIN(34, "gpio34"), -}; - -static const struct pinctrl_pin_desc oxnas_ox820_pins[] = { - PINCTRL_PIN(0, "gpio0"), - PINCTRL_PIN(1, "gpio1"), - PINCTRL_PIN(2, "gpio2"), - PINCTRL_PIN(3, "gpio3"), - PINCTRL_PIN(4, "gpio4"), - PINCTRL_PIN(5, "gpio5"), - PINCTRL_PIN(6, "gpio6"), - PINCTRL_PIN(7, "gpio7"), - PINCTRL_PIN(8, "gpio8"), - PINCTRL_PIN(9, "gpio9"), - PINCTRL_PIN(10, "gpio10"), - PINCTRL_PIN(11, "gpio11"), - PINCTRL_PIN(12, "gpio12"), - PINCTRL_PIN(13, "gpio13"), - PINCTRL_PIN(14, "gpio14"), - PINCTRL_PIN(15, "gpio15"), - PINCTRL_PIN(16, "gpio16"), - PINCTRL_PIN(17, "gpio17"), - PINCTRL_PIN(18, "gpio18"), - PINCTRL_PIN(19, "gpio19"), - PINCTRL_PIN(20, "gpio20"), - PINCTRL_PIN(21, "gpio21"), - PINCTRL_PIN(22, "gpio22"), - PINCTRL_PIN(23, "gpio23"), - PINCTRL_PIN(24, "gpio24"), - PINCTRL_PIN(25, "gpio25"), - PINCTRL_PIN(26, "gpio26"), - PINCTRL_PIN(27, "gpio27"), - PINCTRL_PIN(28, "gpio28"), - PINCTRL_PIN(29, "gpio29"), - PINCTRL_PIN(30, "gpio30"), - PINCTRL_PIN(31, "gpio31"), - PINCTRL_PIN(32, "gpio32"), - PINCTRL_PIN(33, "gpio33"), - PINCTRL_PIN(34, "gpio34"), - PINCTRL_PIN(35, "gpio35"), - PINCTRL_PIN(36, "gpio36"), - PINCTRL_PIN(37, "gpio37"), - PINCTRL_PIN(38, "gpio38"), - PINCTRL_PIN(39, "gpio39"), - PINCTRL_PIN(40, "gpio40"), - PINCTRL_PIN(41, "gpio41"), - PINCTRL_PIN(42, "gpio42"), - PINCTRL_PIN(43, "gpio43"), - PINCTRL_PIN(44, "gpio44"), - PINCTRL_PIN(45, "gpio45"), - PINCTRL_PIN(46, "gpio46"), - PINCTRL_PIN(47, "gpio47"), - PINCTRL_PIN(48, "gpio48"), - PINCTRL_PIN(49, "gpio49"), -}; - -static const char * const oxnas_ox810se_fct0_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio28", "gpio29", "gpio30", "gpio31", - "gpio32", "gpio33", "gpio34" -}; - -static const char * const oxnas_ox810se_fct3_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio20", - "gpio22", "gpio23", "gpio24", "gpio25", - "gpio26", "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32", "gpio33", - "gpio34" -}; - -static const char * const oxnas_ox820_fct0_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio28", "gpio29", "gpio30", "gpio31", - "gpio32", "gpio33", "gpio34", "gpio35", - "gpio36", "gpio37", "gpio38", "gpio39", - "gpio40", "gpio41", "gpio42", "gpio43", - "gpio44", "gpio45", "gpio46", "gpio47", - "gpio48", "gpio49" -}; - -static const char * const oxnas_ox820_fct1_group[] = { - "gpio3", "gpio4", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24" -}; - -static const char * const oxnas_ox820_fct4_group[] = { - "gpio5", "gpio6", "gpio7", "gpio8", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio40", "gpio41", "gpio42", "gpio43" -}; - -static const char * const oxnas_ox820_fct5_group[] = { - "gpio28", "gpio29", "gpio30", "gpio31" -}; - -#define FUNCTION(_name, _gr) \ - { \ - .name = #_name, \ - .groups = oxnas_##_gr##_group, \ - .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \ - } - -static const struct oxnas_function oxnas_ox810se_functions[] = { - FUNCTION(gpio, ox810se_fct0), - FUNCTION(fct3, ox810se_fct3), -}; - -static const struct oxnas_function oxnas_ox820_functions[] = { - FUNCTION(gpio, ox820_fct0), - FUNCTION(fct1, ox820_fct1), - FUNCTION(fct4, ox820_fct4), - FUNCTION(fct5, ox820_fct5), -}; - -#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \ - { \ - .name = #_name, \ - .pin = _pin, \ - .bank = _pin / PINS_PER_BANK, \ - .functions = (struct oxnas_desc_function[]){ \ - __VA_ARGS__, { } }, \ - } - -#define OXNAS_PINCTRL_FUNCTION(_name, _fct) \ - { \ - .name = #_name, \ - .fct = _fct, \ - } - -static const struct oxnas_pin_group oxnas_ox810se_groups[] = { - OXNAS_PINCTRL_GROUP(0, gpio0, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(1, gpio1, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(2, gpio2, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(3, gpio3, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(4, gpio4, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(5, gpio5, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(6, gpio6, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(7, gpio7, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(8, gpio8, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(9, gpio9, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(10, gpio10, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(11, gpio11, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(12, gpio12, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(13, gpio13, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(14, gpio14, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(15, gpio15, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(16, gpio16, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(17, gpio17, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(18, gpio18, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(19, gpio19, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(20, gpio20, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(21, gpio21, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(22, gpio22, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(23, gpio23, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(24, gpio24, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(25, gpio25, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(26, gpio26, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(27, gpio27, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(28, gpio28, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(29, gpio29, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(30, gpio30, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(31, gpio31, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(32, gpio32, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(33, gpio33, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(34, gpio34, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), -}; - -static const struct oxnas_pin_group oxnas_ox820_groups[] = { - OXNAS_PINCTRL_GROUP(0, gpio0, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(1, gpio1, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(2, gpio2, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(3, gpio3, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(4, gpio4, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(5, gpio5, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(6, gpio6, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(7, gpio7, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(8, gpio8, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(9, gpio9, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(10, gpio10, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(11, gpio11, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(12, gpio12, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(13, gpio13, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(14, gpio14, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(15, gpio15, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(16, gpio16, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(17, gpio17, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(18, gpio18, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(19, gpio19, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(20, gpio20, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(21, gpio21, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(22, gpio22, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(23, gpio23, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(24, gpio24, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1), - OXNAS_PINCTRL_FUNCTION(fct4, 5)), - OXNAS_PINCTRL_GROUP(25, gpio25, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(26, gpio26, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(27, gpio27, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(28, gpio28, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(29, gpio29, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(30, gpio30, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(31, gpio31, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(32, gpio32, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(33, gpio33, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(34, gpio34, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(35, gpio35, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(36, gpio36, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(37, gpio37, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(38, gpio38, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(39, gpio39, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(40, gpio40, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(41, gpio41, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(42, gpio42, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(43, gpio43, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(44, gpio44, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(45, gpio45, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(46, gpio46, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(47, gpio47, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(48, gpio48, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(49, gpio49, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), -}; - -static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl, - unsigned int pin) -{ - return &pctl->gpio_banks[pin / PINS_PER_BANK]; -} - -static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->ngroups; -} - -static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->groups[group].name; -} - -static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *pins = &pctl->groups[group].pin; - *num_pins = 1; - - return 0; -} - -static const struct pinctrl_ops oxnas_pinctrl_ops = { - .get_groups_count = oxnas_pinctrl_get_groups_count, - .get_group_name = oxnas_pinctrl_get_group_name, - .get_group_pins = oxnas_pinctrl_get_group_pins, - .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, - .dt_free_map = pinctrl_utils_free_map, -}; - -static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->nfunctions; -} - -static const char * -oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->functions[func].name; -} - -static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int func, - const char * const **groups, - unsigned int * const num_groups) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctl->functions[func].groups; - *num_groups = pctl->functions[func].ngroups; - - return 0; -} - -static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned int func, unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pin_group *pg = &pctl->groups[group]; - const struct oxnas_function *pf = &pctl->functions[func]; - const char *fname = pf->name; - struct oxnas_desc_function *functions = pg->functions; - u32 mask = BIT(pg->pin); - - while (functions->name) { - if (!strcmp(functions->name, fname)) { - dev_dbg(pctl->dev, - "setting function %s bank %d pin %d fct %d mask %x\n", - fname, pg->bank, pg->pin, - functions->fct, mask); - - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_PRIMARY_SEL1 : - PINMUX_810_PRIMARY_SEL0), - mask, - (functions->fct == 1 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_SECONDARY_SEL1 : - PINMUX_810_SECONDARY_SEL0), - mask, - (functions->fct == 2 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_TERTIARY_SEL1 : - PINMUX_810_TERTIARY_SEL0), - mask, - (functions->fct == 3 ? - mask : 0)); - - return 0; - } - - functions++; - } - - dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); - - return -EINVAL; -} - -static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned int func, unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pin_group *pg = &pctl->groups[group]; - const struct oxnas_function *pf = &pctl->functions[func]; - const char *fname = pf->name; - struct oxnas_desc_function *functions = pg->functions; - unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(pg->pin); - - while (functions->name) { - if (!strcmp(functions->name, fname)) { - dev_dbg(pctl->dev, - "setting function %s bank %d pin %d fct %d mask %x\n", - fname, pg->bank, pg->pin, - functions->fct, mask); - - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_SECONDARY_SEL, - mask, - (functions->fct == 1 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_TERTIARY_SEL, - mask, - (functions->fct == 2 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_QUATERNARY_SEL, - mask, - (functions->fct == 3 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_DEBUG_SEL, - mask, - (functions->fct == 4 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_ALTERNATIVE_SEL, - mask, - (functions->fct == 5 ? - mask : 0)); - - return 0; - } - - functions++; - } - - dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); - - return -EINVAL; -} - -static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); - u32 mask = BIT(offset - bank->gpio_chip.base); - - dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n", - offset, bank->gpio_chip.base, bank->id, mask); - - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_PRIMARY_SEL1 : - PINMUX_810_PRIMARY_SEL0), - mask, 0); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_SECONDARY_SEL1 : - PINMUX_810_SECONDARY_SEL0), - mask, 0); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_TERTIARY_SEL1 : - PINMUX_810_TERTIARY_SEL0), - mask, 0); - - return 0; -} - -static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(offset - bank->gpio_chip.base); - - dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n", - offset, bank->gpio_chip.base, bank->id, mask); - - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_SECONDARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_TERTIARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_QUATERNARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_DEBUG_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_ALTERNATIVE_SEL, - mask, 0); - - return 0; -} - -static int oxnas_gpio_get_direction(struct gpio_chip *chip, - unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int oxnas_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR); - - return 0; -} - -static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0; -} - -static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - if (value) - writel_relaxed(mask, bank->reg_base + OUTPUT_SET); - else - writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR); -} - -static int oxnas_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - oxnas_gpio_set(chip, offset, value); - writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET); - - return 0; -} - -static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset, bool input) -{ - struct gpio_chip *chip = range->gc; - - if (input) - oxnas_gpio_direction_input(chip, offset); - else - oxnas_gpio_direction_output(chip, offset, 0); - - return 0; -} - -static const struct pinmux_ops oxnas_ox810se_pinmux_ops = { - .get_functions_count = oxnas_pinmux_get_functions_count, - .get_function_name = oxnas_pinmux_get_function_name, - .get_function_groups = oxnas_pinmux_get_function_groups, - .set_mux = oxnas_ox810se_pinmux_enable, - .gpio_request_enable = oxnas_ox810se_gpio_request_enable, - .gpio_set_direction = oxnas_gpio_set_direction, -}; - -static const struct pinmux_ops oxnas_ox820_pinmux_ops = { - .get_functions_count = oxnas_pinmux_get_functions_count, - .get_function_name = oxnas_pinmux_get_function_name, - .get_function_groups = oxnas_pinmux_get_function_groups, - .set_mux = oxnas_ox820_pinmux_enable, - .gpio_request_enable = oxnas_ox820_gpio_request_enable, - .gpio_set_direction = oxnas_gpio_set_direction, -}; - -static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param = pinconf_to_config_param(*config); - u32 mask = BIT(pin - bank->gpio_chip.base); - int ret; - u32 arg; - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - ret = regmap_read(pctl->regmap, - (bank->id ? - PINMUX_810_PULLUP_CTRL1 : - PINMUX_810_PULLUP_CTRL0), - &arg); - if (ret) - return ret; - - arg = !!(arg & mask); - break; - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param = pinconf_to_config_param(*config); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(pin - bank->gpio_chip.base); - int ret; - u32 arg; - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - ret = regmap_read(pctl->regmap, - bank_offset + PINMUX_820_PULLUP_CTRL, - &arg); - if (ret) - return ret; - - arg = !!(arg & mask); - break; - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned int num_configs) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param; - unsigned int i; - u32 offset = pin - bank->gpio_chip.base; - u32 mask = BIT(offset); - - dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", - pin, bank->gpio_chip.base, mask); - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - dev_dbg(pctl->dev, " pullup\n"); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_PULLUP_CTRL1 : - PINMUX_810_PULLUP_CTRL0), - mask, mask); - break; - default: - dev_err(pctl->dev, "Property %u not supported\n", - param); - return -ENOTSUPP; - } - } - - return 0; -} - -static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned int num_configs) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - unsigned int param; - unsigned int i; - u32 offset = pin - bank->gpio_chip.base; - u32 mask = BIT(offset); - - dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", - pin, bank->gpio_chip.base, mask); - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - dev_dbg(pctl->dev, " pullup\n"); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_PULLUP_CTRL, - mask, mask); - break; - default: - dev_err(pctl->dev, "Property %u not supported\n", - param); - return -ENOTSUPP; - } - } - - return 0; -} - -static const struct pinconf_ops oxnas_ox810se_pinconf_ops = { - .pin_config_get = oxnas_ox810se_pinconf_get, - .pin_config_set = oxnas_ox810se_pinconf_set, - .is_generic = true, -}; - -static const struct pinconf_ops oxnas_ox820_pinconf_ops = { - .pin_config_get = oxnas_ox820_pinconf_get, - .pin_config_set = oxnas_ox820_pinconf_set, - .is_generic = true, -}; - -static void oxnas_gpio_irq_ack(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(data->hwirq); - - writel(mask, bank->reg_base + IRQ_PENDING); -} - -static void oxnas_gpio_irq_mask(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - unsigned int type = irqd_get_trigger_type(data); - u32 mask = BIT(data->hwirq); - - if (type & IRQ_TYPE_EDGE_RISING) - writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask, - bank->reg_base + RE_IRQ_ENABLE); - - if (type & IRQ_TYPE_EDGE_FALLING) - writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask, - bank->reg_base + FE_IRQ_ENABLE); -} - -static void oxnas_gpio_irq_unmask(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - unsigned int type = irqd_get_trigger_type(data); - u32 mask = BIT(data->hwirq); - - if (type & IRQ_TYPE_EDGE_RISING) - writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask, - bank->reg_base + RE_IRQ_ENABLE); - - if (type & IRQ_TYPE_EDGE_FALLING) - writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask, - bank->reg_base + FE_IRQ_ENABLE); -} - -static unsigned int oxnas_gpio_irq_startup(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - - oxnas_gpio_direction_input(chip, data->hwirq); - oxnas_gpio_irq_unmask(data); - - return 0; -} - -static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type) -{ - if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0) - return -EINVAL; - - irq_set_handler_locked(data, handle_edge_irq); - - return 0; -} - -static void oxnas_gpio_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct oxnas_gpio_bank *bank = gpiochip_get_data(gc); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned long stat; - unsigned int pin; - - chained_irq_enter(chip, desc); - - stat = readl(bank->reg_base + IRQ_PENDING); - - for_each_set_bit(pin, &stat, BITS_PER_LONG) - generic_handle_domain_irq(gc->irq.domain, pin); - - chained_irq_exit(chip, desc); -} - -#define GPIO_BANK(_bank) \ - { \ - .gpio_chip = { \ - .label = "GPIO" #_bank, \ - .request = gpiochip_generic_request, \ - .free = gpiochip_generic_free, \ - .get_direction = oxnas_gpio_get_direction, \ - .direction_input = oxnas_gpio_direction_input, \ - .direction_output = oxnas_gpio_direction_output, \ - .get = oxnas_gpio_get, \ - .set = oxnas_gpio_set, \ - .ngpio = PINS_PER_BANK, \ - .base = GPIO_BANK_START(_bank), \ - .owner = THIS_MODULE, \ - .can_sleep = 0, \ - }, \ - .irq_chip = { \ - .name = "GPIO" #_bank, \ - .irq_startup = oxnas_gpio_irq_startup, \ - .irq_ack = oxnas_gpio_irq_ack, \ - .irq_mask = oxnas_gpio_irq_mask, \ - .irq_unmask = oxnas_gpio_irq_unmask, \ - .irq_set_type = oxnas_gpio_irq_set_type, \ - }, \ - } - -static struct oxnas_gpio_bank oxnas_gpio_banks[] = { - GPIO_BANK(0), - GPIO_BANK(1), -}; - -static struct oxnas_pinctrl ox810se_pinctrl = { - .functions = oxnas_ox810se_functions, - .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions), - .groups = oxnas_ox810se_groups, - .ngroups = ARRAY_SIZE(oxnas_ox810se_groups), - .gpio_banks = oxnas_gpio_banks, - .nbanks = ARRAY_SIZE(oxnas_gpio_banks), -}; - -static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = { - .name = "oxnas-pinctrl", - .pins = oxnas_ox810se_pins, - .npins = ARRAY_SIZE(oxnas_ox810se_pins), - .pctlops = &oxnas_pinctrl_ops, - .pmxops = &oxnas_ox810se_pinmux_ops, - .confops = &oxnas_ox810se_pinconf_ops, - .owner = THIS_MODULE, -}; - -static struct oxnas_pinctrl ox820_pinctrl = { - .functions = oxnas_ox820_functions, - .nfunctions = ARRAY_SIZE(oxnas_ox820_functions), - .groups = oxnas_ox820_groups, - .ngroups = ARRAY_SIZE(oxnas_ox820_groups), - .gpio_banks = oxnas_gpio_banks, - .nbanks = ARRAY_SIZE(oxnas_gpio_banks), -}; - -static struct pinctrl_desc oxnas_ox820_pinctrl_desc = { - .name = "oxnas-pinctrl", - .pins = oxnas_ox820_pins, - .npins = ARRAY_SIZE(oxnas_ox820_pins), - .pctlops = &oxnas_pinctrl_ops, - .pmxops = &oxnas_ox820_pinmux_ops, - .confops = &oxnas_ox820_pinconf_ops, - .owner = THIS_MODULE, -}; - -static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = { - .desc = &oxnas_ox810se_pinctrl_desc, - .pctl = &ox810se_pinctrl, -}; - -static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = { - .desc = &oxnas_ox820_pinctrl_desc, - .pctl = &ox820_pinctrl, -}; - -static const struct of_device_id oxnas_pinctrl_of_match[] = { - { .compatible = "oxsemi,ox810se-pinctrl", - .data = &oxnas_ox810se_pinctrl_data - }, - { .compatible = "oxsemi,ox820-pinctrl", - .data = &oxnas_ox820_pinctrl_data, - }, - { }, -}; - -static int oxnas_pinctrl_probe(struct platform_device *pdev) -{ - const struct of_device_id *id; - const struct oxnas_pinctrl_data *data; - struct oxnas_pinctrl *pctl; - - id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node); - if (!id) - return -ENODEV; - - data = id->data; - if (!data || !data->pctl || !data->desc) - return -EINVAL; - - pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); - if (!pctl) - return -ENOMEM; - pctl->dev = &pdev->dev; - dev_set_drvdata(&pdev->dev, pctl); - - pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "oxsemi,sys-ctrl"); - if (IS_ERR(pctl->regmap)) { - dev_err(&pdev->dev, "failed to get sys ctrl regmap\n"); - return -ENODEV; - } - - pctl->functions = data->pctl->functions; - pctl->nfunctions = data->pctl->nfunctions; - pctl->groups = data->pctl->groups; - pctl->ngroups = data->pctl->ngroups; - pctl->gpio_banks = data->pctl->gpio_banks; - pctl->nbanks = data->pctl->nbanks; - - pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl); - if (IS_ERR(pctl->pctldev)) { - dev_err(&pdev->dev, "Failed to register pinctrl device\n"); - return PTR_ERR(pctl->pctldev); - } - - return 0; -} - -static int oxnas_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct of_phandle_args pinspec; - struct oxnas_gpio_bank *bank; - unsigned int id, ngpios; - int irq, ret; - struct gpio_irq_chip *girq; - - if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", - 3, 0, &pinspec)) { - dev_err(&pdev->dev, "gpio-ranges property not found\n"); - return -EINVAL; - } - - id = pinspec.args[1] / PINS_PER_BANK; - ngpios = pinspec.args[2]; - - if (id >= ARRAY_SIZE(oxnas_gpio_banks)) { - dev_err(&pdev->dev, "invalid gpio-ranges base arg\n"); - return -EINVAL; - } - - if (ngpios > PINS_PER_BANK) { - dev_err(&pdev->dev, "invalid gpio-ranges count arg\n"); - return -EINVAL; - } - - bank = &oxnas_gpio_banks[id]; - - bank->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(bank->reg_base)) - return PTR_ERR(bank->reg_base); - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - bank->id = id; - bank->gpio_chip.parent = &pdev->dev; - bank->gpio_chip.ngpio = ngpios; - girq = &bank->gpio_chip.irq; - girq->chip = &bank->irq_chip; - girq->parent_handler = oxnas_gpio_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = irq; - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_level_irq; - - ret = gpiochip_add_data(&bank->gpio_chip, bank); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", - id, ret); - return ret; - } - - return 0; -} - -static struct platform_driver oxnas_pinctrl_driver = { - .driver = { - .name = "oxnas-pinctrl", - .of_match_table = oxnas_pinctrl_of_match, - .suppress_bind_attrs = true, - }, - .probe = oxnas_pinctrl_probe, -}; - -static const struct of_device_id oxnas_gpio_of_match[] = { - { .compatible = "oxsemi,ox810se-gpio", }, - { .compatible = "oxsemi,ox820-gpio", }, - { }, -}; - -static struct platform_driver oxnas_gpio_driver = { - .driver = { - .name = "oxnas-gpio", - .of_match_table = oxnas_gpio_of_match, - .suppress_bind_attrs = true, - }, - .probe = oxnas_gpio_probe, -}; - -static int __init oxnas_gpio_register(void) -{ - return platform_driver_register(&oxnas_gpio_driver); -} -arch_initcall(oxnas_gpio_register); - -static int __init oxnas_pinctrl_register(void) -{ - return platform_driver_register(&oxnas_pinctrl_driver); -} -arch_initcall(oxnas_pinctrl_register); From patchwork Fri Jun 30 16:58:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298513 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D060817725 for ; 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Fri, 30 Jun 2023 09:58:52 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:35 +0200 Subject: [PATCH v2 10/15] dt-bindings: pinctrl: oxnas,pinctrl: remove obsolete bindings Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-10-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Krzysztof Kozlowski , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2520; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=lU0Rgil/ev1/BqzGapYknrWAekAzhIDCjFFvr/Tl7mg=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm4+5/g0rcYb66QxjBIlFiUjvocLVgWZT6mtpaE GF1Pn0+JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JuAAKCRB33NvayMhJ0dPvD/ 93ZAw/LIPqNPF0li9/7yv9xUx84tStF1AkO8ltYZ00U95njJe5mPlivwj+pDdPNLiCEk2nmUPunY3M 7CuVgtBbHpWcIqx8BDZ70S3yrj6NvQ4MaoES6FuoTEwqXEc8PMvk6wEkEjfL0M13jSe/oNVrYgnzlq tenzbEkFaTh5Hgi4XxDqiMvprL37YdzCRzmsoic5XqS2eewnvUAUqy+rhQ1GdnpyiOVv8V0tp4Pqm5 9cOwbashPgyJeWOsmnzN6Rae795M5pTBkJx1knCyQtXZLKEPNifnQOCfpzSjIFHuPMTqYDQzeZetvI fjP4q1vHO1m6hvP6sYHb4iMNXi4ho37b8eUabnUBZP2syBsyP+UBeL0f6wMbDE4Bqyc8i2Me9rXVVD qbaKXAAZzqiZgNKBbCRSU+kwDU0/mZVH9BNnAORdEYeYo4XSglwuLtKubLamhA1DHbMmeO5spP202f 3O5Rg17wscN4iJbKsZjfzH4YJ2Vx0gMqEO77pyJhyhxiLkXDfiHiX3ESELQpbUQb76vCDlxOvUNIis sLVWN+pk3K2ckjcQhpsFrL3blpXjHiNTZDdFkjiMf2MdFl69K2sRxnNDEvBZCAAkMBXGExG5t6kuE5 YzCjrEAZmHYK/h/PtJt2bj+n/N+O8EIkQJnxiI6dKaSy/UtKIirJ4XpqqPqw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 pinctrl bindings. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- .../devicetree/bindings/pinctrl/oxnas,pinctrl.txt | 56 ---------------------- 1 file changed, 56 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt deleted file mode 100644 index b1159434f593..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Oxford Semiconductor OXNAS SoC Family Pin Controller - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -OXNAS 'pin configuration node' is a node of a group of pins which can be -used for a specific device or function. This node represents configurations of -pins, optional function, and optional mux related configuration. - -Required properties for pin controller node: - - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl" - - oxsemi,sys-ctrl: a phandle to the system controller syscon node - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - function: Mux function for the specified pins. - - bias-pull-up: Enable weak pull-up. - -Example: - -pinctrl: pinctrl { - compatible = "oxsemi,ox810se-pinctrl"; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - pinctrl_uart2: pinctrl_uart2 { - uart2a { - pins = "gpio31"; - function = "fct3"; - }; - uart2b { - pins = "gpio32"; - function = "fct3"; - }; - }; -}; - -uart2: serial@900000 { - compatible = "ns16550a"; - reg = <0x900000 0x100000>; - clocks = <&sysclk>; - interrupts = <29>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - resets = <&reset 22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; From patchwork Fri Jun 30 16:58:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298514 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A22717725 for ; Fri, 30 Jun 2023 16:59:08 +0000 (UTC) Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2ACDD4492 for ; Fri, 30 Jun 2023 09:58:56 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3fb4146e8ceso23793945e9.0 for ; Fri, 30 Jun 2023 09:58:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144334; x=1690736334; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RLUKsP4vp/raKLTHtwvUFRJTqG/hdN77zosI8Yw2myw=; b=sVa5c1v/DkueUOCsS+MIb0EGouW76eY2gyfiQAQ4dSKuCyWJeA3bmBrQGzimmySJuV ZVoIoSrizM9pksB1Dl100COoWxOSVIdEUmsw3NH5eCfLyGUKi0XFhVF5U4lNd2oNuoGI E1NNYCk5HgtBo5I1sDgcdZ+iHACj6rVf1u6Hb18pHJv1QWD4WP1P8yFeUJ1xExTJugXL AUMNLcvs7hbekeaX5QrGQliSFPKvjFwhdHL0bQcwuSTxv2A7xsgHuDl2sBn8YtxqtlJv sySMd6ET4xfwk3ENv5SaF2DyQm0jF+J4vjCXZC9c5IxmIZQG1kr28S74KPLOlSrPp8M0 uFVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688144334; x=1690736334; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RLUKsP4vp/raKLTHtwvUFRJTqG/hdN77zosI8Yw2myw=; b=BoCJrhTh6+etn/gksVM7gycx/P3NvdKE5l+CZT+WkXMF71PRSv8YLT3Pn9nvIh6Fo/ P7AWdDythqvkSg+8WEWFnT/Cu6nGKkG9m6tiT+nwpQrt2b+WfcwNcMCkdVdRA+SFN4d/ FJcxEudqfdrY3H7gDbRxLbWW2CUsKObqV024TRbwctsu4x37/KNzRZZHUnIHBurE1K3a zdPmVTjCvTPtm4POcNr5lBXJQpjfwfdgLRHJ0tYb+mgRD32L3fXsD2E6C2uiLiQrtFHK lnMpTQ/BgLKoXc5JSTR7jt6CFoPK82+dbRlMun1pPp5T9Lwv3YB5DGls3YXCptsI5pWq 26qg== X-Gm-Message-State: ABy/qLYbd8WdNxnRiz9ItQHUpI/i5Ropr4/zwERIlFpJbjljYh3uRkEV Qo+PHCjYO8P7WbedoNRejy2I2A== X-Google-Smtp-Source: APBJJlEza6koXpLRSzsJiwPWlR4i5LXfO4P/D0KmtkFikXar2B9xsTCDhnNIiFf4wc1a8fdVyS8ysQ== X-Received: by 2002:a5d:4fc4:0:b0:313:ebf3:f817 with SMTP id h4-20020a5d4fc4000000b00313ebf3f817mr2423330wrw.22.1688144334391; Fri, 30 Jun 2023 09:58:54 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:58:53 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:36 +0200 Subject: [PATCH v2 11/15] dt-bindings: gpio: gpio_oxnas: remove obsolete bindings Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-11-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Krzysztof Kozlowski , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2380; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=Dz983lZEvCc6SwFVyqblurV6ZIa65HUG1Xc2A0bqn7M=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm4wJTRSSerqNYfifwQ1Pt541qqx0tcBG6P43WV xd4i9FuJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JuAAKCRB33NvayMhJ0XPgEA DCjZvFC0V3ejPt1N0/o80mIHNA0zrhPM/j3UrO6bINU5AQsXNX1xP2zjlRpgKhTOC9Kry0IhDZCdD5 WL0T2vk+BI+Va3NzwJv213/b8bECOoXLNNE6WIquR51sKxTq3iexFaN7SAKORBYZWNzJpqTfu/41Nt DliCF/6SErEstzu8aItxlKrfbuLYcgjaDIkLnrP9zxkcxTu21ZPLY1vD57YMLHZSxik4e/3FGMbWpp 2Pg+BIVRh/IH00JwzMSdBgAzumU8ANPQGXe3ATTr+xDKPk+WJpNXQXOYpUhyYjLs1QNGZ3MPP7YZde iUEmJ9HxUiOQaiyDcISadusL+ObaqjGz3rTFmir3Jexj5wGgO2FKcNgDcCAJCoxMMGrw1WKLpTUgH2 8HVN1jqaV/0baqMaKlTovePXtHWdHYjASjVeY/bTjirRqJT4RPeGlIvE2FsUcTduyhLiw6IxTOWLhK lva9N1TCBRTx3PwzlP1zZ7ufAI1cvHH9mCe9VRBdYBzijNZwC5jid2xpGyQ7npRA8Yycw1QIhlmgvM JsNmLwe8dqD3EaBFMKqL/dcMmG6IQDXcKoGIqtYV43O9odb5ReKfMRJM81olt8ArfGto80z6Vsp8a7 27w7UeMv8YbkcGD1lOGEjg0PMpq1jqZEhb47IOLUWfNsGXYGW1BOJamnxHXw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 gpio bindings. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Bartosz Golaszewski --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 47 ---------------------- 1 file changed, 47 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt deleted file mode 100644 index 966514744df4..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Oxford Semiconductor OXNAS SoC GPIO Controller - -Please refer to gpio.txt for generic information regarding GPIO bindings. - -Required properties: - - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio" - - reg: Base address and length for the device. - - interrupts: The port interrupt shared by all pins. - - gpio-controller: Marks the port as GPIO controller. - - #gpio-cells: Two. The first cell is the pin number and - the second cell is used to specify the gpio polarity as defined in - defined in : - 0 = GPIO_ACTIVE_HIGH - 1 = GPIO_ACTIVE_LOW - - interrupt-controller: Marks the device node as an interrupt controller. - - #interrupt-cells: Two. The first cell is the GPIO number and second cell - is used to specify the trigger type as defined in - : - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING - IRQ_TYPE_EDGE_BOTH - - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the - gpio base and count, should be in the format of numeric-gpio-range as - specified in the gpio.txt file. - -Example: - -gpio0: gpio@0 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x000000 0x100000>; - interrupts = <21>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pinctrl 0 0 32>; -}; - -keys { - ... - - button-esc { - label = "ESC"; - linux,code = <1>; - gpios = <&gpio0 12 0>; - }; -}; From patchwork Fri Jun 30 16:58:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298515 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2017D17725 for ; Fri, 30 Jun 2023 16:59:13 +0000 (UTC) Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FC4D44A3 for ; Fri, 30 Jun 2023 09:58:57 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-31409e8c145so2348983f8f.2 for ; Fri, 30 Jun 2023 09:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144336; x=1690736336; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4FgwEHIiufvN4/vrAM+EmRTKMvuGIUCUJpN7+/AjohE=; b=zJKm1O3gqfl+/l50NqDCQVslJww9J04yE89jZ5f/lU/O9RkBXTLjndN7cOTiCR52d+ 2rWtrBCNymviRY86hDdMyCddB6ShlNjbD6K2lo5+z+o6X1NUfJdkYXxeNPy7ld4+Lh+2 sYysn1DdGwZGblXk6RYANZeFevQ97VVVYiUMJJnpLk0D3ssCK1znw7XESfsbUN7O7GeR DQhavB0xiTESX7UaUitfbY6F/PHswbOkNBRvzi651+5RWH5QtNkO4lu0WopUCi8jZroa WgCPdF9MdRJx9PfrdQM8jMACd94F5U0aUvHS7+r0CDEvdNETaEHZJC54c+0x55olTUwM ZOqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688144336; x=1690736336; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4FgwEHIiufvN4/vrAM+EmRTKMvuGIUCUJpN7+/AjohE=; b=NKh6C8e5FUc49YXWzoouUk0GeXgVmXuQKvQASaGUac2k9LS3xXYVo0TYxqAQ7TV8vN W3d60y18yG7YVUqGxigilZ1/hblV3SIKoxbkHCoRVJdQfhqSkqsDJxrnryLNuHKwz1hl C37RyRfWHEaHQ8nuVule9hJsAPvL4Lk9eYh4Rcj4KtnWHEYLxV4x3QL0rZEkcY4ptJQu 84jd9FKBb10JuiHU5c+sj2uUFF1qSejmbV4d4BnIS296o+bWV8GWTRrgdHSOV5G1c6N5 4SOeQl9cFmfcfUirNHMadvEwly+fkak3qkhis91DTWy1eVzLarORvHRajlosxt4fJppk lnGg== X-Gm-Message-State: ABy/qLYcpIViJyvR3mGAcR66BUCPzXEcThmBNLgp3q2PaURyVHCU3gvL dfmIYJ9AJCB6z89oE1x8b+/qpQ== X-Google-Smtp-Source: APBJJlF+HR7IlwOv6BGJulPd3da1YOPyBnMGP5I0+G0uGCgFrxABHVR8qHNl0+04XrjGbTvktRYacg== X-Received: by 2002:adf:ed0a:0:b0:314:13e2:2f6c with SMTP id a10-20020adfed0a000000b0031413e22f6cmr2444524wro.58.1688144336059; Fri, 30 Jun 2023 09:58:56 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:58:55 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:37 +0200 Subject: [PATCH v2 12/15] power: reset: oxnas-restart: remove obsolete restart driver Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-12-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Sebastian Reichel , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=11262; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=NNcUV2Vccp2R6feBFSgnzPy5EF8i0mzkDpw8Uj3QejE=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm4ttQQcVXfjEc6zcYUSzILYTX7Rne5j6+Afkl3 GWDpCd+JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JuAAKCRB33NvayMhJ0cU8D/ 95wd5v6ygGkISEKlkwGW17FxM49F6T4SMlre7FJQHzam7WZxMKPHqmGoggmwhs+7qeLZ19TJspfC2n tFh2S5HN+040y+1vUwBeckjBbVeEJcnPszDnRxi3XumlnfKURTDPvQOI7MIhRLuSc9tChMbAMxnu4n QyPICeZm+qpMFgUdy8vKdFU7NKmP6Ge19SkD0k3SfqOB6MNijMGVBlMDJxmfoh9uPiE2KHIDo2Zs9A m1H5ddDX1dWobSPx1pnm/nlNOMAvCE6Af7f+bmGgCPoMOhtHnfYjvpbUlqd/aUSafeQUenqL8a8yY9 7CScsFjys4iQH4or+SGbcwtJkCg5NMLyMREJ+QcJQANd6D/jgefq9lVk+vmnwRKD7BE75cKdWPfX88 EBk3k6ENCFCcR9QOW25EMrbPm0ixsUH9avRngd6oDWeiwM7aoBbjUDk9H1WAT33iVkeG1x7Q+xJBFu rrSGUv+JJYS21nJjOy69NbOyEfAv7A+4KErcxKo9ZwpcG00RCfM59CtWiWEfIGkoPNI9Bx7f3mZlK2 62PSiEzqVumcUqhpMJYajHYLDAV03hudTNXrlfj7JY+iDFERrOxpNmUt1XVQkrSnFoVtDBg34SYtas rVENXk/3r4FDd4mUoo+Sja5jCeaZ5Q92ZWtqP//XHkBl7KP6e7uAZl/m9lCQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 restart feature. Acked-by: Sebastian Reichel Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- drivers/power/reset/Kconfig | 7 -- drivers/power/reset/Makefile | 1 - drivers/power/reset/oxnas-restart.c | 233 ------------------------------------ 3 files changed, 241 deletions(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index fff07b2bd77b..59e1ebb7842e 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -148,13 +148,6 @@ config POWER_RESET_ODROID_GO_ULTRA_POWEROFF help This driver supports Power off for Odroid Go Ultra device. -config POWER_RESET_OXNAS - bool "OXNAS SoC restart driver" - depends on ARCH_OXNAS - default MACH_OX820 - help - Restart support for OXNAS/PLXTECH OX820 SoC. - config POWER_RESET_PIIX4_POWEROFF tristate "Intel PIIX4 power-off driver" depends on PCI diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index d763e6735ee3..a95d1bd275d1 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o obj-$(CONFIG_POWER_RESET_LINKSTATION) += linkstation-poweroff.o obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o obj-$(CONFIG_POWER_RESET_MT6323) += mt6323-poweroff.o -obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o obj-$(CONFIG_POWER_RESET_QCOM_PON) += qcom-pon.o obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o obj-$(CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF) += odroid-go-ultra-poweroff.o diff --git a/drivers/power/reset/oxnas-restart.c b/drivers/power/reset/oxnas-restart.c deleted file mode 100644 index 13090bec058a..000000000000 --- a/drivers/power/reset/oxnas-restart.c +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * oxnas SoC reset driver - * based on: - * Microsemi MIPS SoC reset driver - * and ox820_assert_system_reset() written by Ma Hajun - * - * Copyright (c) 2013 Ma Hajun - * Copyright (c) 2017 Microsemi Corporation - * Copyright (c) 2020 Daniel Golle - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* bit numbers of reset control register */ -#define OX820_SYS_CTRL_RST_SCU 0 -#define OX820_SYS_CTRL_RST_COPRO 1 -#define OX820_SYS_CTRL_RST_ARM0 2 -#define OX820_SYS_CTRL_RST_ARM1 3 -#define OX820_SYS_CTRL_RST_USBHS 4 -#define OX820_SYS_CTRL_RST_USBHSPHYA 5 -#define OX820_SYS_CTRL_RST_MACA 6 -#define OX820_SYS_CTRL_RST_MAC OX820_SYS_CTRL_RST_MACA -#define OX820_SYS_CTRL_RST_PCIEA 7 -#define OX820_SYS_CTRL_RST_SGDMA 8 -#define OX820_SYS_CTRL_RST_CIPHER 9 -#define OX820_SYS_CTRL_RST_DDR 10 -#define OX820_SYS_CTRL_RST_SATA 11 -#define OX820_SYS_CTRL_RST_SATA_LINK 12 -#define OX820_SYS_CTRL_RST_SATA_PHY 13 -#define OX820_SYS_CTRL_RST_PCIEPHY 14 -#define OX820_SYS_CTRL_RST_STATIC 15 -#define OX820_SYS_CTRL_RST_GPIO 16 -#define OX820_SYS_CTRL_RST_UART1 17 -#define OX820_SYS_CTRL_RST_UART2 18 -#define OX820_SYS_CTRL_RST_MISC 19 -#define OX820_SYS_CTRL_RST_I2S 20 -#define OX820_SYS_CTRL_RST_SD 21 -#define OX820_SYS_CTRL_RST_MACB 22 -#define OX820_SYS_CTRL_RST_PCIEB 23 -#define OX820_SYS_CTRL_RST_VIDEO 24 -#define OX820_SYS_CTRL_RST_DDR_PHY 25 -#define OX820_SYS_CTRL_RST_USBHSPHYB 26 -#define OX820_SYS_CTRL_RST_USBDEV 27 -#define OX820_SYS_CTRL_RST_ARMDBG 29 -#define OX820_SYS_CTRL_RST_PLLA 30 -#define OX820_SYS_CTRL_RST_PLLB 31 - -/* bit numbers of clock control register */ -#define OX820_SYS_CTRL_CLK_COPRO 0 -#define OX820_SYS_CTRL_CLK_DMA 1 -#define OX820_SYS_CTRL_CLK_CIPHER 2 -#define OX820_SYS_CTRL_CLK_SD 3 -#define OX820_SYS_CTRL_CLK_SATA 4 -#define OX820_SYS_CTRL_CLK_I2S 5 -#define OX820_SYS_CTRL_CLK_USBHS 6 -#define OX820_SYS_CTRL_CLK_MACA 7 -#define OX820_SYS_CTRL_CLK_MAC OX820_SYS_CTRL_CLK_MACA -#define OX820_SYS_CTRL_CLK_PCIEA 8 -#define OX820_SYS_CTRL_CLK_STATIC 9 -#define OX820_SYS_CTRL_CLK_MACB 10 -#define OX820_SYS_CTRL_CLK_PCIEB 11 -#define OX820_SYS_CTRL_CLK_REF600 12 -#define OX820_SYS_CTRL_CLK_USBDEV 13 -#define OX820_SYS_CTRL_CLK_DDR 14 -#define OX820_SYS_CTRL_CLK_DDRPHY 15 -#define OX820_SYS_CTRL_CLK_DDRCK 16 - -/* Regmap offsets */ -#define OX820_CLK_SET_REGOFFSET 0x2c -#define OX820_CLK_CLR_REGOFFSET 0x30 -#define OX820_RST_SET_REGOFFSET 0x34 -#define OX820_RST_CLR_REGOFFSET 0x38 -#define OX820_SECONDARY_SEL_REGOFFSET 0x14 -#define OX820_TERTIARY_SEL_REGOFFSET 0x8c -#define OX820_QUATERNARY_SEL_REGOFFSET 0x94 -#define OX820_DEBUG_SEL_REGOFFSET 0x9c -#define OX820_ALTERNATIVE_SEL_REGOFFSET 0xa4 -#define OX820_PULLUP_SEL_REGOFFSET 0xac -#define OX820_SEC_SECONDARY_SEL_REGOFFSET 0x100014 -#define OX820_SEC_TERTIARY_SEL_REGOFFSET 0x10008c -#define OX820_SEC_QUATERNARY_SEL_REGOFFSET 0x100094 -#define OX820_SEC_DEBUG_SEL_REGOFFSET 0x10009c -#define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4 -#define OX820_SEC_PULLUP_SEL_REGOFFSET 0x1000ac - -struct oxnas_restart_context { - struct regmap *sys_ctrl; - struct notifier_block restart_handler; -}; - -static int ox820_restart_handle(struct notifier_block *this, - unsigned long mode, void *cmd) -{ - struct oxnas_restart_context *ctx = container_of(this, struct - oxnas_restart_context, - restart_handler); - u32 value; - - /* - * Assert reset to cores as per power on defaults - * Don't touch the DDR interface as things will come to an impromptu - * stop NB Possibly should be asserting reset for PLLB, but there are - * timing concerns here according to the docs - */ - value = BIT(OX820_SYS_CTRL_RST_COPRO) | - BIT(OX820_SYS_CTRL_RST_USBHS) | - BIT(OX820_SYS_CTRL_RST_USBHSPHYA) | - BIT(OX820_SYS_CTRL_RST_MACA) | - BIT(OX820_SYS_CTRL_RST_PCIEA) | - BIT(OX820_SYS_CTRL_RST_SGDMA) | - BIT(OX820_SYS_CTRL_RST_CIPHER) | - BIT(OX820_SYS_CTRL_RST_SATA) | - BIT(OX820_SYS_CTRL_RST_SATA_LINK) | - BIT(OX820_SYS_CTRL_RST_SATA_PHY) | - BIT(OX820_SYS_CTRL_RST_PCIEPHY) | - BIT(OX820_SYS_CTRL_RST_STATIC) | - BIT(OX820_SYS_CTRL_RST_UART1) | - BIT(OX820_SYS_CTRL_RST_UART2) | - BIT(OX820_SYS_CTRL_RST_MISC) | - BIT(OX820_SYS_CTRL_RST_I2S) | - BIT(OX820_SYS_CTRL_RST_SD) | - BIT(OX820_SYS_CTRL_RST_MACB) | - BIT(OX820_SYS_CTRL_RST_PCIEB) | - BIT(OX820_SYS_CTRL_RST_VIDEO) | - BIT(OX820_SYS_CTRL_RST_USBHSPHYB) | - BIT(OX820_SYS_CTRL_RST_USBDEV); - - regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value); - - /* Release reset to cores as per power on defaults */ - regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET, - BIT(OX820_SYS_CTRL_RST_GPIO)); - - /* - * Disable clocks to cores as per power-on defaults - must leave DDR - * related clocks enabled otherwise we'll stop rather abruptly. - */ - value = BIT(OX820_SYS_CTRL_CLK_COPRO) | - BIT(OX820_SYS_CTRL_CLK_DMA) | - BIT(OX820_SYS_CTRL_CLK_CIPHER) | - BIT(OX820_SYS_CTRL_CLK_SD) | - BIT(OX820_SYS_CTRL_CLK_SATA) | - BIT(OX820_SYS_CTRL_CLK_I2S) | - BIT(OX820_SYS_CTRL_CLK_USBHS) | - BIT(OX820_SYS_CTRL_CLK_MAC) | - BIT(OX820_SYS_CTRL_CLK_PCIEA) | - BIT(OX820_SYS_CTRL_CLK_STATIC) | - BIT(OX820_SYS_CTRL_CLK_MACB) | - BIT(OX820_SYS_CTRL_CLK_PCIEB) | - BIT(OX820_SYS_CTRL_CLK_REF600) | - BIT(OX820_SYS_CTRL_CLK_USBDEV); - - regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value); - - /* Enable clocks to cores as per power-on defaults */ - - /* Set sys-control pin mux'ing as per power-on defaults */ - regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0); - - regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0); - regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0); - - /* - * No need to save any state, as the ROM loader can determine whether - * reset is due to power cycling or programatic action, just hit the - * (self-clearing) CPU reset bit of the block reset register - */ - value = - BIT(OX820_SYS_CTRL_RST_SCU) | - BIT(OX820_SYS_CTRL_RST_ARM0) | - BIT(OX820_SYS_CTRL_RST_ARM1); - - regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value); - - pr_emerg("Unable to restart system\n"); - return NOTIFY_DONE; -} - -static int ox820_restart_probe(struct platform_device *pdev) -{ - struct oxnas_restart_context *ctx; - struct regmap *sys_ctrl; - struct device *dev = &pdev->dev; - int err = 0; - - sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node); - if (IS_ERR(sys_ctrl)) - return PTR_ERR(sys_ctrl); - - ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return -ENOMEM; - - ctx->sys_ctrl = sys_ctrl; - ctx->restart_handler.notifier_call = ox820_restart_handle; - ctx->restart_handler.priority = 192; - err = register_restart_handler(&ctx->restart_handler); - if (err) - dev_err(dev, "can't register restart notifier (err=%d)\n", err); - - return err; -} - -static const struct of_device_id ox820_restart_of_match[] = { - { .compatible = "oxsemi,ox820-sys-ctrl" }, - {} -}; - -static struct platform_driver ox820_restart_driver = { - .probe = ox820_restart_probe, - .driver = { - .name = "ox820-chip-reset", - .of_match_table = ox820_restart_of_match, - }, -}; -builtin_platform_driver(ox820_restart_driver); From patchwork Fri Jun 30 16:58:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298516 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A532C17725 for ; Fri, 30 Jun 2023 16:59:16 +0000 (UTC) Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4947144AC for ; Fri, 30 Jun 2023 09:58:59 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-31409e8c145so2349029f8f.2 for ; Fri, 30 Jun 2023 09:58:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144337; x=1690736337; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; 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Fri, 30 Jun 2023 09:58:57 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:58:57 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:38 +0200 Subject: [PATCH v2 13/15] irqchip: irq-versatile-fpga: remove obsolete oxnas compatible Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-13-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Krzysztof Kozlowski , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1082; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=Hwq/1nyBJbIaeaNsvFzhDu1oXx5gpF7OJ2azvf7yeno=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm5eVilyz5juesTZ+I8YEmM7E2RHfvZxVYP1ZZV mwVWJPmJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JuQAKCRB33NvayMhJ0dq1EA Cn2KcT1QQ1o1T7+RYh3kPUyZMDiiOc1DSphO3W/uzuy17B2do61hFjY0ldTR9LVnga9ZpODHRUkIR7 XY925yWYXfnrJgPmf02FEU37ju1/RJ424oSZMlsZ99qOyF0Gd4/pCCGcSwDiVhFH6+gx4ASuiOTZc9 UNHnfQjGBOcD/HnhgwB38S+QSpueoaTYDT6Mjc5cX0SBcGXjGp9Bx+Md99BODkp4Hd9Y5mJ+CY/+8/ w1GO8w/7Dmb7m79QwPWi6c/G5/i5MHFpAl9kc2QU/6ynyI5xPJUoJiFFLZAlNngwtVPWJENg0Q1UBw YN7jBh7yKomkrlxp6NW4WKFYSEFaKt4ybYtjmo+3DmpbQO/yc6r1k1bl46qufJJWzK1fE7phMItHf/ 1EO6h4/9HG5YhAEmtw4VuXyotDSG7xHUX84iTUqisRFHtkh3aq+vcCh42Glx+/g9amw3FUDvIQw9lm B7w/d/CgDk94Qs0gp/nKv8v/o1/fZMhTgS2mZbSXar3CcvfJEaoG3oNjk0VIK8iHwEbgROuQgEGKbz evwteKmyZKDOO1c/lCrJmD/4h3CnxXB9HxUynW1SZXjBIpchVe5SetsPfmEo1WkJzkyQvNovTcLpaJ rjkszeLvxd0rHZrpvV22nNfMyHRdmt4uWeyFu7fIz0koHI40RGLbE+d44/5Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 IRQ controller. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Marc Zyngier --- drivers/irqchip/irq-versatile-fpga.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c index ba543ed9c154..5018a06060e6 100644 --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -242,5 +242,4 @@ static int __init fpga_irq_of_init(struct device_node *node, } IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init); IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init); -IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init); #endif From patchwork Fri Jun 30 16:58:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298517 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8164517725 for ; Fri, 30 Jun 2023 16:59:24 +0000 (UTC) Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 189844684 for ; Fri, 30 Jun 2023 09:59:00 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-313e742a787so1907125f8f.1 for ; Fri, 30 Jun 2023 09:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144339; x=1690736339; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7RE5534hcGxVn/KNo4nNaHNAogiNWte5Y38IgWgMeyE=; b=gR6XOYdMaz4svBnafrAt8z5G3LWrxkXx+DHTJ3rnahYVDf05L/uW7OhXWeAWIqfQVo edwrNpWAfmHD/o9eGOgjuDipftZKWa8FzAaHW58dpkijnk56ldCGxmyCK6cPs3guGGFG s+8itEyQW84sAG5APGIGylBvPZKRmcrwxH0KM5ZIyKwbUsq0A7pSt4qK5PVnT04kSTbx 8SH3WgcUUyG2AGIiwSEzrlBfALSCgC+x36PgqYPgBFdktRGSShh5gO4yLrlJRvfmPbji GbCP6PJZqhbajC2s8LN0ysfkZ67Cx07Wy20YrtJUyJ9WhQKPBLq2r88Z/kj7Auc6BBjE GJfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688144339; x=1690736339; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7RE5534hcGxVn/KNo4nNaHNAogiNWte5Y38IgWgMeyE=; b=l/MuG7r4+cDaQjVfWzFDh4A4PjDuxmujTyYW4arWc27nzMDqf04WPATar8sBLvI0VO OWy3HV5jJ9zrgBtVUJo7fsCZVM1B6bWrKpaG24jS+vMrBB7zmGNCwR/kEjecM8ls4n92 dfgr2ltFpeHz58F6cieLLX6goVQMphs0t8Jkah3ynAwssTyIXJTU9HAmEVO7Gk+HnC8z cphI8voRBBTJeglRW8FqUdmzbZzbybaIhv2f/IhPsye1KU8Lwrl3N5+d5qh1yr2MdHAz RS0m2VoPwXSgqTPljSYyJZalr765WJ2D81gwKDowoBmvf5K8+Rq4+AnevhJcJv/21FmS L8HA== X-Gm-Message-State: AC+VfDwX/DU/RPKddWE1j11mG2+XAX/ZFTOc8HhWmeSvcCj3/22Mw/ZA KOQq0ET5u3thbb7PCbwem7gFdA== X-Google-Smtp-Source: ACHHUZ67VHZg4s+SYrTR6+84c/ufKS7Q01De9EVEy+1Ktnx9SqhFoXMa/ALr5i7wOY4YYAh12zGPEA== X-Received: by 2002:a05:6000:104d:b0:314:2c4:9fea with SMTP id c13-20020a056000104d00b0031402c49feamr7004552wrx.29.1688144339127; Fri, 30 Jun 2023 09:58:59 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:58:58 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:39 +0200 Subject: [PATCH v2 14/15] dt-bindings: interrupt-controller: arm,versatile-fpga-irq: mark oxnas compatible as deprecated Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-14-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1659; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=KAyf/uprdG2/Uxev0fRE9woiE1KO/ssntpRa1SRTGCE=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm5ebaeq5y28ag1NJPXsR2UMRtXo/2vvtxyaCAH q7bNYGyJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JuQAKCRB33NvayMhJ0a00D/ 949YBvowHmFLhM/PIxv1RNwEMg/gXdoG/wZrUvr3PALas1Cu0FQTMj4xevGv3DdfS8uo3ctM9oWYV6 By90JIc1WSNQmG+KCH4hm+/qf5oE+Gw0Z3wEBD3rsvElYFEQ3fwuPrztim6PnbGy8QDBwms1IQIfzf h7RLWvZ+E8qGp3eltGC12OHkBIePX0rXXrxjdedr/j5FIw6tA75yvupH2hOl4NrPRBMFysio3ZkDWc 9M8CG8/5lKHq46Y0YQxGe33JYEliELgFeuQZ2F2wAa8691MAj/qQgGvNkK+p0d3QC8ffPUSwyr3VmH 5Q25o0x6lw7sIETB+MEPAkNIHmB/T6nlcBZXSf8KPxekM9p89ERPpyZVYu6fgo7AgnHZ2ViAWfT0aK vJMjzlAtrNbHtCUfuytjC+4kbC3bDd9vNFE29dLvMuhuZD+DnsX/UoP/WyAgt28L2k8BVEWwSbyCaQ 2eYdh4Y+6SFl4s5/eClwjOvqKjGKgqEhW8aOec1A+m1QS5VYIk8pHdk0RSKLAMbNrghtIhbKMyQhU5 860pnYTW31uqEHzSrRV62sO4Jd841tMmNAuImfY91tf2tLKDPYfECYF1tRp4lhsqUy9s8lxoRc4IJV mozMYh/oDrg2/3lH8mszi0QhKB4BvSDNTDFh/hQrDLMyXPR5es8ILH2xAzcg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, mark the OX810 and OX820 IRQ compatible as deprecated. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Conor Dooley --- .../bindings/interrupt-controller/arm,versatile-fpga-irq.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt index 2a1d16bdf834..ea939f54c5eb 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt @@ -6,7 +6,7 @@ controllers are OR:ed together and fed to the CPU tile's IRQ input. Each instance can handle up to 32 interrupts. Required properties: -- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq" +- compatible: "arm,versatile-fpga-irq" - interrupt-controller: Identifies the node as an interrupt controller - #interrupt-cells: The number of cells to define the interrupts. Must be 1 as the FPGA IRQ controller has no configuration options for interrupt @@ -19,6 +19,8 @@ Required properties: the system till not make it possible for devices to request these interrupts. +The "oxsemi,ox810se-rps-irq" compatible is deprecated. + Example: pic: pic@14000000 { From patchwork Fri Jun 30 16:58:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13298518 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C2AD17AB3 for ; Fri, 30 Jun 2023 16:59:29 +0000 (UTC) Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 749BA4692 for ; Fri, 30 Jun 2023 09:59:03 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-313e23d0a28so2500018f8f.3 for ; Fri, 30 Jun 2023 09:59:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688144341; x=1690736341; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8Eyaf/JArFBnOJmUxcF7DoGLYY7fHW+Lur/i45+1eYA=; b=cRsI+Jc0zlEoiUnzMwgGVMTkMYll1xolMO9sNUYMp0FooJsUY4ea3qKTvrBPV3W1xS PdZIteGitEx9EYSLfRJOYktkFaGNgrjM1fFkOgOEvg9QpZfmPTHRP0w9/N2IQbu4+vs0 nb54cBQE/s37T2C5zG7nCIR1V1emFvCiO2dgZn0Pz5F2ONkZj2tZtARRUTJGEin0ve2S TMKzcm5hDnbkJdr2TIU0CbpiH29R/WxZLmENSPUSj9byP3++sCzxuhKXEZ1zIb6Wn2I2 cYCa21dnclLHYM4KbKNbtJpA/o/MUiaWI16RbEycKNxYjhX7e3isSa7OfeVEqG9msFcB UCYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688144341; x=1690736341; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Eyaf/JArFBnOJmUxcF7DoGLYY7fHW+Lur/i45+1eYA=; b=NT3bnHsPoOgCO9yXW1dqRHbPa/IpAexUyth4sqiv9g6nz9KvRJGLmgId6y0wWyLWKN /GPTPvt2lauXjhZQyTvJvmovLgJlFV7OubgI0DILwlS2UynAZxjwnJ2Q2pOUIpXK6G0G rDP+Lc0cObY8GOkwaDmBTNk7FbFwYBryxoTyhCGdJsX4k3RWvx/gDXGw9WdLgTtkAgp8 UkUVvG/o+i7fKfnXRSlLLY6SJUj7933h8XlGn+Q6VvWpH0RV/Rh3kffigizAUjxZfqBq /kX3XbSuZhSY833mHUFmU6OeqUs12yETTxfmE2KaWM9uZEhYwiLYKl2/iBuW7Tcc7uX/ /gkQ== X-Gm-Message-State: ABy/qLad8PK2rJTcJKrMHmtGBnZnGdnDyAUFbzjODD4/nGJ6AJ/3GRdu zrH0qMutTTrkPMwGYPK2T5MDEQ== X-Google-Smtp-Source: APBJJlHFfj2oZl0xVr1nB2zXh05figvBAqXp7tIH/wIQJvw0txyZj53M9A0+P0VhEGIP+1a6UuKwCw== X-Received: by 2002:a5d:49d1:0:b0:314:172b:a75a with SMTP id t17-20020a5d49d1000000b00314172ba75amr3025280wrs.26.1688144340838; Fri, 30 Jun 2023 09:59:00 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id u14-20020adfdb8e000000b003112ab916cdsm18913772wri.73.2023.06.30.09.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 09:59:00 -0700 (PDT) From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:40 +0200 Subject: [PATCH v2 15/15] MAINTAINERS: remove OXNAS entry Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230630-topic-oxnas-upstream-remove-v2-15-fb6ab3dea87c@linaro.org> References: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> In-Reply-To: <20230630-topic-oxnas-upstream-remove-v2-0-fb6ab3dea87c@linaro.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Sebastian Reichel , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-oxnas@groups.io, Neil Armstrong , Arnd Bergmann , Daniel Golle X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1154; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=/Lhm4rki32xogr5e1680FrjcVLCt+j7sMVgTOqF2+4g=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBknwm6aoHZMmN8vUbEzTBcIOV7ONJvx2yeNn0kZRnx LgLt0iSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJ8JugAKCRB33NvayMhJ0aMOD/ 4o1u07bP99PyNkyrdoo5HuA/tEA4HRTOWRFwUBK2Fr4hLcuccLKZbqEoot/K06rPOpWlmBA0xJibYq 9sx1cEJc+h2Z6AM6bLv21ZYqK5qXiv45NFZpA+avGwHQ3eQR49KMC8+J9Fb92MOTESddkVzr1uu4WE e9aJ1LI/ccd/i2cJ1q6JYWT4B5L5cIQbiI/ZtSRz8pqJ4w6w0RKypV0T7VJm80k0Jv8SmEp0Dlp+vG 2WQAMcwB/wTd8fh2LKmHED0shMiW2MEQuAkLKiPoDPvybnsLhvaPHGkWmSMXRhTZl6DoGzOsvrTeGt aTFim1T/5SP8kSCH5IyYKe7HfsE8Yt9gBcyRyqu0NC2ehuN5DgDWJ25XQwf3CLLfN8xEj42a7f9Exr zWAe21b8vupE/IPlBZdtLAl4pizrS9O5UPCdYcEh7XVCBa8AMrQci3cdYVfnZjmMz9oQqhg9nYhA0V JGXiIp5zNtWsKoFqxPzpq30E48YAl7SC9jsUWLsXeqRm5FyrRsX8HmFPcHSNlOHUHID+XL5ltvxMy9 5gbGOWZlwiRjX+X7+KZrzjzudA7BX8jOe+INgytdS3AgKSHSOiXc8Sx/ja2xf/Z/Hwp1CQeFZO2eQN 2DfMAaMQrsOrzJs9Ps4BqxlAh6NcIKGU989Dmfjl521a7QN3/cdOvxA/sGbw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove MAINTAINERS entry for OXNAS files. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong --- MAINTAINERS | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4545d4287305..cfe1bc884005 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2565,16 +2565,6 @@ S: Maintained W: http://www.digriz.org.uk/ts78xx/kernel F: arch/arm/mach-orion5x/ts78xx-* -ARM/OXNAS platform support -M: Neil Armstrong -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -L: linux-oxnas@groups.io (moderated for non-subscribers) -S: Maintained -F: arch/arm/boot/dts/ox8*.dts* -F: arch/arm/mach-oxnas/ -F: drivers/power/reset/oxnas-restart.c -N: oxnas - ARM/QUALCOMM CHROMEBOOK SUPPORT R: cros-qcom-dts-watchers@chromium.org F: arch/arm64/boot/dts/qcom/sc7180*