From patchwork Sun Jul 2 00:16:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13299138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60E70EB64DD for ; Sun, 2 Jul 2023 00:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229902AbjGBAQN (ORCPT ); Sat, 1 Jul 2023 20:16:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229533AbjGBAQM (ORCPT ); Sat, 1 Jul 2023 20:16:12 -0400 Received: from h2.cmg2.smtp.forpsi.com (h2.cmg2.smtp.forpsi.com [81.2.195.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81A2B10CE for ; Sat, 1 Jul 2023 17:16:10 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id Fkl4qyGAIv5uIFkl6qC7pR; Sun, 02 Jul 2023 02:16:08 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1688256968; bh=UCEJNQOpESPc4EiJCt4jIRYvj7zf9Z8evzoKgUnIWP4=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=n8tF2xsWeZZWdNwidh0LrTJhm8VfY9Q+eegpPpcmRatnNsoz+UOULsVPXPhK1ejWr EyEDoWcEtH1FoxABaqFyHgE+xs+3clRKheDKn6PHe1L7+WoCmYcnaXK/ATiK3kALk7 AcGi4LFPUtkQHJu++K1Cu5eJa2Hpuqr/wYHilupbKvArd06ZZHpoqmJnZoTUJBlQuh 69HoK6/fI2lqFwr5T99wyBQ5oBTZrnpg67oiKs61U8Kt6bcRe06xiWMtic5orFdgtM 7CDafaQ8sdGyj8EmXGALFSJp3OWngyzaVdtUazFGDaX7ST42ClJnOsP9IeyeSNkfEu Fw60rBKMt7TkA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1688256968; bh=UCEJNQOpESPc4EiJCt4jIRYvj7zf9Z8evzoKgUnIWP4=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=n8tF2xsWeZZWdNwidh0LrTJhm8VfY9Q+eegpPpcmRatnNsoz+UOULsVPXPhK1ejWr EyEDoWcEtH1FoxABaqFyHgE+xs+3clRKheDKn6PHe1L7+WoCmYcnaXK/ATiK3kALk7 AcGi4LFPUtkQHJu++K1Cu5eJa2Hpuqr/wYHilupbKvArd06ZZHpoqmJnZoTUJBlQuh 69HoK6/fI2lqFwr5T99wyBQ5oBTZrnpg67oiKs61U8Kt6bcRe06xiWMtic5orFdgtM 7CDafaQ8sdGyj8EmXGALFSJp3OWngyzaVdtUazFGDaX7ST42ClJnOsP9IeyeSNkfEu Fw60rBKMt7TkA== Date: Sun, 2 Jul 2023 02:16:06 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v2 1/3] usb: dwc3: dwc3-octeon: Convert to glue driver Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfLTrQkFLi0MTEclLOYJBj7KeP6OTlfblZEv3W+2zcIi+Esy+TPbQ4sFevORCgmDPvxWkpr3BbCuTs3MxzJVbqKwRjN1Lm+OIiS+Unn4Subhq8ENqCNgj L/bKhBNTnLy5t0KY/EjJ7B6G7IQDKe0w90w1hffClLtPaKNbBH3n8e9jdSl8bMUCH7v+ekFqt8zvqwhvh4KfmtFabInpvQq2i9XIHup/w4eYk1Km9h3tp5HM yyym/TRACqooEDBUYLVEPP7guppWoQnjkJvPnqPeNrOjC5oUe1fQQu5ZAg00xHTNshDhz9iNyPGnC12RsXi4VR0va287b33pC7A1E0Tn5U5U+eyp4R3Qwrob yxHaVfsW Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Move Octeon DWC3 glue code from arch/mips and use it instead of dwc3-of-simple. Signed-off-by: Ladislav Michl Acked-by: Thomas Bogendoerfer --- CHANGES: - v2: squashed move and glue conversion patch, fixed sparse warning and formatting issue. Set private data at the end of probe. Clear drvdata on remove. Added host mode only notice. Collected ack for move from arch/mips. arch/mips/cavium-octeon/Makefile | 1 - arch/mips/cavium-octeon/octeon-platform.c | 1 - drivers/usb/dwc3/Kconfig | 10 ++ drivers/usb/dwc3/Makefile | 1 + .../usb/dwc3/dwc3-octeon.c | 108 ++++++++++-------- drivers/usb/dwc3/dwc3-of-simple.c | 1 - 6 files changed, 69 insertions(+), 53 deletions(-) rename arch/mips/cavium-octeon/octeon-usb.c => drivers/usb/dwc3/dwc3-octeon.c (91%) diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 7c02e542959a..2a5926578841 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -18,4 +18,3 @@ obj-y += crypto/ obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o -obj-$(CONFIG_USB) += octeon-usb.o diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index ce05c0dd3acd..235c77ce7b18 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -450,7 +450,6 @@ static const struct of_device_id octeon_ids[] __initconst = { { .compatible = "cavium,octeon-3860-bootbus", }, { .compatible = "cavium,mdio-mux", }, { .compatible = "gpio-leds", }, - { .compatible = "cavium,octeon-7130-usb-uctl", }, {}, }; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index be954a9abbe0..98efcbb76c88 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -168,4 +168,14 @@ config USB_DWC3_AM62 The Designware Core USB3 IP is programmed to operate in in USB 2.0 mode only. Say 'Y' or 'M' here if you have one such device + +config USB_DWC3_OCTEON + tristate "Cavium Octeon Platforms" + depends on CAVIUM_OCTEON_SOC || COMPILE_TEST + default USB_DWC3 + help + Support Cavium Octeon platforms with DesignWare Core USB3 IP. + Only the host mode is currently supported. + Say 'Y' or 'M' here if you have one such device. + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 9f66bd82b639..fe1493d4bbe5 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o +obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/drivers/usb/dwc3/dwc3-octeon.c similarity index 91% rename from arch/mips/cavium-octeon/octeon-usb.c rename to drivers/usb/dwc3/dwc3-octeon.c index 2add435ad038..8d5facd881c1 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -187,7 +187,10 @@ #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 -static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); +struct dwc3_data { + struct device *dev; + void __iomem *base; +}; #ifdef CONFIG_CAVIUM_OCTEON_SOC #include @@ -233,6 +236,11 @@ static inline uint64_t dwc3_octeon_readq(void __iomem *addr) static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { } static inline void dwc3_octeon_config_gpio(int index, int gpio) { } + +static uint64_t octeon_get_io_clock_rate(void) +{ + return 150000000; +} #endif static int dwc3_octeon_get_divider(void) @@ -271,7 +279,7 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) dev_err(dev, "invalid power configuration\n"); return -EINVAL; } - dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio); + dwc3_octeon_config_gpio(((__force u64)base >> 24) & 1, gpio); /* Enable XHCI power control and set if active high or low. */ val = dwc3_octeon_readq(uctl_host_cfg_reg); @@ -383,7 +391,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) || (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) { dev_err(dev, "dwc3 controller clock init failure.\n"); - return -EINVAL; + return -EINVAL; } /* Step 4c: Deassert the controller clock divider reset. */ @@ -494,58 +502,58 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base) dwc3_octeon_writeq(uctl_ctl_reg, val); } -static int __init dwc3_octeon_device_init(void) +static int dwc3_octeon_probe(struct platform_device *pdev) { - const char compat_node_name[] = "cavium,octeon-7130-usb-uctl"; - struct platform_device *pdev; - struct device_node *node; - struct resource *res; - void __iomem *base; + struct device *dev = &pdev->dev; + struct dwc3_data *data; + int err; - /* - * There should only be three universal controllers, "uctl" - * in the device tree. Two USB and a SATA, which we ignore. - */ - node = NULL; - do { - node = of_find_node_by_name(node, "uctl"); - if (!node) - return -ENODEV; - - if (of_device_is_compatible(node, compat_node_name)) { - pdev = of_find_device_by_node(node); - if (!pdev) - return -ENODEV; - - /* - * The code below maps in the registers necessary for - * setting up the clocks and reseting PHYs. We must - * release the resources so the dwc3 subsystem doesn't - * know the difference. - */ - base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(base)) { - put_device(&pdev->dev); - return PTR_ERR(base); - } + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; - mutex_lock(&dwc3_octeon_clocks_mutex); - if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0) - dev_info(&pdev->dev, "clocks initialized.\n"); - dwc3_octeon_set_endian_mode(base); - dwc3_octeon_phy_reset(base); - mutex_unlock(&dwc3_octeon_clocks_mutex); - devm_iounmap(&pdev->dev, base); - devm_release_mem_region(&pdev->dev, res->start, - resource_size(res)); - put_device(&pdev->dev); - } - } while (node != NULL); + data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); - return 0; + err = dwc3_octeon_clocks_start(dev, data->base); + if (err) + return err; + + dwc3_octeon_set_endian_mode(data->base); + dwc3_octeon_phy_reset(data->base); + + data->dev = dev; + platform_set_drvdata(pdev, data); + + return of_platform_populate(node, NULL, NULL, dev); +} + +static void dwc3_octeon_remove(struct platform_device *pdev) +{ + struct dwc3_data *data = platform_get_drvdata(pdev); + + of_platform_depopulate(data->dev); + platform_set_drvdata(pdev, NULL); } -device_initcall(dwc3_octeon_device_init); +static const struct of_device_id dwc3_octeon_of_match[] = { + { .compatible = "cavium,octeon-7130-usb-uctl" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc3_octeon_of_match); + +static struct platform_driver dwc3_octeon_driver = { + .probe = dwc3_octeon_probe, + .remove_new = dwc3_octeon_remove, + .driver = { + .name = "dwc3-octeon", + .of_match_table = dwc3_octeon_of_match, + }, +}; +module_platform_driver(dwc3_octeon_driver); + +MODULE_ALIAS("platform:dwc3-octeon"); MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("USB driver for OCTEON III SoC"); +MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer"); diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index 71fd620c5161..e3423fbea3ed 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -172,7 +172,6 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "rockchip,rk3399-dwc3" }, - { .compatible = "cavium,octeon-7130-usb-uctl" }, { .compatible = "sprd,sc9860-dwc3" }, { .compatible = "allwinner,sun50i-h6-dwc3" }, { .compatible = "hisilicon,hi3670-dwc3" }, From patchwork Sun Jul 2 00:16:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13299139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E213C001B0 for ; Sun, 2 Jul 2023 00:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229940AbjGBARB (ORCPT ); Sat, 1 Jul 2023 20:17:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229540AbjGBARA (ORCPT ); Sat, 1 Jul 2023 20:17:00 -0400 Received: from h2.cmg2.smtp.forpsi.com (h2.cmg2.smtp.forpsi.com [81.2.195.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D8AAB2 for ; Sat, 1 Jul 2023 17:16:59 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id FkltqyGMmv5uIFkluqC7rF; Sun, 02 Jul 2023 02:16:59 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1688257019; bh=8cLAqu4SbJugHlf6NtzTCnWowB3trdRaIc06JLqcGPE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=Z63Nurucna2mYR39tEVg6DqOteUsKTgBXYhTyXE3zT91unfAnFFjh9WNhoW+K5J97 +ZWjrUbLwodqcULedtCYicndWV53ElTZ4gnNOPHJcvfyaiM+ZiSoDd8WKJoGyPjOw9 KJGqxoowpr9kZKYK0FPmHIVY1CIgCFijyq15joooXS7jwFMuuB9DjHXNCuPwLhCgHp FfXSyEaGT6DH28ggHYXxIOI/oJqmsmYRsymfvJmICI3Fk3YTpdJXHthPL2Q2ARkuuA UUfMMkpcf6JfLSsQ1xTonrfNiqHGn36kFmA4L3rdfCfR+ydelVyJAQ8BxAbuptsuud F9L13u82f4IsQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1688257019; bh=8cLAqu4SbJugHlf6NtzTCnWowB3trdRaIc06JLqcGPE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=Z63Nurucna2mYR39tEVg6DqOteUsKTgBXYhTyXE3zT91unfAnFFjh9WNhoW+K5J97 +ZWjrUbLwodqcULedtCYicndWV53ElTZ4gnNOPHJcvfyaiM+ZiSoDd8WKJoGyPjOw9 KJGqxoowpr9kZKYK0FPmHIVY1CIgCFijyq15joooXS7jwFMuuB9DjHXNCuPwLhCgHp FfXSyEaGT6DH28ggHYXxIOI/oJqmsmYRsymfvJmICI3Fk3YTpdJXHthPL2Q2ARkuuA UUfMMkpcf6JfLSsQ1xTonrfNiqHGn36kFmA4L3rdfCfR+ydelVyJAQ8BxAbuptsuud F9L13u82f4IsQ== Date: Sun, 2 Jul 2023 02:16:57 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v2 2/3] usb: dwc3: dwc3-octeon: Move node parsing into driver probe Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfDmIjgZTAJTTYm/tBu0tMJxwWMjT+Qsh08UuZvnvMp+uQDFRIkkLawsBju1cpdIj5iBg/RBtSXIElLBlrDtQaWV+hEj+xD9dK7lKNRhtNP5NtuG0qMDv bDPZpDo2dskIbO7vyAS/CA0PLsWUb+6Sp9AUqhgOq9Ki44B3bhooyjLsviErdoveGyHVidjkfRhGWrzJSA8i6d27c42r1Ajp9c7Y2q1nkAzo+KJdotCwlo5l YuyvrXFDn4P4S6xUz8FIzn9wwBQrrxZRjeqjYcGkKPkopTwhVPKY2xMuXK1/dyrzJ7jZUDOXUR0R0kB0wiTyA89s+YJeDQhJgivhTk0dwQkZrFB0baWH1V/O hRkKQo2F Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Make dwc3_octeon_clocks_start just start the clocks. Signed-off-by: Ladislav Michl --- CHANGES: -v2: if else block bracket according CodingStyle drivers/usb/dwc3/dwc3-octeon.c | 148 ++++++++++++++++----------------- 1 file changed, 71 insertions(+), 77 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 8d5facd881c1..668f6d3490b1 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -300,67 +300,14 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) return 0; } -static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) +static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base, + int ref_clk_sel, int ref_clk_fsel, + int mpll_mul) { - int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; - u32 clock_rate; + int div; u64 val; void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; - if (dev->of_node) { - const char *ss_clock_type; - const char *hs_clock_type; - - i = of_property_read_u32(dev->of_node, - "refclk-frequency", &clock_rate); - if (i) { - dev_err(dev, "No UCTL \"refclk-frequency\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-ss", &ss_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-hs", &hs_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); - return -EINVAL; - } - if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) - ref_clk_sel = 0; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 2; - else - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) - ref_clk_sel = 1; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 3; - else { - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - ref_clk_sel = 3; - } - } else - dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", - ss_clock_type); - - if ((ref_clk_sel == 0 || ref_clk_sel == 1) && - (clock_rate != 100000000)) - dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n", - clock_rate); - - } else { - dev_err(dev, "No USB UCTL device node\n"); - return -EINVAL; - } - /* * Step 1: Wait for all voltages to be stable...that surely * happened before starting the kernel. SKIP @@ -404,24 +351,6 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); - ref_clk_fsel = 0x07; - switch (clock_rate) { - default: - dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", - clock_rate); - fallthrough; - case 100000000: - mpll_mul = 0x19; - if (ref_clk_sel < 2) - ref_clk_fsel = 0x27; - break; - case 50000000: - mpll_mul = 0x32; - break; - case 125000000: - mpll_mul = 0x28; - break; - } val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); @@ -505,8 +434,72 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base) static int dwc3_octeon_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; struct dwc3_data *data; - int err; + int err, ref_clk_sel, ref_clk_fsel, mpll_mul; + uint32_t clock_rate; + const char *hs_clock_type, *ss_clock_type; + + if (!node) { + dev_err(dev, "No USB UCTL device node\n"); + return -EINVAL; + } + + if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) { + dev_err(dev, "No UCTL \"refclk-frequency\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); + return -EINVAL; + } + + ref_clk_sel = 2; + if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) + ref_clk_sel = 0; + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) + ref_clk_sel = 2; + else + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) + ref_clk_sel = 1; + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) { + ref_clk_sel = 3; + } else { + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + ref_clk_sel = 3; + } + } else { + dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", + ss_clock_type); + } + + ref_clk_fsel = 0x07; + switch (clock_rate) { + default: + dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", + clock_rate); + fallthrough; + case 100000000: + mpll_mul = 0x19; + if (ref_clk_sel < 2) + ref_clk_fsel = 0x27; + break; + case 50000000: + mpll_mul = 0x32; + break; + case 125000000: + mpll_mul = 0x28; + break; + } data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -516,7 +509,8 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(data->base)) return PTR_ERR(data->base); - err = dwc3_octeon_clocks_start(dev, data->base); + err = dwc3_octeon_clocks_start(dev, data->base, + ref_clk_sel, ref_clk_fsel, mpll_mul); if (err) return err; From patchwork Sun Jul 2 00:17:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13299140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66FC4C001B0 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1688257079; bh=3KkCu185G3ZQm3DEAyBLDCiqHHgacxJIMSCHKu0iSJk=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=KQ+G7nlrx/bM40xiPhWPmDy81TBkiQB6RzN2fLXaFXx2Fyl4Ug0IXlnEXkaop9XLY CJu90gFrjWoMqdmCFNEYQ6N50YXtdIZo8ZM1HeNrOwEWm2v4wj3a0rvWmY6kJ7MoMY m9xbiO9IzCGFjYlLL7XTi50Z1UlHrH/F4GHYfQhpc/QzFNM9a0f11TaD6zLCbDU6Ca 44DnekckCXEG87kihNj6CppHYN2x6GfAtV+nCSVhZyHS68ewIhwk6NZA3snqtNqZsE qcSBUAhnzjESXx2qJYPs9NVgNq7U8n/VFWFzH0Va/z0H5/9HagXbCl24ydttLoHUfs ArbO/nI0ElkSg== Date: Sun, 2 Jul 2023 02:17:57 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v2 3/3] usb: dwc3: Add SPDX header and copyright Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfIAna0uwwLijKGj4cA4Wl0P6kku77D86pxk63eiH+HfiVpIzSWlMkhxZO8tAZvCMarPCyd5l7qEtzKozXrR5puYaQSNU6K8wb/YMGS8sVVF85oDJrqOF 19bIOhYDnRo6RWfgZvAGzho0AKqqAlkPWmx5Xup65l5yQeKpCDESHY5cC7xkwm90yKXOax1lPImwnp7Pnpt47/oa6AC22RoG5EoVsF/BaZk4HsR9sHnmM5LR 5ClHvMtCOgYyFKKvESrNucGT2UqAyMfY5+e7nFiJ/KDEWExig3JUfSU8w3movX+W95U03+trMMboIECqm0Q4xpmafPMKeNrwOpbEVv77pPs9Y2td4h35LNEu yUv5tY0p Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl As driver is rewritten and David no longer works for Marvell (Cavium), I'm to blame for breakage. Signed-off-by: Ladislav Michl --- CHANGES: -v2: None drivers/usb/dwc3/dwc3-octeon.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 668f6d3490b1..01c43b2c0ac9 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -1,11 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * XHCI HCD glue for Cavium Octeon III SOCs. + * DWC3 glue for Cavium Octeon III SOCs. * * Copyright (C) 2010-2017 Cavium Networks - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (C) 2023 Ladislav Michl */ #include @@ -548,6 +546,6 @@ static struct platform_driver dwc3_octeon_driver = { module_platform_driver(dwc3_octeon_driver); MODULE_ALIAS("platform:dwc3-octeon"); -MODULE_AUTHOR("David Daney "); +MODULE_AUTHOR("Ladislav Michl "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer");