From patchwork Mon Jul 10 19:24:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13307526 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D54A7EB64DC for ; Mon, 10 Jul 2023 19:24:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229811AbjGJTYl (ORCPT ); Mon, 10 Jul 2023 15:24:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229659AbjGJTYi (ORCPT ); Mon, 10 Jul 2023 15:24:38 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F8F81A8 for ; Mon, 10 Jul 2023 12:24:35 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-1b8130aceefso74217035ad.2 for ; Mon, 10 Jul 2023 12:24:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689017075; x=1691609075; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=T195FWXfqucyEBgiIGQAY+Lmu6WGEseWSNrrUvHiu4k=; b=WEL8yeJBXLqzExhD6IHURdek5D4wvVU763ij1nXK8iYTaLrwHbm45oCwnW5EiOyICr ECOVHHRt04C8aCXCcHarD1e5tpbz/VD9139ooil7auwC5ZX9SeFEFSQJQEYvgMCiTJJT priMyy7eGQZOHQvWd+Rnvzdk2a6yDeqadOA2wAjDN8MohQcROJA4VCNaJhMeqzczzGNc Q4fO1VvryLtbUuk7JkXj6jkZV2sPZ65InW8KYpLm/PQIIg1Nyn5ZjHpKrB8rZ3myZCNl WhDLT/kCjBT6z1aYNMZP2KN/0p6C17+ILwBIKj2LCquGaWN+Po9fmNCZD1mreciXtBox ZcGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689017075; x=1691609075; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=T195FWXfqucyEBgiIGQAY+Lmu6WGEseWSNrrUvHiu4k=; b=kKuWZuOp++k+DYJzhy99EA0jjS8eb2eHvdY+Wk+KbaFxyP7Ey7DP3isCegF0DHeRt5 dT6zsRhjrXB8pRkPiikABkevQYtanDL9gX8PKhqc5S3lUeKghinNPxpdzSyYceVu+4d3 LEjZjRFNvYOrHsClvDwYmUrrxsTbqQszr8/3Sih2zL/l5Zl7TFYpklVcGa67zv48Tnn4 csvTbyeT/y2AUUFLOTkg9j8jSpqmHHSxntd46h0qLo4MK1hrlgkBaoM0pK4QtxULp9OA A3dl8vXYs1o/djh5F51FmqKwZ0MOP5wZE2XKD8bNTWjASdIamlGQcsIwCopgOTPO88Ms lC4w== X-Gm-Message-State: ABy/qLYEprnkFy1cIDmk+GSjkptkeKF2MbRs9VfOqy2AXzEjyOCApcxA N2w8orAkSoja2L2ZarghtMf/5qZvf1rOwgZ+qGAFJSAoBUHA5SUPiq+fjTZwWww90i2UFf3DGXl 46xJAXZM7m+agbO6XQyOzu2+MmXjB55MQLTqmQZbvdqL1dqpmvdkB4dlPEEZp/ncO3dHH/1k= X-Google-Smtp-Source: APBJJlF18xsYgsI0CxYuUZH80Cwz7kk1zPTVFelfLYuD+GDrkVgWul4z+afhe2yJxGfDVGHbruy74hyRYY9cbvtPLw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:903:41c9:b0:1b7:ef3f:5ed3 with SMTP id u9-20020a17090341c900b001b7ef3f5ed3mr13176575ple.5.1689017075354; Mon, 10 Jul 2023 12:24:35 -0700 (PDT) Date: Mon, 10 Jul 2023 19:24:24 +0000 In-Reply-To: <20230710192430.1992246-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230710192430.1992246-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230710192430.1992246-2-jingzhangos@google.com> Subject: [PATCH v5 1/6] KVM: arm64: Use guest ID register values for the sake of emulation From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since KVM now supports per-VM ID registers, use per-VM ID register values for the sake of emulation for DBGDIDR and LORegion. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index bd3431823ec5..c1a5ec1a016e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -379,7 +379,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + u64 val = IDREG(vcpu->kvm, SYS_ID_AA64MMFR1_EL1); u32 sr = reg_to_encoding(r); if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { @@ -2429,8 +2429,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu, if (p->is_write) { return ignore_write(vcpu, p); } else { - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + u64 dfr = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); + u64 pfr = IDREG(vcpu->kvm, SYS_ID_AA64PFR0_EL1); u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | From patchwork Mon Jul 10 19:24:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13307527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BA67C0015E for ; Mon, 10 Jul 2023 19:24:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229659AbjGJTYm (ORCPT ); Mon, 10 Jul 2023 15:24:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230358AbjGJTYl (ORCPT ); Mon, 10 Jul 2023 15:24:41 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41D821B4 for ; Mon, 10 Jul 2023 12:24:38 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-577323ba3d5so85247047b3.0 for ; Mon, 10 Jul 2023 12:24:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689017077; x=1691609077; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=NjXGqinFg6JbUCcCuD1314VDCv679WJcMyQaO6pNuqI=; b=riWsju77MCgLxcyPUA5zvABoTX1/n+uRhqXiNScFzay1HPX99z0tc697bB4UPgxFup v6vjFDK+OpdAh+ZfjD+AN7l24j6yRvX3XtBvROnruXBLFl2kWNA8PHx/58YzuBVEhk5A tzoGrsxzCwHBrSrfUBwlAu5r1zF87t1cTryo+Ov3gX8k5EDIk63Rk7uqhpoTmNfHtVXW iB6XkV+A/4mmcFig5KzmD1Tjd2NkDPiTGmGTlD/9MwaZtYufwCgye+a0Yei9/XK5XQg8 xopGAsDxQTs9dWPaMe8zfQxyD4pigDfKPNFKYllHwZX0MpFq1iOzO70eUexC7njvYRQ6 kegg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689017077; x=1691609077; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NjXGqinFg6JbUCcCuD1314VDCv679WJcMyQaO6pNuqI=; b=OWK7Z6Iq9VpBTPFGh5mlFFEdxSlBmmrpDcst4ixmMhFRQLQx30kTk8wJZcXWD4rm/R 2LbkaEkJXaqfFDWZEb8GavIfOTQQkKK47FmCnc7d5ApaVGJ2qpUGGSvTinmJvDlEFk4E PbvuNLXfeC4eS0hNtyHpdQkIZDShhj8i3Nfij3UmME4GRrBleJFUmX+6xB10o8v2zuLM zQPfsRno73eDDM9BTmj91bgvih+ug/Msu8J7JHSXG8yBZuk2DISG0jjnU6uItYnztO2o v55cc2fZFcF3mCMxnlZ6l9t6EEsTDUk5BX7YHiCrFjcA4CJ/aWCVeBAUncUYeGZ53YTD PUpg== X-Gm-Message-State: ABy/qLYAg0IerlkWpbtcDxTBFcsPqx/RGGORI2cZxmJ9b7+Yq0RyzK50 LMr2Run3Zu6xM/+EyWrBtmmHJZrYb69hg4rs9Y4QpSQOfoLfIZf1Vq861//CITWm8WSL1h6ztHf BkLdiRT0CwfY9KF871BdYU3ChGdDQa0s3UbwFS4KDFgsCF8mc4rR4zT/6whWSVRFCJvwDQZY= X-Google-Smtp-Source: APBJJlFU/3p3XZytGnnz4g0xxHNMZggWlz1mMLZ78y9fLOkMhIqS/5mIom3amLly/wcRCruQ7qwxSVnY/RznFpLozw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a25:ab90:0:b0:bc4:a660:528f with SMTP id v16-20020a25ab90000000b00bc4a660528fmr143365ybi.5.1689017077178; Mon, 10 Jul 2023 12:24:37 -0700 (PDT) Date: Mon, 10 Jul 2023 19:24:25 +0000 In-Reply-To: <20230710192430.1992246-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230710192430.1992246-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230710192430.1992246-3-jingzhangos@google.com> Subject: [PATCH v5 2/6] KVM: arm64: Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org All valid fields in ID_AA64DFR0_EL1 and ID_DFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c1a5ec1a016e..0160ef9cfe18 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1980,7 +1980,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .set_user = set_id_dfr0_el1, .visibility = aa32_id_visibility, .reset = read_sanitised_id_dfr0_el1, - .val = ID_DFR0_EL1_PerfMon_MASK, }, + .val = GENMASK(63, 0), }, ID_HIDDEN(ID_AFR0_EL1), AA32_ID_SANITISED(ID_MMFR0_EL1), AA32_ID_SANITISED(ID_MMFR1_EL1), @@ -2029,7 +2029,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, .reset = read_sanitised_id_aa64dfr0_el1, - .val = ID_AA64DFR0_EL1_PMUVer_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), ID_UNALLOCATED(5,3), From patchwork Mon Jul 10 19:24:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13307528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F78FEB64DC for ; Mon, 10 Jul 2023 19:24:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229954AbjGJTYp (ORCPT ); Mon, 10 Jul 2023 15:24:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230210AbjGJTYo (ORCPT ); Mon, 10 Jul 2023 15:24:44 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56101BC for ; Mon, 10 Jul 2023 12:24:40 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-57320c10635so56374007b3.3 for ; Mon, 10 Jul 2023 12:24:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689017079; x=1691609079; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=RJ6ya0NEnIa5aVQX1AiBY2Ns/ppVJUg4kBKaquDN4C0=; b=OdWaI8UetC5xlsDbivt/wI1RqtD2Ol3BBLHnxQ9/Cf9Go9SKNCN7pvoug5MOr8pFRE Jr0HJYE6+lJIFXqJiZFwE62NlyzEhmli/QtYehhll8htzke3R17cDFmL4EWRtVDdtxpj v/3b49yRvxDs3842p5I92zZ1Nxbg+u3MD2SrWdYVKspzUMp2ZxinKiQymdYZdCuRoei2 Fav1CzDCizrzfvxke6uiRWaXz9+d3t/p+qH5BHFH/8Hkr4CYv5kH/Gm2210yjr/D/U2A OJ34jvPSX4bqdF8X1d/o/dTD9bTQ9+/d/P8r54rZ+w2wkDB97xWCkJgaW1vJvrm1zxUo Dz9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689017079; x=1691609079; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=RJ6ya0NEnIa5aVQX1AiBY2Ns/ppVJUg4kBKaquDN4C0=; b=e8OyPJjJ85EODWn7oldcQmU1rCkNqf9kVEBGlRjdDp/hexSoWWsl5Isu7X4u/l6W2T 5bNq0dU1bLeSw11C4RvcV0tL+5nkkajs8aWG19jhlWsg4lhtIBU46HogLO2y1omohxE4 kGoP2LNBNyNHgpzjTjSY1LuFnKR4qn/I2hky4C1m5SRhLTRFWKMtsKgOzPEQYoSehZAe Q1Cn4mrBDpjK60VAsxTPW7FShkV6ZO/rEbxEvgrfkfdlOGBcp3PEUydYgQ1cfkzZ/Dvo eflPSe9SYPsV9AxWmD1v8M/dcP3NG+a6xYcI9SCo2OKm7wxbnjpiTWU3Skg7e3z3qe47 FNOQ== X-Gm-Message-State: ABy/qLaKg+8Csymn0q8boXscsED035Jd92RdO/ctUqs6pFxZ+YoaqhEX S7CTqgcZQPOsEdOo1K30o0TUUlAsD0J33J6ejcQvff6xV7wqbzXiRTQhuj+/rVTN8lg+ZN9xdDr tDrr7g8EYX2aTKRBvs3JCdJbEBPQIRCyGv94WUrjfG8sWTnk5Sxb8hHc7lP/UJjSFfPDeysg= X-Google-Smtp-Source: APBJJlGrizomlrXrfIIBON5g1LdEHWOUxmR3lblulK7dG7BSaVkBpJJIgLVla3mrwr0NssOyEnvwpwXcUtXHepnUaA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a25:508:0:b0:c66:b847:544d with SMTP id 8-20020a250508000000b00c66b847544dmr113736ybf.1.1689017079311; Mon, 10 Jul 2023 12:24:39 -0700 (PDT) Date: Mon, 10 Jul 2023 19:24:26 +0000 In-Reply-To: <20230710192430.1992246-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230710192430.1992246-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230710192430.1992246-4-jingzhangos@google.com> Subject: [PATCH v5 3/6] KVM: arm64: Reject attempts to set invalid debug arch version From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Oliver Upton The debug architecture is mandatory in ARMv8, so KVM should not allow userspace to configure a vCPU with less than that. Of course, this isn't handled elegantly by the generic ID register plumbing, as the respective ID register fields have a nonzero starting value. Add an explicit check for debug versions less than v8 of the architecture. Signed-off-by: Oliver Upton Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0160ef9cfe18..c44504038ae9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1496,6 +1496,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { + u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); /* @@ -1515,6 +1516,13 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; + /* + * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a + * nonzero minimum safe value. + */ + if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } @@ -1536,6 +1544,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, u64 val) { u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); + u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { val &= ~ID_DFR0_EL1_PerfMon_MASK; @@ -1551,6 +1560,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) return -EINVAL; + if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } From patchwork Mon Jul 10 19:24:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13307529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA115EB64DC for ; Mon, 10 Jul 2023 19:24:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231217AbjGJTYt (ORCPT ); Mon, 10 Jul 2023 15:24:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230377AbjGJTYr (ORCPT ); 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Mon, 10 Jul 2023 12:24:41 -0700 (PDT) Date: Mon, 10 Jul 2023 19:24:27 +0000 In-Reply-To: <20230710192430.1992246-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230710192430.1992246-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230710192430.1992246-5-jingzhangos@google.com> Subject: [PATCH v5 4/6] KVM: arm64: Enable writable for ID_AA64PFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org All valid fields in ID_AA64PFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c44504038ae9..967ecd57a86a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2026,7 +2026,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_reg, .reset = read_sanitised_id_aa64pfr0_el1, - .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), From patchwork Mon Jul 10 19:24:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13307530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17707EB64DA for ; Mon, 10 Jul 2023 19:24:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230358AbjGJTYv (ORCPT ); Mon, 10 Jul 2023 15:24:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230487AbjGJTYr (ORCPT ); Mon, 10 Jul 2023 15:24:47 -0400 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60849E3 for ; Mon, 10 Jul 2023 12:24:43 -0700 (PDT) Received: by mail-pg1-x549.google.com with SMTP id 41be03b00d2f7-553d076dce5so5583926a12.3 for ; Mon, 10 Jul 2023 12:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689017083; x=1691609083; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=q8Pfm1k8D0yA8LpBE9VtBtVTcRMyZS82/djAneCpkmQ=; b=GDvwqv1MlzXGhRLJnLJVug7YjvSyOR6eGB5341bF6QxHQZRZgkvaDlH66y4otQAjxR 44UbQIWUSOEUnsrC+JRRpIOD794NJBNrvpilQ7LO6keqcvGltAH1FCmFC3SyXkOwYQ/0 crkiuQnUI2yGw0A4pjGjbwtLO3U6I5Dh1NwZzexJa3qLV/JxBB+WCx0PBSJDgoXI72sq LXWeycLBLLeq7lyQ+Kz3VJhHfDhYEvJ/rpKj4QaoZuWnuNfv2i5xlOK+8ONgEsLm1Gze 4kc8pmZHweX9syFCVFkCQQ7hmDa3KevbPWic1vjbctzP5FGA9XSCZpASTHh3DdJ0ZRsF merg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689017083; x=1691609083; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=q8Pfm1k8D0yA8LpBE9VtBtVTcRMyZS82/djAneCpkmQ=; b=jW3+CZ2QMCA/ustvXfIgs+uAufaVKTZxNMdU35YfRB+u8vysKVnuZTqdDV2oogDFqd QrrRPRql5ied51ylQ4n3+0AR7zLDSyr/5mC4uYMvBVrjDo5dragfvHfz9PqW6RG0rHJ8 wcxc54i3YxhAqFXJIo0tMXbxDEKsIupIKRwWoVG6TCUzzCEhSJs0LTwoOxiTIqANqr+A 93X7WHD8o6TmGV/uAk3Vu95GinCvZoKYXALGF0vXQ+WVoGOrPhKu2UgTcwFfExdceAeU 3gZL3BX+K+P/E9OVKxBIkbj0BHb262L2qTIUW1R8NcrVkfRWf4NkEjkZYRQAAeXWzx+K Isfg== X-Gm-Message-State: ABy/qLZJ79L3OUxh5AWVP6/flMJ434QNOBGyxWY5Z9r3dLU+MhDl8/i4 /FcB0gCmtQXkft9aSr8JMuVfdahIwVtd45z/SAhW0aryHyiwh7x3Z9EAUpdeDuKsgHcjcdAxg3Z 3RtYmswfyY642Fzmbfdawi4qtpkRcGP7BG/6kMpjNDScNOEiNSXgnfEgkx1bmGxPlOz2KlzM= X-Google-Smtp-Source: APBJJlGBCHc1RRKkPANqOkNMUbhIdTsh4hoWApD9cH5zSD49oQpk7M8yIJXyvY9F4ifLaUr+n7yMTQtPbIKIxkg7Jw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a63:6:0:b0:550:d2d6:525b with SMTP id 6-20020a630006000000b00550d2d6525bmr9180529pga.12.1689017082796; Mon, 10 Jul 2023 12:24:42 -0700 (PDT) Date: Mon, 10 Jul 2023 19:24:28 +0000 In-Reply-To: <20230710192430.1992246-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230710192430.1992246-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230710192430.1992246-6-jingzhangos@google.com> Subject: [PATCH v5 5/6] KVM: arm64: Enable writable for ID_AA64MMFR{0, 1, 2, 3}_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Enable writable from userspace for ID_AA64MMFR{0, 1, 2, 3}_EL1. Added a macro for defining general writable idregs. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 967ecd57a86a..78ccc95624fa 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1340,9 +1340,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS); break; - case SYS_ID_AA64MMFR2_EL1: - val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; - break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -1566,6 +1563,18 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, return set_id_reg(vcpu, rd, val); } +static u64 read_sanitised_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + u64 val; + u32 id = reg_to_encoding(rd); + + val = read_sanitised_ftr_reg(id); + val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; + + return val; +} + /* * cpufeature ID register user accessors * @@ -1840,6 +1849,16 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, .val = 0, \ } +#define ID_SANITISED_WRITABLE(name) { \ + SYS_DESC(SYS_##name), \ + .access = access_id_reg, \ + .get_user = get_id_reg, \ + .set_user = set_id_reg, \ + .visibility = id_visibility, \ + .reset = kvm_read_sanitised_id_reg, \ + .val = GENMASK(63, 0), \ +} + /* sys_reg_desc initialiser for known cpufeature ID registers */ #define AA32_ID_SANITISED(name) { \ SYS_DESC(SYS_##name), \ @@ -2061,10 +2080,15 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(6,7), /* CRm=7 */ - ID_SANITISED(ID_AA64MMFR0_EL1), - ID_SANITISED(ID_AA64MMFR1_EL1), - ID_SANITISED(ID_AA64MMFR2_EL1), - ID_SANITISED(ID_AA64MMFR3_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR0_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR1_EL1), + { SYS_DESC(SYS_ID_AA64MMFR2_EL1), + .access = access_id_reg, + .get_user = get_id_reg, + .set_user = set_id_reg, + .reset = read_sanitised_id_aa64mmfr2_el1, + .val = GENMASK(63, 0), }, + ID_SANITISED_WRITABLE(ID_AA64MMFR3_EL1), ID_UNALLOCATED(7,4), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6), From patchwork Mon Jul 10 19:24:29 2023 Content-Type: text/plain; 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Mon, 10 Jul 2023 12:24:44 -0700 (PDT) Date: Mon, 10 Jul 2023 19:24:29 +0000 In-Reply-To: <20230710192430.1992246-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230710192430.1992246-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230710192430.1992246-7-jingzhangos@google.com> Subject: [PATCH v5 6/6] KVM: arm64: selftests: Test for setting ID register from usersapce From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a test to verify setting ID registers from userapce is handled correctly by KVM. Signed-off-by: Jing Zhang --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/aarch64/set_id_regs.c | 163 ++++++++++++++++++ 2 files changed, 164 insertions(+) create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index c692cc86e7da..87ceadc1292a 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -144,6 +144,7 @@ TEST_GEN_PROGS_aarch64 += aarch64/get-reg-list TEST_GEN_PROGS_aarch64 += aarch64/hypercalls TEST_GEN_PROGS_aarch64 += aarch64/page_fault_test TEST_GEN_PROGS_aarch64 += aarch64/psci_test +TEST_GEN_PROGS_aarch64 += aarch64/set_id_regs TEST_GEN_PROGS_aarch64 += aarch64/smccc_filter TEST_GEN_PROGS_aarch64 += aarch64/vcpu_width_config TEST_GEN_PROGS_aarch64 += aarch64/vgic_init diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c new file mode 100644 index 000000000000..e2242ef36bab --- /dev/null +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * set_id_regs - Test for setting ID register from usersapce. + * + * Copyright (c) 2023 Google LLC. + * + * + * Test that KVM supports setting ID registers from userspace and handles the + * feature set correctly. + */ + +#include +#include "kvm_util.h" +#include "processor.h" +#include "test_util.h" +#include + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +struct reg_feature { + uint64_t reg; + uint64_t ftr_mask; +}; + +static void guest_code(void) +{ + for (;;) + GUEST_SYNC(0); +} + +static struct reg_feature lower_safe_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS) }, + { KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1), ARM64_FEATURE_MASK(ID_DFR0_COPDBG) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), ARM64_FEATURE_MASK(ID_AA64PFR0_EL3) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN4) }, +}; + +static void test_user_set_lower_safe(struct kvm_vcpu *vcpu) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lower_safe_reg_ftrs); i++) { + struct reg_feature *reg_ftr = lower_safe_reg_ftrs + i; + uint64_t val, new_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + + /* Set a safe value for the feature */ + if (ftr > 0) + ftr--; + + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + + vcpu_set_reg(vcpu, reg_ftr->reg, val); + vcpu_get_reg(vcpu, reg_ftr->reg, &new_val); + ASSERT_EQ(new_val, val); + } +} + +static struct reg_feature exact_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER) }, +}; + +static void test_user_set_exact(struct kvm_vcpu *vcpu) +{ + int i, r; + + for (i = 0; i < ARRAY_SIZE(exact_reg_ftrs); i++) { + struct reg_feature *reg_ftr = exact_reg_ftrs + i; + uint64_t val, old_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + old_val = val; + + /* Exact match */ + vcpu_set_reg(vcpu, reg_ftr->reg, val); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + + /* Smaller value */ + if (ftr > 0) + ftr--; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + + /* Bigger value */ + ftr += 2; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + } +} + +static struct reg_feature fail_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS) }, + { KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1), ARM64_FEATURE_MASK(ID_DFR0_MPROFDBG) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), ARM64_FEATURE_MASK(ID_AA64PFR0_EL2) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN64) }, +}; + +static void test_user_set_fail(struct kvm_vcpu *vcpu) +{ + int i, r; + + for (i = 0; i < ARRAY_SIZE(fail_reg_ftrs); i++) { + struct reg_feature *reg_ftr = fail_reg_ftrs + i; + uint64_t val, old_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + + /* Set a invalid value (too big) for the feature */ + ftr++; + + old_val = val; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + } +} + +int main(void) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + + ksft_print_header(); + ksft_set_plan(3); + + test_user_set_lower_safe(vcpu); + ksft_test_result_pass("test_user_set_lower_safe\n"); + + test_user_set_exact(vcpu); + ksft_test_result_pass("test_user_set_exact\n"); + + test_user_set_fail(vcpu); + ksft_test_result_pass("test_user_set_fail\n"); + + kvm_vm_free(vm); + + ksft_finished(); +}