From patchwork Mon Jul 10 20:58:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Eichenberger X-Patchwork-Id: 13307648 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4979A154BA for ; Mon, 10 Jul 2023 20:59:07 +0000 (UTC) Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C87CA8 for ; Mon, 10 Jul 2023 13:59:05 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3fc0aecf15bso24094425e9.1 for ; Mon, 10 Jul 2023 13:59:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689022743; x=1691614743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Fjf5v9UuafzTHrJxUsERoLDEtugSFZ4poO5yBpVHGE=; b=If7u7GV7P5Vqvn9YzZElu4NM4khCBPoT9D41y4s9UPaeyYphZopWXEGFGmLN7qzvMv jY45HLJ7kv1XpcGpFYz50PvbDHdzkjTmD22IlPvf2AZgrT05+SxD3El6HFjiDUpQR6AT 0H6LJXG5M0SY6q/lLcUAdKNzEZibeXyAia9zQqO1Mb2h+3JzQWsaK175ZQ4QG7KWflcN eLXQ0lGIea/B2IhSzcZiHqukaSXtN/TU6yknTxHYeLzQaHdjQQ+ZRrSZX5eD0AV1HVyO f7F0iCopIXQX7C9GMmNZfVPKkoP+5A7bdNo1kcXA+VXwAl9qD2/Ikrg5L5Bffv1W1cAC bthA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689022743; x=1691614743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Fjf5v9UuafzTHrJxUsERoLDEtugSFZ4poO5yBpVHGE=; b=NrCWAzODG5WEbLlUMDGTpTT2OuuRnY2EBk770N4U8e0Gccz6akdFmpVhHbqnqoxqbc E8MfXIafOJEJ0MB1ta2b/N+v19/g7rf54aCg14XiYrlLM6SmQU+Re43uHGfrBUsUYoUo RRmGRNAvUllHFM0W9AFs6COtHGbz5I3n1wbq3WQttkT3HPUcX1EJfwDX1YW4mQMq1a5P riP1yOqSKxDGGvIbUGIhh0hTmXze5ZxZ16+x9kRV8ZcSVmxa9VMmysCOKcIiR10X7Zkq ZQvtdEFn/AQDzgmWN5aFpEb8GoAQ1AuToKHzXo/8IUzSl++eFi37HGifbZkl+NPvlTP4 AGpg== X-Gm-Message-State: ABy/qLagTeuTfUadjushrbFLxOd/pJnJS3eBF4QK3/FafeMpaW136HQA oYUr1Ng8OKLiF5AwgQiTFv7C9hsxIq3jiw== X-Google-Smtp-Source: APBJJlHquV74DO0lYeXMHeMmxhl2J17Nl5qBaMDrUAjSQyq1Hvzi9iFNaF1llb7YVYDqpOFG1qhkLA== X-Received: by 2002:a7b:ce11:0:b0:3f7:f584:5796 with SMTP id m17-20020a7bce11000000b003f7f5845796mr13233428wmc.2.1689022743269; Mon, 10 Jul 2023 13:59:03 -0700 (PDT) Received: from eichest-laptop.lan ([2a02:168:af72:0:f6df:53b3:3114:b666]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c025200b003fbca942499sm11167880wmj.14.2023.07.10.13.59.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 13:59:02 -0700 (PDT) From: Stefan Eichenberger To: netdev@vger.kernel.org, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, francesco.dolcini@toradex.com Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, eichest@gmail.com Subject: [PATCH net-next v2 1/4] net: phy: add the link modes for 1000BASE-T1 Ethernet PHY Date: Mon, 10 Jul 2023 22:58:57 +0200 Message-Id: <20230710205900.52894-2-eichest@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230710205900.52894-1-eichest@gmail.com> References: <20230710205900.52894-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org This patch adds the link modes for the 1000BASE-T1 Ethernet PHYs. It supports 100BASE-T1/1000BASE-T1 in full duplex mode. So far I could not find a 1000BASE-T1 PHY that also supports 10BASE-T1, so this mode is not added. Signed-off-by: Stefan Eichenberger --- drivers/net/phy/phy_device.c | 14 ++++++++++++++ include/linux/phy.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 0c2014accba7d..acc8950f08cfa 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -50,6 +50,9 @@ EXPORT_SYMBOL_GPL(phy_basic_t1_features); __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init; EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features); +__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_t1_features) __ro_after_init; +EXPORT_SYMBOL_GPL(phy_gbit_t1_features); + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init; EXPORT_SYMBOL_GPL(phy_gbit_features); @@ -109,6 +112,13 @@ const int phy_basic_t1s_p2mp_features_array[2] = { }; EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features_array); +const int phy_gbit_t1_features_array[3] = { + ETHTOOL_LINK_MODE_TP_BIT, + ETHTOOL_LINK_MODE_100baseT1_Full_BIT, + ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, +}; +EXPORT_SYMBOL_GPL(phy_gbit_t1_features_array); + const int phy_gbit_features_array[2] = { ETHTOOL_LINK_MODE_1000baseT_Half_BIT, ETHTOOL_LINK_MODE_1000baseT_Full_BIT, @@ -165,6 +175,10 @@ static void features_init(void) linkmode_set_bit_array(phy_basic_t1s_p2mp_features_array, ARRAY_SIZE(phy_basic_t1s_p2mp_features_array), phy_basic_t1s_p2mp_features); + /* 1000 full, TP */ + linkmode_set_bit_array(phy_gbit_t1_features_array, + ARRAY_SIZE(phy_gbit_t1_features_array), + phy_gbit_t1_features); /* 10/100 half/full + 1000 half/full */ linkmode_set_bit_array(phy_basic_ports_array, diff --git a/include/linux/phy.h b/include/linux/phy.h index 11c1e91563d47..6c71f10e0f7f0 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -47,6 +47,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init; +extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_t1_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init; extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init; @@ -58,6 +59,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init; #define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features) #define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features) #define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features) +#define PHY_GBIT_T1_FEATURES ((unsigned long *)&phy_gbit_t1_features) #define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features) #define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features) #define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features) From patchwork Mon Jul 10 20:58:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Eichenberger X-Patchwork-Id: 13307650 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41894156F0 for ; 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Mon, 10 Jul 2023 13:59:03 -0700 (PDT) From: Stefan Eichenberger To: netdev@vger.kernel.org, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, francesco.dolcini@toradex.com Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, eichest@gmail.com Subject: [PATCH net-next v2 2/4] net: phy: add registers to support 1000BASE-T1 Date: Mon, 10 Jul 2023 22:58:58 +0200 Message-Id: <20230710205900.52894-3-eichest@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230710205900.52894-1-eichest@gmail.com> References: <20230710205900.52894-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add registers and definitions to support 1000BASE-T1. This includes the PCS Control and Status registers (3.2304 and 3.2305) as well as some missing bits on the PMA/PMD extended ability register (1.18) and PMA/PMD CTRL (1.2100) register. Signed-off-by: Stefan Eichenberger --- include/uapi/linux/mdio.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index b826598d1e94c..ffa821cb291a5 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -82,6 +82,8 @@ #define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */ #define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */ #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */ +#define MDIO_PCS_1000BT1_CTRL 2304 /* 1000BASE-T1 PCS control register */ +#define MDIO_PCS_1000BT1_STAT 2305 /* 1000BASE-T1 PCS status register */ /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ @@ -332,6 +334,7 @@ #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */ /* BASE-T1 PMA/PMD extended ability register. */ +#define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002 /* 1000BASE-T1 Ability */ #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */ /* BASE-T1 auto-negotiation advertisement register [15:0] */ @@ -373,7 +376,14 @@ #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */ /* BASE-T1 PMA/PMD control register */ -#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */ +#define MDIO_PMA_PMD_BT1_CTRL_STRAP 0x000F /* Type selection (Strap) */ +#define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001 /* Select 1000BASE-T1 */ +#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */ + +/* 1000BASE-T1 PCS control register */ +#define MDIO_PCS_1000BT1_LOW_POWER 0x0800 /* Low power mode */ +#define MDIO_PCS_1000BT1_DISABLE_TX 0x4000 /* Global PMA transmit disable */ +#define MDIO_PCS_1000BT1_CTRL_RESET 0x8000 /* Software reset value */ /* EEE Supported/Advertisement/LP Advertisement registers. * From patchwork Mon Jul 10 20:58:59 2023 Content-Type: text/plain; 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Mon, 10 Jul 2023 13:59:05 -0700 (PDT) Received: from eichest-laptop.lan ([2a02:168:af72:0:f6df:53b3:3114:b666]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c025200b003fbca942499sm11167880wmj.14.2023.07.10.13.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 13:59:05 -0700 (PDT) From: Stefan Eichenberger To: netdev@vger.kernel.org, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, francesco.dolcini@toradex.com Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, eichest@gmail.com Subject: [PATCH net-next v2 3/4] net: phy: c45: add support for 1000BASE-T1 Date: Mon, 10 Jul 2023 22:58:59 +0200 Message-Id: <20230710205900.52894-4-eichest@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230710205900.52894-1-eichest@gmail.com> References: <20230710205900.52894-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add support for 1000BASE-T1 to the forced link setup. Signed-off-by: Stefan Eichenberger --- drivers/net/phy/phy-c45.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c index 93ed072233779..ec1232066b914 100644 --- a/drivers/net/phy/phy-c45.c +++ b/drivers/net/phy/phy-c45.c @@ -108,7 +108,7 @@ EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); */ int genphy_c45_pma_setup_forced(struct phy_device *phydev) { - int ctrl1, ctrl2, ret; + int bt1_ctrl, ctrl1, ctrl2, ret; /* Half duplex is not supported */ if (phydev->duplex != DUPLEX_FULL) @@ -176,6 +176,12 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev) ret = genphy_c45_pma_baset1_setup_master_slave(phydev); if (ret < 0) return ret; + + bt1_ctrl = 0; + if (phydev->speed == SPEED_1000) + bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000; + phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, + MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl); } return genphy_c45_an_disable_aneg(phydev); @@ -976,6 +982,10 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev) phydev->supported, val & MDIO_PMA_PMD_BT1_B10L_ABLE); + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, + phydev->supported, + val & MDIO_PMA_PMD_BT1_B1000_ABLE); + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); if (val < 0) return val; From patchwork Mon Jul 10 20:59:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Eichenberger X-Patchwork-Id: 13307652 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF0A11640B for ; Mon, 10 Jul 2023 20:59:09 +0000 (UTC) Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3312DA8 for ; Mon, 10 Jul 2023 13:59:08 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-3fbea14700bso51011235e9.3 for ; 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This driver is minimalistic, but already allows to detect the link, switch between 100BASE-T1 and 1000BASE-T1 and switch between master and slave mode. Autonegotiation supported by the PHY is not yet implemented. Signed-off-by: Stefan Eichenberger --- drivers/net/phy/Kconfig | 6 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/marvell-88q2xxx.c | 149 ++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 drivers/net/phy/marvell-88q2xxx.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 78e6981650d94..87b8238587173 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -217,6 +217,12 @@ config MARVELL_10G_PHY help Support for the Marvell Alaska MV88X3310 and compatible PHYs. +config MARVELL_88Q2XXX_PHY + tristate "Marvell 88Q2XXX PHY" + help + Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet + PHYs. + config MARVELL_88X2222_PHY tristate "Marvell 88X2222 PHY" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 2fe51ea83babe..35142780fc9da 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o obj-$(CONFIG_LXT_PHY) += lxt.o obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o obj-$(CONFIG_MARVELL_PHY) += marvell.o +obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o diff --git a/drivers/net/phy/marvell-88q2xxx.c b/drivers/net/phy/marvell-88q2xxx.c new file mode 100644 index 0000000000000..a073124c33f5e --- /dev/null +++ b/drivers/net/phy/marvell-88q2xxx.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell 88Q2XXX automotive 100BASE-T1/1000BASE-T1 PHY driver + */ +#include +#include +#include + +#define MARVELL_PHY_ID_88Q2110 0x002b0981 + +static int mv88q2xxx_soft_reset(struct phy_device *phydev) +{ + return phy_write_mmd(phydev, MDIO_MMD_PCS, + MDIO_PCS_1000BT1_CTRL, MDIO_PCS_1000BT1_CTRL_RESET); +} + +static int mv88q2xxx_read_link(struct phy_device *phydev) +{ + u16 ret1, ret2; + + /* The 88Q2XXX PHYs do not have the PMA/PMD status register available, + * therefore we need to read the link status from the vendor specific + * registers. + */ + if (phydev->speed == SPEED_1000) { + /* Read twice to clear the latched status */ + ret1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_STAT); + ret1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_STAT); + /* Read vendor specific Auto-Negotiation status register to get + * local and remote receiver status + */ + ret2 = phy_read_mmd(phydev, MDIO_MMD_AN, 0x8001); + } else { + /* Read vendor specific status registers, the registers are not + * documented but they can be found in the Software + * Initialization Guide + */ + ret1 = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8109); + ret2 = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8108); + } + + /* Check the link status according to Software Initialization Guide */ + return (0x0 != (ret1 & 0x0004)) && (0x0 != (ret2 & 0x3000)) ? 1 : 0; +} + +static int mv88q2xxx_read_status(struct phy_device *phydev) +{ + int ret; + + phydev->link = mv88q2xxx_read_link(phydev); + + ret = genphy_c45_read_pma(phydev); + if (ret) + return ret; + + return 0; +} + +static int mv88q2xxx_config_aneg(struct phy_device *phydev) +{ + int ret; + + ret = genphy_c45_config_aneg(phydev); + if (ret) + return ret; + + ret = mv88q2xxx_soft_reset(phydev); + if (ret) + return ret; + + return 0; +} + +static int mv88q2xxx_config_init(struct phy_device *phydev) +{ + int ret; + + /* The 88Q2XXX PHYs do have the extended ability register available, but + * register MDIO_PMA_EXTABLE where they should signalize it does not + * work according to specification. Therefore, we force it here. + */ + phydev->pma_extable = MDIO_PMA_EXTABLE_BT1; + + /* Read the current PHY configuration */ + ret = genphy_c45_read_pma(phydev); + if (ret) + return ret; + + return mv88q2xxx_config_aneg(phydev); +} + +static int mv88q2xxx_probe(struct phy_device *phydev) +{ + return 0; +} + +static int mv88q2xxxx_get_sqi(struct phy_device *phydev) +{ + u16 value; + + if (phydev->speed == SPEED_100) { + /* Read the SQI from the vendor specific receiver status + * register + */ + value = (phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8230) >> 12) & 0x0F; + } else { + /* Read from vendor specific registers, they are not documented + * but can be found in the Software Initialization Guide. Only + * revisions >= A0 are supported. + */ + phy_modify_mmd(phydev, MDIO_MMD_PCS, 0xFC5D, 0x00FF, 0x00AC); + value = phy_read_mmd(phydev, MDIO_MMD_PCS, 0xfc88) & 0x0F; + } + + return value; +} + +static int mv88q2xxxx_get_sqi_max(struct phy_device *phydev) +{ + return 15; +} + +static struct phy_driver mv88q2xxx_driver[] = { + { + .phy_id = MARVELL_PHY_ID_88Q2110, + .phy_id_mask = MARVELL_PHY_ID_MASK, + .features = PHY_GBIT_T1_FEATURES, + .name = "mv88q2110", + .probe = mv88q2xxx_probe, + .soft_reset = mv88q2xxx_soft_reset, + .config_init = mv88q2xxx_config_init, + .read_status = mv88q2xxx_read_status, + .config_aneg = mv88q2xxx_config_aneg, + .set_loopback = genphy_c45_loopback, + .get_sqi = mv88q2xxxx_get_sqi, + .get_sqi_max = mv88q2xxxx_get_sqi_max, + }, +}; + +module_phy_driver(mv88q2xxx_driver); + +static struct mdio_device_id __maybe_unused mv88q2xxx_tbl[] = { + { MARVELL_PHY_ID_88Q2110, MARVELL_PHY_ID_MASK }, + { /*sentinel*/ } +}; +MODULE_DEVICE_TABLE(mdio, mv88q2xxx_tbl); + +MODULE_DESCRIPTION("Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet PHY driver"); +MODULE_LICENSE("GPL");