From patchwork Wed Jul 12 10:32:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66BEAC001B0 for ; Wed, 12 Jul 2023 10:34:06 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562201.878791 (Exim 4.92) (envelope-from ) id 1qJXAM-00066u-85; Wed, 12 Jul 2023 10:33:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562201.878791; Wed, 12 Jul 2023 10:33:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAM-00065M-2Q; Wed, 12 Jul 2023 10:33:50 +0000 Received: by outflank-mailman (input) for mailman id 562201; Wed, 12 Jul 2023 10:33:48 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAK-00061z-Tc for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:48 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9556afb5-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:33:47 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 15B614EE0C87; Wed, 12 Jul 2023 12:33:46 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9556afb5-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 01/15] x86/cpufreq: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:02 +0200 Message-Id: <4f22e7c9de1ca407d976891774ad7c74df6cb36f.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- Changes in v3: - change 'Signed-off-by' ordering Changes in v2: - change commit title to make it unique - change commit message --- xen/arch/x86/acpi/cpufreq/powernow.c | 14 +++++++------- xen/include/acpi/cpufreq/processor_perf.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufreq/powernow.c index d4c7dcd5d9..8e0784b69c 100644 --- a/xen/arch/x86/acpi/cpufreq/powernow.c +++ b/xen/arch/x86/acpi/cpufreq/powernow.c @@ -32,14 +32,14 @@ #include #include -#define HW_PSTATE_MASK 0x00000007 -#define HW_PSTATE_VALID_MASK 0x80000000 -#define HW_PSTATE_MAX_MASK 0x000000f0 +#define HW_PSTATE_MASK 0x00000007U +#define HW_PSTATE_VALID_MASK 0x80000000U +#define HW_PSTATE_MAX_MASK 0x000000f0U #define HW_PSTATE_MAX_SHIFT 4 -#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */ -#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */ -#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */ -#define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* pstate current limit MSR */ +#define MSR_PSTATE_DEF_BASE 0xc0010064U /* base of Pstate MSRs */ +#define MSR_PSTATE_STATUS 0xc0010063U /* Pstate Status MSR */ +#define MSR_PSTATE_CTRL 0xc0010062U /* Pstate control MSR */ +#define MSR_PSTATE_CUR_LIMIT 0xc0010061U /* pstate current limit MSR */ #define MSR_HWCR_CPBDIS_MASK 0x02000000ULL #define ARCH_CPU_FLAG_RESUME 1 diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h index d8a1ba68a6..8b5a1b9bde 100644 --- a/xen/include/acpi/cpufreq/processor_perf.h +++ b/xen/include/acpi/cpufreq/processor_perf.h @@ -5,7 +5,7 @@ #include #include -#define XEN_PX_INIT 0x80000000 +#define XEN_PX_INIT 0x80000000U int powernow_cpufreq_init(void); unsigned int powernow_register_driver(void); From patchwork Wed Jul 12 10:32:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25177EB64DD for ; Wed, 12 Jul 2023 10:34:06 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562202.878806 (Exim 4.92) (envelope-from ) id 1qJXAN-0006X4-It; Wed, 12 Jul 2023 10:33:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562202.878806; Wed, 12 Jul 2023 10:33:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAN-0006Wt-G5; Wed, 12 Jul 2023 10:33:51 +0000 Received: by outflank-mailman (input) for mailman id 562202; Wed, 12 Jul 2023 10:33:50 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAM-00061z-GW for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:50 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 960c99eb-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:33:48 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 4B2794EE0C89; Wed, 12 Jul 2023 12:33:47 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 960c99eb-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 02/15] AMD/IOMMU: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:03 +0200 Message-Id: <662b39b70f91d3f71de929f2b79ad3cfc88f4007.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- Changes in v3: - change 'Signed-off-by' ordering Changes in v2: - minor change to commit title - change commit message --- xen/drivers/passthrough/amd/iommu-defs.h | 122 +++++++++++------------ 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/xen/drivers/passthrough/amd/iommu-defs.h b/xen/drivers/passthrough/amd/iommu-defs.h index 35de548e3a..c145248f9a 100644 --- a/xen/drivers/passthrough/amd/iommu-defs.h +++ b/xen/drivers/passthrough/amd/iommu-defs.h @@ -38,49 +38,49 @@ ((uint64_t)(offset) << (12 + (PTE_PER_TABLE_SHIFT * ((level) - 1)))) /* IOMMU Capability */ -#define PCI_CAP_ID_MASK 0x000000FF +#define PCI_CAP_ID_MASK 0x000000FFU #define PCI_CAP_ID_SHIFT 0 -#define PCI_CAP_NEXT_PTR_MASK 0x0000FF00 +#define PCI_CAP_NEXT_PTR_MASK 0x0000FF00U #define PCI_CAP_NEXT_PTR_SHIFT 8 -#define PCI_CAP_TYPE_MASK 0x00070000 +#define PCI_CAP_TYPE_MASK 0x00070000U #define PCI_CAP_TYPE_SHIFT 16 -#define PCI_CAP_REV_MASK 0x00F80000 +#define PCI_CAP_REV_MASK 0x00F80000U #define PCI_CAP_REV_SHIFT 19 -#define PCI_CAP_IOTLB_MASK 0x01000000 +#define PCI_CAP_IOTLB_MASK 0x01000000U #define PCI_CAP_IOTLB_SHIFT 24 -#define PCI_CAP_HT_TUNNEL_MASK 0x02000000 +#define PCI_CAP_HT_TUNNEL_MASK 0x02000000U #define PCI_CAP_HT_TUNNEL_SHIFT 25 -#define PCI_CAP_NP_CACHE_MASK 0x04000000 +#define PCI_CAP_NP_CACHE_MASK 0x04000000U #define PCI_CAP_NP_CACHE_SHIFT 26 #define PCI_CAP_EFRSUP_SHIFT 27 -#define PCI_CAP_RESET_MASK 0x80000000 +#define PCI_CAP_RESET_MASK 0x80000000U #define PCI_CAP_RESET_SHIFT 31 #define PCI_CAP_TYPE_IOMMU 0x3 #define PCI_CAP_MMIO_BAR_LOW_OFFSET 0x04 #define PCI_CAP_MMIO_BAR_HIGH_OFFSET 0x08 -#define PCI_CAP_MMIO_BAR_LOW_MASK 0xFFFFC000 +#define PCI_CAP_MMIO_BAR_LOW_MASK 0xFFFFC000U #define IOMMU_MMIO_REGION_LENGTH 0x4000 #define PCI_CAP_RANGE_OFFSET 0x0C -#define PCI_CAP_BUS_NUMBER_MASK 0x0000FF00 +#define PCI_CAP_BUS_NUMBER_MASK 0x0000FF00U #define PCI_CAP_BUS_NUMBER_SHIFT 8 -#define PCI_CAP_FIRST_DEVICE_MASK 0x00FF0000 +#define PCI_CAP_FIRST_DEVICE_MASK 0x00FF0000U #define PCI_CAP_FIRST_DEVICE_SHIFT 16 -#define PCI_CAP_LAST_DEVICE_MASK 0xFF000000 +#define PCI_CAP_LAST_DEVICE_MASK 0xFF000000U #define PCI_CAP_LAST_DEVICE_SHIFT 24 -#define PCI_CAP_UNIT_ID_MASK 0x0000001F +#define PCI_CAP_UNIT_ID_MASK 0x0000001FU #define PCI_CAP_UNIT_ID_SHIFT 0 #define PCI_CAP_MISC_INFO_OFFSET 0x10 -#define PCI_CAP_MSI_NUMBER_MASK 0x0000001F +#define PCI_CAP_MSI_NUMBER_MASK 0x0000001FU #define PCI_CAP_MSI_NUMBER_SHIFT 0 /* Device Table */ #define IOMMU_DEV_TABLE_BASE_LOW_OFFSET 0x00 #define IOMMU_DEV_TABLE_BASE_HIGH_OFFSET 0x04 -#define IOMMU_DEV_TABLE_SIZE_MASK 0x000001FF +#define IOMMU_DEV_TABLE_SIZE_MASK 0x000001FFU #define IOMMU_DEV_TABLE_SIZE_SHIFT 0 #define IOMMU_DEV_TABLE_ENTRIES_PER_BUS 256 @@ -159,13 +159,13 @@ struct amd_iommu_dte { #define IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET 0x0C #define IOMMU_CMD_BUFFER_HEAD_OFFSET 0x2000 #define IOMMU_CMD_BUFFER_TAIL_OFFSET 0x2008 -#define IOMMU_CMD_BUFFER_LENGTH_MASK 0x0F000000 +#define IOMMU_CMD_BUFFER_LENGTH_MASK 0x0F000000U #define IOMMU_CMD_BUFFER_LENGTH_SHIFT 24 #define IOMMU_CMD_BUFFER_ENTRY_ORDER 4 #define IOMMU_CMD_BUFFER_MAX_ENTRIES (1u << 15) -#define IOMMU_CMD_OPCODE_MASK 0xF0000000 +#define IOMMU_CMD_OPCODE_MASK 0xF0000000U #define IOMMU_CMD_OPCODE_SHIFT 28 #define IOMMU_CMD_COMPLETION_WAIT 0x1 #define IOMMU_CMD_INVALIDATE_DEVTAB_ENTRY 0x2 @@ -178,50 +178,50 @@ struct amd_iommu_dte { /* COMPLETION_WAIT command */ #define IOMMU_COMP_WAIT_DATA_BUFFER_SIZE 8 #define IOMMU_COMP_WAIT_DATA_BUFFER_ALIGNMENT 8 -#define IOMMU_COMP_WAIT_S_FLAG_MASK 0x00000001 -#define IOMMU_COMP_WAIT_I_FLAG_MASK 0x00000002 -#define IOMMU_COMP_WAIT_F_FLAG_MASK 0x00000004 -#define IOMMU_COMP_WAIT_ADDR_LOW_MASK 0xFFFFFFF8 +#define IOMMU_COMP_WAIT_S_FLAG_MASK 0x00000001U +#define IOMMU_COMP_WAIT_I_FLAG_MASK 0x00000002U +#define IOMMU_COMP_WAIT_F_FLAG_MASK 0x00000004U +#define IOMMU_COMP_WAIT_ADDR_LOW_MASK 0xFFFFFFF8U #define IOMMU_COMP_WAIT_ADDR_LOW_SHIFT 3 -#define IOMMU_COMP_WAIT_ADDR_HIGH_MASK 0x000FFFFF +#define IOMMU_COMP_WAIT_ADDR_HIGH_MASK 0x000FFFFFU #define IOMMU_COMP_WAIT_ADDR_HIGH_SHIFT 0 /* INVALIDATE_IOMMU_PAGES command */ -#define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_MASK 0x0000FFFF +#define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_MASK 0x0000FFFFU #define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_SHIFT 0 -#define IOMMU_INV_IOMMU_PAGES_S_FLAG_MASK 0x00000001 +#define IOMMU_INV_IOMMU_PAGES_S_FLAG_MASK 0x00000001U #define IOMMU_INV_IOMMU_PAGES_S_FLAG_SHIFT 0 -#define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_MASK 0x00000002 +#define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_MASK 0x00000002U #define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_SHIFT 1 -#define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_MASK 0xFFFFF000 +#define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_MASK 0xFFFFF000U #define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_SHIFT 12 -#define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_MASK 0xFFFFFFFF +#define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_MASK 0xFFFFFFFFU #define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_SHIFT 0 /* INVALIDATE_DEVTAB_ENTRY command */ -#define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_SHIFT 0 /* INVALIDATE_INTERRUPT_TABLE command */ -#define IOMMU_INV_INT_TABLE_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_INV_INT_TABLE_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_INV_INT_TABLE_DEVICE_ID_SHIFT 0 /* INVALIDATE_IOTLB_PAGES command */ -#define IOMMU_INV_IOTLB_PAGES_MAXPEND_MASK 0xff000000 +#define IOMMU_INV_IOTLB_PAGES_MAXPEND_MASK 0xff000000U #define IOMMU_INV_IOTLB_PAGES_MAXPEND_SHIFT 24 -#define IOMMU_INV_IOTLB_PAGES_PASID1_MASK 0x00ff0000 +#define IOMMU_INV_IOTLB_PAGES_PASID1_MASK 0x00ff0000U #define IOMMU_INV_IOTLB_PAGES_PASID1_SHIFT 16 -#define IOMMU_INV_IOTLB_PAGES_PASID2_MASK 0x0fff0000 +#define IOMMU_INV_IOTLB_PAGES_PASID2_MASK 0x0fff0000U #define IOMMU_INV_IOTLB_PAGES_PASID2_SHIFT 16 -#define IOMMU_INV_IOTLB_PAGES_QUEUEID_MASK 0x0000ffff +#define IOMMU_INV_IOTLB_PAGES_QUEUEID_MASK 0x0000ffffU #define IOMMU_INV_IOTLB_PAGES_QUEUEID_SHIFT 0 -#define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_SHIFT 0 -#define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_MASK 0xFFFFF000 +#define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_MASK 0xFFFFF000U #define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_SHIFT 12 -#define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_MASK 0xFFFFFFFF +#define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_MASK 0xFFFFFFFFU #define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_SHIFT 0 -#define IOMMU_INV_IOTLB_PAGES_S_FLAG_MASK 0x00000001 +#define IOMMU_INV_IOTLB_PAGES_S_FLAG_MASK 0x00000001U #define IOMMU_INV_IOTLB_PAGES_S_FLAG_SHIFT 0 /* Event Log */ @@ -229,18 +229,18 @@ struct amd_iommu_dte { #define IOMMU_EVENT_LOG_BASE_HIGH_OFFSET 0x14 #define IOMMU_EVENT_LOG_HEAD_OFFSET 0x2010 #define IOMMU_EVENT_LOG_TAIL_OFFSET 0x2018 -#define IOMMU_EVENT_LOG_LENGTH_MASK 0x0F000000 +#define IOMMU_EVENT_LOG_LENGTH_MASK 0x0F000000U #define IOMMU_EVENT_LOG_LENGTH_SHIFT 24 -#define IOMMU_EVENT_LOG_HEAD_MASK 0x0007FFF0 +#define IOMMU_EVENT_LOG_HEAD_MASK 0x0007FFF0U #define IOMMU_EVENT_LOG_HEAD_SHIFT 4 -#define IOMMU_EVENT_LOG_TAIL_MASK 0x0007FFF0 +#define IOMMU_EVENT_LOG_TAIL_MASK 0x0007FFF0U #define IOMMU_EVENT_LOG_TAIL_SHIFT 4 #define IOMMU_EVENT_LOG_ENTRY_SIZE 16 #define IOMMU_EVENT_LOG_POWER_OF2_ENTRIES_PER_PAGE 8 #define IOMMU_EVENT_LOG_U32_PER_ENTRY (IOMMU_EVENT_LOG_ENTRY_SIZE / 4) -#define IOMMU_EVENT_CODE_MASK 0xF0000000 +#define IOMMU_EVENT_CODE_MASK 0xF0000000U #define IOMMU_EVENT_CODE_SHIFT 28 #define IOMMU_EVENT_ILLEGAL_DEV_TABLE_ENTRY 0x1 #define IOMMU_EVENT_IO_PAGE_FAULT 0x2 @@ -251,12 +251,12 @@ struct amd_iommu_dte { #define IOMMU_EVENT_IOTLB_INV_TIMEOUT 0x7 #define IOMMU_EVENT_INVALID_DEV_REQUEST 0x8 -#define IOMMU_EVENT_DOMAIN_ID_MASK 0x0000FFFF +#define IOMMU_EVENT_DOMAIN_ID_MASK 0x0000FFFFU #define IOMMU_EVENT_DOMAIN_ID_SHIFT 0 -#define IOMMU_EVENT_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_EVENT_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_EVENT_DEVICE_ID_SHIFT 0 #define IOMMU_EVENT_FLAGS_SHIFT 16 -#define IOMMU_EVENT_FLAGS_MASK 0x0FFF0000 +#define IOMMU_EVENT_FLAGS_MASK 0x0FFF0000U /* PPR Log */ #define IOMMU_PPR_LOG_ENTRY_SIZE 16 @@ -265,21 +265,21 @@ struct amd_iommu_dte { #define IOMMU_PPR_LOG_BASE_LOW_OFFSET 0x0038 #define IOMMU_PPR_LOG_BASE_HIGH_OFFSET 0x003C -#define IOMMU_PPR_LOG_BASE_LOW_MASK 0xFFFFF000 +#define IOMMU_PPR_LOG_BASE_LOW_MASK 0xFFFFF000U #define IOMMU_PPR_LOG_BASE_LOW_SHIFT 12 -#define IOMMU_PPR_LOG_BASE_HIGH_MASK 0x000FFFFF +#define IOMMU_PPR_LOG_BASE_HIGH_MASK 0x000FFFFFU #define IOMMU_PPR_LOG_BASE_HIGH_SHIFT 0 -#define IOMMU_PPR_LOG_LENGTH_MASK 0x0F000000 +#define IOMMU_PPR_LOG_LENGTH_MASK 0x0F000000U #define IOMMU_PPR_LOG_LENGTH_SHIFT 24 -#define IOMMU_PPR_LOG_HEAD_MASK 0x0007FFF0 +#define IOMMU_PPR_LOG_HEAD_MASK 0x0007FFF0U #define IOMMU_PPR_LOG_HEAD_SHIFT 4 -#define IOMMU_PPR_LOG_TAIL_MASK 0x0007FFF0 +#define IOMMU_PPR_LOG_TAIL_MASK 0x0007FFF0U #define IOMMU_PPR_LOG_TAIL_SHIFT 4 #define IOMMU_PPR_LOG_HEAD_OFFSET 0x2030 #define IOMMU_PPR_LOG_TAIL_OFFSET 0x2038 -#define IOMMU_PPR_LOG_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_PPR_LOG_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_PPR_LOG_DEVICE_ID_SHIFT 0 -#define IOMMU_PPR_LOG_CODE_MASK 0xF0000000 +#define IOMMU_PPR_LOG_CODE_MASK 0xF0000000U #define IOMMU_PPR_LOG_CODE_SHIFT 28 #define IOMMU_LOG_ENTRY_TIMEOUT 1000 @@ -342,17 +342,17 @@ union amd_iommu_control { #define IOMMU_EXCLUSION_BASE_HIGH_OFFSET 0x24 #define IOMMU_EXCLUSION_LIMIT_LOW_OFFSET 0x28 #define IOMMU_EXCLUSION_LIMIT_HIGH_OFFSET 0x2C -#define IOMMU_EXCLUSION_BASE_LOW_MASK 0xFFFFF000 +#define IOMMU_EXCLUSION_BASE_LOW_MASK 0xFFFFF000U #define IOMMU_EXCLUSION_BASE_LOW_SHIFT 12 -#define IOMMU_EXCLUSION_BASE_HIGH_MASK 0xFFFFFFFF +#define IOMMU_EXCLUSION_BASE_HIGH_MASK 0xFFFFFFFFU #define IOMMU_EXCLUSION_BASE_HIGH_SHIFT 0 -#define IOMMU_EXCLUSION_RANGE_ENABLE_MASK 0x00000001 +#define IOMMU_EXCLUSION_RANGE_ENABLE_MASK 0x00000001U #define IOMMU_EXCLUSION_RANGE_ENABLE_SHIFT 0 -#define IOMMU_EXCLUSION_ALLOW_ALL_MASK 0x00000002 +#define IOMMU_EXCLUSION_ALLOW_ALL_MASK 0x00000002U #define IOMMU_EXCLUSION_ALLOW_ALL_SHIFT 1 -#define IOMMU_EXCLUSION_LIMIT_LOW_MASK 0xFFFFF000 +#define IOMMU_EXCLUSION_LIMIT_LOW_MASK 0xFFFFF000U #define IOMMU_EXCLUSION_LIMIT_LOW_SHIFT 12 -#define IOMMU_EXCLUSION_LIMIT_HIGH_MASK 0xFFFFFFFF +#define IOMMU_EXCLUSION_LIMIT_HIGH_MASK 0xFFFFFFFFU #define IOMMU_EXCLUSION_LIMIT_HIGH_SHIFT 0 /* Extended Feature Register */ @@ -476,14 +476,14 @@ union amd_iommu_pte { #define INV_IOMMU_ALL_PAGES_ADDRESS ((1ULL << 63) - 1) -#define IOMMU_RING_BUFFER_PTR_MASK 0x0007FFF0 +#define IOMMU_RING_BUFFER_PTR_MASK 0x0007FFF0U -#define IOMMU_CMD_DEVICE_ID_MASK 0x0000FFFF +#define IOMMU_CMD_DEVICE_ID_MASK 0x0000FFFFU #define IOMMU_CMD_DEVICE_ID_SHIFT 0 -#define IOMMU_REG_BASE_ADDR_LOW_MASK 0xFFFFF000 +#define IOMMU_REG_BASE_ADDR_LOW_MASK 0xFFFFF000U #define IOMMU_REG_BASE_ADDR_LOW_SHIFT 12 -#define IOMMU_REG_BASE_ADDR_HIGH_MASK 0x000FFFFF +#define IOMMU_REG_BASE_ADDR_HIGH_MASK 0x000FFFFFU #define IOMMU_REG_BASE_ADDR_HIGH_SHIFT 0 #endif /* AMD_IOMMU_DEFS_H */ From patchwork Wed Jul 12 10:32:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C534DC001E0 for ; Wed, 12 Jul 2023 10:34:07 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562203.878811 (Exim 4.92) (envelope-from ) id 1qJXAN-0006aK-Tg; Wed, 12 Jul 2023 10:33:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562203.878811; Wed, 12 Jul 2023 10:33:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAN-0006Zi-Ox; Wed, 12 Jul 2023 10:33:51 +0000 Received: by outflank-mailman (input) for mailman id 562203; Wed, 12 Jul 2023 10:33:50 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAM-0006Dd-Nu for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:50 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 96d0c3b8-209f-11ee-b239-6b7b168915f2; Wed, 12 Jul 2023 12:33:49 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 7E7F34EE0C8A; Wed, 12 Jul 2023 12:33:48 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 96d0c3b8-209f-11ee-b239-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 03/15] x86/svm: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:04 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- Changes in v3: - change 'Signed-off-by' ordering Changes in v2: - change commit title to make it unique - change commit message --- xen/arch/x86/hvm/svm/asid.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/hvm/svm/asid.c b/xen/arch/x86/hvm/svm/asid.c index 09f8c23fd9..56306d1a16 100644 --- a/xen/arch/x86/hvm/svm/asid.c +++ b/xen/arch/x86/hvm/svm/asid.c @@ -16,7 +16,7 @@ void svm_asid_init(const struct cpuinfo_x86 *c) /* Check for erratum #170, and leave ASIDs disabled if it's present. */ if ( !cpu_has_amd_erratum(c, AMD_ERRATUM_170) ) - nasids = cpuid_ebx(0x8000000A); + nasids = cpuid_ebx(0x8000000AU); hvm_asid_init(nasids); } diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 59a6e88dff..56cb2f61bb 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -269,9 +269,9 @@ svm_msrbit(unsigned long *msr_bitmap, uint32_t msr) */ if ( msr <= 0x1fff ) msr_bit = msr_bitmap + 0x0000 / BYTES_PER_LONG; - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) msr_bit = msr_bitmap + 0x0800 / BYTES_PER_LONG; - else if ( (msr >= 0xc0010000) && (msr <= 0xc0011fff) ) + else if ( (msr >= 0xc0010000U) && (msr <= 0xc0011fffU) ) msr_bit = msr_bitmap + 0x1000 / BYTES_PER_LONG; return msr_bit; @@ -2539,8 +2539,8 @@ const struct hvm_function_table * __init start_svm(void) setup_vmcb_dump(); - if ( boot_cpu_data.extended_cpuid_level >= 0x8000000a ) - svm_feature_flags = cpuid_edx(0x8000000a); + if ( boot_cpu_data.extended_cpuid_level >= 0x8000000aU ) + svm_feature_flags = cpuid_edx(0x8000000aU); printk("SVM: Supported advanced features:\n"); From patchwork Wed Jul 12 10:32:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2AD4EB64DD for ; Wed, 12 Jul 2023 10:34:11 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562204.878826 (Exim 4.92) (envelope-from ) id 1qJXAQ-00073z-3a; Wed, 12 Jul 2023 10:33:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562204.878826; Wed, 12 Jul 2023 10:33:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAQ-00073f-0M; Wed, 12 Jul 2023 10:33:54 +0000 Received: by outflank-mailman (input) for mailman id 562204; Wed, 12 Jul 2023 10:33:53 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAP-00061z-0s for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:53 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 97858c44-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:33:51 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id C76694EE0C8B; Wed, 12 Jul 2023 12:33:49 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 97858c44-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 04/15] xen/arm: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:05 +0200 Message-Id: <0e899828681c4c408ce223dcd03444a4c9039eab.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- Changes in v3: - change 'Signed-off-by' ordering - add 'ULL' instead of 'U' in 'efibind.h' and 'vgic-v3.c' - remove excessive suffixes in 'efi-boot.h' and 'smccc.h' Changes in v2: - minor change to commit title - change commit message - fix in 'domain_build.c' file for consistency - fix typo in 'gic-v2.c' file - fix in 'insn.h' file for consistency - add fixes in 'gic-v3.c', 'traps.c' and 'vgic-v3.c' --- xen/arch/arm/domain_build.c | 4 ++-- xen/arch/arm/efi/efi-boot.h | 2 +- xen/arch/arm/gic-v2.c | 6 +++--- xen/arch/arm/gic-v3.c | 10 +++++----- xen/arch/arm/include/asm/arm64/brk.h | 2 +- xen/arch/arm/include/asm/arm64/efibind.h | 10 +++++----- xen/arch/arm/include/asm/arm64/insn.h | 16 ++++++++-------- xen/arch/arm/include/asm/vreg.h | 2 +- xen/arch/arm/kernel.c | 2 +- xen/arch/arm/traps.c | 14 +++++++------- xen/arch/arm/vgic-v2.c | 2 +- xen/arch/arm/vgic-v3.c | 2 +- xen/include/public/arch-arm/smccc.h | 4 ++-- 13 files changed, 38 insertions(+), 38 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index d0d6be922d..d58604ef4a 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -3751,8 +3751,8 @@ static int __init construct_domain(struct domain *d, struct kernel_info *kinfo) * r1 = machine nr, r2 = atags or dtb pointer. *... */ - regs->r0 = 0; /* SBZ */ - regs->r1 = 0xffffffff; /* We use DTB therefore no machine id */ + regs->r0 = 0U; /* SBZ */ + regs->r1 = 0xffffffffU; /* We use DTB therefore no machine id */ regs->r2 = kinfo->dtb_paddr; } #ifdef CONFIG_ARM_64 diff --git a/xen/arch/arm/efi/efi-boot.h b/xen/arch/arm/efi/efi-boot.h index bb64925d70..3daa63a40d 100644 --- a/xen/arch/arm/efi/efi-boot.h +++ b/xen/arch/arm/efi/efi-boot.h @@ -46,7 +46,7 @@ static int get_module_file_index(const char *name, unsigned int name_len); static void PrintMessage(const CHAR16 *s); #define DEVICE_TREE_GUID \ -{0xb1b621d5, 0xf19c, 0x41a5, {0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0}} +{0xb1b621d5U, 0xf19c, 0x41a5, {0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0}} static struct file __initdata dtbfile; static void __initdata *fdt; diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 6476ff4230..cf392bfd1c 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -386,9 +386,9 @@ static void gicv2_cpu_init(void) /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so * even though they are controlled with GICD registers, they must * be set up here with the other per-cpu state. */ - writel_gicd(0xffffffff, GICD_ICACTIVER); /* Diactivate PPIs and SGIs */ - writel_gicd(0xffff0000, GICD_ICENABLER); /* Disable all PPI */ - writel_gicd(0x0000ffff, GICD_ISENABLER); /* Enable all SGI */ + writel_gicd(0xffffffffU, GICD_ICACTIVER); /* De-activate PPIs and SGIs */ + writel_gicd(0xffff0000U, GICD_ICENABLER); /* Disable all PPI */ + writel_gicd(0x0000ffffU, GICD_ISENABLER); /* Enable all SGI */ /* Set SGI priorities */ for ( i = 0; i < 16; i += 4 ) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 4e6c98bada..95e4f020fe 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -619,8 +619,8 @@ static void __init gicv3_dist_init(void) /* Disable/deactivate all global interrupts */ for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 ) { - writel_relaxed(0xffffffff, GICD + GICD_ICENABLER + (i / 32) * 4); - writel_relaxed(0xffffffff, GICD + GICD_ICACTIVER + (i / 32) * 4); + writel_relaxed(0xffffffffU, GICD + GICD_ICENABLER + (i / 32) * 4); + writel_relaxed(0xffffffffU, GICD + GICD_ICACTIVER + (i / 32) * 4); } /* @@ -832,13 +832,13 @@ static int gicv3_cpu_init(void) * The activate state is unknown at boot, so make sure all * SGIs and PPIs are de-activated. */ - writel_relaxed(0xffffffff, GICD_RDIST_SGI_BASE + GICR_ICACTIVER0); + writel_relaxed(0xffffffffU, GICD_RDIST_SGI_BASE + GICR_ICACTIVER0); /* * Disable all PPI interrupts, ensure all SGI interrupts are * enabled. */ - writel_relaxed(0xffff0000, GICD_RDIST_SGI_BASE + GICR_ICENABLER0); - writel_relaxed(0x0000ffff, GICD_RDIST_SGI_BASE + GICR_ISENABLER0); + writel_relaxed(0xffff0000U, GICD_RDIST_SGI_BASE + GICR_ICENABLER0); + writel_relaxed(0x0000ffffU, GICD_RDIST_SGI_BASE + GICR_ISENABLER0); /* Configure SGIs/PPIs as non-secure Group-1 */ writel_relaxed(GENMASK(31, 0), GICD_RDIST_SGI_BASE + GICR_IGROUPR0); diff --git a/xen/arch/arm/include/asm/arm64/brk.h b/xen/arch/arm/include/asm/arm64/brk.h index 04442c4b9f..3af153a053 100644 --- a/xen/arch/arm/include/asm/arm64/brk.h +++ b/xen/arch/arm/include/asm/arm64/brk.h @@ -21,7 +21,7 @@ * BRK instruction encoding * The #imm16 value should be placed at bits[20:5] within BRK ins */ -#define AARCH64_BREAK_MON 0xd4200000 +#define AARCH64_BREAK_MON 0xd4200000U /* * BRK instruction for provoking a fault on purpose diff --git a/xen/arch/arm/include/asm/arm64/efibind.h b/xen/arch/arm/include/asm/arm64/efibind.h index 8b43bb8495..f13eadd4f0 100644 --- a/xen/arch/arm/include/asm/arm64/efibind.h +++ b/xen/arch/arm/include/asm/arm64/efibind.h @@ -22,12 +22,12 @@ Revision History #pragma pack() #endif -#define EFIERR(a) (0x8000000000000000 | a) -#define EFI_ERROR_MASK 0x8000000000000000 -#define EFIERR_OEM(a) (0xc000000000000000 | a) +#define EFIERR(a) (0x8000000000000000ULL | a) +#define EFI_ERROR_MASK 0x8000000000000000ULL +#define EFIERR_OEM(a) (0xc000000000000000ULL | a) -#define BAD_POINTER 0xFBFBFBFBFBFBFBFB -#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFF +#define BAD_POINTER 0xFBFBFBFBFBFBFBFBULL +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL #define EFI_STUB_ERROR MAX_ADDRESS diff --git a/xen/arch/arm/include/asm/arm64/insn.h b/xen/arch/arm/include/asm/arm64/insn.h index 4e0d364d41..6308959449 100644 --- a/xen/arch/arm/include/asm/arm64/insn.h +++ b/xen/arch/arm/include/asm/arm64/insn.h @@ -60,14 +60,14 @@ static always_inline bool aarch64_insn_is_##abbr(u32 code) \ static always_inline u32 aarch64_insn_get_##abbr##_value(void) \ { return (val); } -__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) -__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) -__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) -__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000) -__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000) -__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000) -__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000) -__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) +__AARCH64_INSN_FUNCS(b, 0xFC000000U, 0x14000000U) +__AARCH64_INSN_FUNCS(bl, 0xFC000000U, 0x94000000U) +__AARCH64_INSN_FUNCS(cbz, 0x7F000000U, 0x34000000U) +__AARCH64_INSN_FUNCS(cbnz, 0x7F000000U, 0x35000000U) +__AARCH64_INSN_FUNCS(tbz, 0x7F000000U, 0x36000000U) +__AARCH64_INSN_FUNCS(tbnz, 0x7F000000U, 0x37000000U) +__AARCH64_INSN_FUNCS(bcond, 0xFF000010U, 0x54000000U) +__AARCH64_INSN_FUNCS(hint, 0xFFFFF01FU, 0xD503201FU) bool aarch64_insn_is_branch_imm(u32 insn); diff --git a/xen/arch/arm/include/asm/vreg.h b/xen/arch/arm/include/asm/vreg.h index bf945eebbd..387ce76e7e 100644 --- a/xen/arch/arm/include/asm/vreg.h +++ b/xen/arch/arm/include/asm/vreg.h @@ -56,7 +56,7 @@ static inline bool vreg_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr, if ( ret && cp64.read ) { - set_user_reg(regs, cp64.reg1, x & 0xffffffff); + set_user_reg(regs, cp64.reg1, x & 0xffffffffU); set_user_reg(regs, cp64.reg2, x >> 32); } diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index ca5318515e..508c54824d 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -39,7 +39,7 @@ struct minimal_dtb_header { /* There are other fields but we don't use them yet. */ }; -#define DTB_MAGIC 0xd00dfeed +#define DTB_MAGIC 0xd00dfeedU /** * copy_from_paddr - copy data from a physical address diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ef5c6a8195..d1ef787638 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -398,7 +398,7 @@ static vaddr_t exception_handler32(vaddr_t offset) register_t sctlr = READ_SYSREG(SCTLR_EL1); if ( sctlr & SCTLR_A32_EL1_V ) - return 0xffff0000 + offset; + return 0xffff0000U + offset; else /* always have security exceptions */ return READ_SYSREG(VBAR_EL1) + offset; } @@ -809,7 +809,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, #ifdef CONFIG_ARM_64 (uint32_t)(ctxt->far >> 32), ctxt->ifsr32_el2, - (uint32_t)(ctxt->far & 0xffffffff), + (uint32_t)(ctxt->far & 0xffffffffU), ctxt->esr_el1 #else ctxt->ifar, ctxt->ifsr, ctxt->dfar, ctxt->dfsr @@ -1414,16 +1414,16 @@ static void do_trap_hypercall(struct cpu_user_regs *regs, register_t *nr, { /* Deliberately corrupt parameter regs used by this hypercall. */ switch ( hypercall_args[*nr] ) { - case 5: HYPERCALL_ARG5(regs) = 0xDEADBEEF; - case 4: HYPERCALL_ARG4(regs) = 0xDEADBEEF; - case 3: HYPERCALL_ARG3(regs) = 0xDEADBEEF; - case 2: HYPERCALL_ARG2(regs) = 0xDEADBEEF; + case 5: HYPERCALL_ARG5(regs) = 0xDEADBEEFU; + case 4: HYPERCALL_ARG4(regs) = 0xDEADBEEFU; + case 3: HYPERCALL_ARG3(regs) = 0xDEADBEEFU; + case 2: HYPERCALL_ARG2(regs) = 0xDEADBEEFU; case 1: /* Don't clobber x0/r0 -- it's the return value */ case 0: /* -ENOSYS case */ break; default: BUG(); } - *nr = 0xDEADBEEF; + *nr = 0xDEADBEEFU; } #endif diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 0b083c33e6..35363fee09 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -306,7 +306,7 @@ static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info, case VREG32(GICD_SGIR): if ( dabt.size != DABT_WORD ) goto bad_width; /* Write only -- read unknown */ - *r = 0xdeadbeef; + *r = 0xdeadbeefU; return 1; case VRANGE32(0xF04, 0xF0C): diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 9c1fdcc3f8..1b7173da1e 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -354,7 +354,7 @@ read_reserved: return 1; read_unknown: - *r = vreg_reg64_extract(0xdeadbeafdeadbeaf, info); + *r = vreg_reg64_extract(0xdeadbeafdeadbeafULL, info); return 1; } diff --git a/xen/include/public/arch-arm/smccc.h b/xen/include/public/arch-arm/smccc.h index 802d800aad..8a9321ebed 100644 --- a/xen/include/public/arch-arm/smccc.h +++ b/xen/include/public/arch-arm/smccc.h @@ -26,7 +26,7 @@ #define XEN_SMCCC_MINOR_REVISION 1 /* Hypervisor Service UID. Randomly generated with uuidgen. */ -#define XEN_SMCCC_UID XEN_DEFINE_UUID(0xa71812dc, 0xc698, 0x4369, 0x9acf, \ +#define XEN_SMCCC_UID XEN_DEFINE_UUID(0xa71812dcU, 0xc698, 0x4369, 0x9acf, \ 0x79, 0xd1, 0x8d, 0xde, 0xe6, 0x67) /* Standard Service Service Call version. */ @@ -34,7 +34,7 @@ #define SSSC_SMCCC_MINOR_REVISION 1 /* Standard Service Call UID. Randomly generated with uuidgen. */ -#define SSSC_SMCCC_UID XEN_DEFINE_UUID(0xf863386f, 0x4b39, 0x4cbd, 0x9220,\ +#define SSSC_SMCCC_UID XEN_DEFINE_UUID(0xf863386fU, 0x4b39, 0x4cbd, 0x9220,\ 0xce, 0x16, 0x41, 0xe5, 0x9f, 0x6f) #endif /* __XEN_PUBLIC_ARCH_ARM_SMCCC_H__ */ From patchwork Wed Jul 12 10:32:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43F07C001DD for ; Wed, 12 Jul 2023 10:34:07 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562206.878838 (Exim 4.92) (envelope-from ) id 1qJXAR-0007Fm-BY; Wed, 12 Jul 2023 10:33:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562206.878838; Wed, 12 Jul 2023 10:33:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAQ-0007De-V9; Wed, 12 Jul 2023 10:33:54 +0000 Received: by outflank-mailman (input) for mailman id 562206; Wed, 12 Jul 2023 10:33:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAQ-00061z-10 for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:54 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9831a288-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:33:52 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id F0ED54EE0C8D; Wed, 12 Jul 2023 12:33:50 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9831a288-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Stefano Stabellini , Julien Grall , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin , Luca Fancellu Subject: [XEN PATCH v3 05/15] xen/device-tree: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:06 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Luca Fancellu Reviewed-by: Stefano Stabellini --- Changes in v3: - change 'Signed-off-by' ordering Changes in v2: - change commit title to the right one - change commit message - change maintainers in Cc - remove changes in 'libfdt' --- xen/common/device_tree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c index 8da1052911..0677193ab3 100644 --- a/xen/common/device_tree.c +++ b/xen/common/device_tree.c @@ -2115,7 +2115,7 @@ static void __init __unflatten_device_tree(const void *fdt, /* Allocate memory for the expanded device tree */ mem = (unsigned long)_xmalloc (size + 4, __alignof__(struct dt_device_node)); - ((__be32 *)mem)[size / 4] = cpu_to_be32(0xdeadbeef); + ((__be32 *)mem)[size / 4] = cpu_to_be32(0xdeadbeefU); dt_dprintk(" unflattening %lx...\n", mem); @@ -2125,7 +2125,7 @@ static void __init __unflatten_device_tree(const void *fdt, if ( be32_to_cpup((__be32 *)start) != FDT_END ) printk(XENLOG_WARNING "Weird tag at end of tree: %08x\n", *((u32 *)start)); - if ( be32_to_cpu(((__be32 *)mem)[size / 4]) != 0xdeadbeef ) + if ( be32_to_cpu(((__be32 *)mem)[size / 4]) != 0xdeadbeefU ) printk(XENLOG_WARNING "End of tree marker overwritten: %08x\n", be32_to_cpu(((__be32 *)mem)[size / 4])); *allnextp = NULL; From patchwork Wed Jul 12 10:32:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05AF7C001DF for ; Wed, 12 Jul 2023 10:34:08 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562205.878831 (Exim 4.92) (envelope-from ) id 1qJXAQ-0007Bn-N9; Wed, 12 Jul 2023 10:33:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562205.878831; Wed, 12 Jul 2023 10:33:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAQ-00079N-JQ; Wed, 12 Jul 2023 10:33:54 +0000 Received: by outflank-mailman (input) for mailman id 562205; Wed, 12 Jul 2023 10:33:53 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAP-0006Dd-Mr for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:53 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 98cb6af0-209f-11ee-b239-6b7b168915f2; Wed, 12 Jul 2023 12:33:53 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 16E794EE0C8F; Wed, 12 Jul 2023 12:33:52 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 98cb6af0-209f-11ee-b239-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin , Luca Fancellu Subject: [XEN PATCH v3 06/15] xen/efi: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:07 +0200 Message-Id: <4e53fc8fc5c3512a521311220375ba8542ae0e5f.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type. For the sake of uniformity, the following changes are made: - add the 'U' suffix to all first macro's arguments in 'boot.c' - add the 'U' suffix near '0x3fffffff' in 'runtime.c' Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Luca Fancellu Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- Changes in v3: - change 'Signed-off-by' ordering - change commit message - remove excessive suffixes in 'boot.c' Changes in v2: - minor change to commit title - change commit message - remove changes in 'efibind.h', 'efiapi.h', 'efidef.h' and 'efiprot.h' --- xen/common/efi/boot.c | 8 ++++---- xen/common/efi/runtime.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index c5850c26af..24169b7b50 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -34,13 +34,13 @@ #define EFI_REVISION(major, minor) (((major) << 16) | (minor)) #define SMBIOS3_TABLE_GUID \ - { 0xf2fd1544, 0x9794, 0x4a2c, {0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94} } + { 0xf2fd1544U, 0x9794, 0x4a2c, {0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94} } #define SHIM_LOCK_PROTOCOL_GUID \ - { 0x605dab50, 0xe046, 0x4300, {0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23} } + { 0x605dab50U, 0xe046, 0x4300, {0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23} } #define APPLE_PROPERTIES_PROTOCOL_GUID \ - { 0x91bd12fe, 0xf6c3, 0x44fb, { 0xa5, 0xb7, 0x51, 0x22, 0xab, 0x30, 0x3a, 0xe0} } + { 0x91bd12feU, 0xf6c3, 0x44fb, {0xa5, 0xb7, 0x51, 0x22, 0xab, 0x30, 0x3a, 0xe0} } #define EFI_SYSTEM_RESOURCE_TABLE_GUID \ - { 0xb122a263, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80} } + { 0xb122a263U, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80} } #define EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION 1 typedef struct { diff --git a/xen/common/efi/runtime.c b/xen/common/efi/runtime.c index 13b0975866..5cb7504c96 100644 --- a/xen/common/efi/runtime.c +++ b/xen/common/efi/runtime.c @@ -698,7 +698,7 @@ int efi_runtime_call(struct xenpf_efi_runtime_call *op) #ifndef COMPAT op->status = status; #else - op->status = (status & 0x3fffffff) | ((status >> 32) & 0xc0000000); + op->status = (status & 0x3fffffffU) | ((status >> 32) & 0xc0000000U); #endif return rc; From patchwork Wed Jul 12 10:32:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94DA9EB64D9 for ; Wed, 12 Jul 2023 10:34:14 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562211.878856 (Exim 4.92) (envelope-from ) id 1qJXAU-0007zf-Jy; Wed, 12 Jul 2023 10:33:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562211.878856; Wed, 12 Jul 2023 10:33:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAU-0007zI-EF; Wed, 12 Jul 2023 10:33:58 +0000 Received: by outflank-mailman (input) for mailman id 562211; Wed, 12 Jul 2023 10:33:56 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAS-00061z-F3 for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:56 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 99a1a30f-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:33:54 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 291FE4EE0C92; Wed, 12 Jul 2023 12:33:53 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 99a1a30f-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 07/15] x86/vmx: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:08 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type. For the sake of uniformity, the following changes are made: - add the 'U' suffix to macros near 'CPU_BASED_ACTIVATE_SECONDARY_CONTROLS' and 'SECONDARY_EXEC_NOTIFY_VM_EXITING' macros in 'vmcs.h' - add the 'U' suffix to macros near 'INTR_INFO_VALID_MASK' macro in 'vmx.h' Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini Reviewed-by: Jan Beulich Reviewed-by: Stefano Stabellini --- Changes in v3: - change 'Signed-off-by' ordering - change commit message - remove unnecessary changes in 'vvmx.c' - add 'uint32_t' casts in 'vvmx.c' - add missing 'U' in 'vmcs.h' macros - change macro to '(1u << 31)' in 'vmx.h' - remove unnecessary changes to 'vmx.h' Changes in v2: - minor change to commit title - change commit message - remove unnecessary changes in 'vpmu_intel.c' and 'vmx.h' - add 'ULL' suffix in 'vpmu_intel.c' - add zero-padding to constants in 'vmx.h' - add missing 'U' in 'vmx.h' --- xen/arch/x86/cpu/vpmu_intel.c | 2 +- xen/arch/x86/hvm/vmx/vmcs.c | 6 +- xen/arch/x86/hvm/vmx/vvmx.c | 8 +-- xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 84 ++++++++++++------------- xen/arch/x86/include/asm/hvm/vmx/vmx.h | 16 ++--- 5 files changed, 58 insertions(+), 58 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index fa5b40c65c..6330c89b47 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -945,7 +945,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1); global_ctrl_mask = ~((((1ULL << fixed_pmc_cnt) - 1) << 32) | ((1ULL << arch_pmc_cnt) - 1)); - global_ovf_ctrl_mask = ~(0xC000000000000000 | + global_ovf_ctrl_mask = ~(0xC000000000000000ULL | (((1ULL << fixed_pmc_cnt) - 1) << 32) | ((1ULL << arch_pmc_cnt) - 1)); if ( version > 2 ) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index b209563625..d5a2b847a9 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -911,7 +911,7 @@ void vmx_clear_msr_intercept(struct vcpu *v, unsigned int msr, if ( type & VMX_MSR_W ) clear_bit(msr, msr_bitmap->write_low); } - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) { msr &= 0x1fff; if ( type & VMX_MSR_R ) @@ -939,7 +939,7 @@ void vmx_set_msr_intercept(struct vcpu *v, unsigned int msr, if ( type & VMX_MSR_W ) set_bit(msr, msr_bitmap->write_low); } - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) { msr &= 0x1fff; if ( type & VMX_MSR_R ) @@ -957,7 +957,7 @@ bool vmx_msr_is_intercepted(struct vmx_msr_bitmap *msr_bitmap, if ( msr <= 0x1fff ) return test_bit(msr, is_write ? msr_bitmap->write_low : msr_bitmap->read_low); - else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) ) + else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) ) return test_bit(msr & 0x1fff, is_write ? msr_bitmap->write_high : msr_bitmap->read_high); else diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 16b0ef82b6..b7be424afb 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -263,7 +263,7 @@ uint64_t get_vvmcs_virtual(void *vvmcs, uint32_t vmcs_encoding) res >>= 32; break; case VVMCS_WIDTH_32: - res &= 0xffffffff; + res = (uint32_t)res; break; case VVMCS_WIDTH_NATURAL: default: @@ -315,14 +315,14 @@ void set_vvmcs_virtual(void *vvmcs, uint32_t vmcs_encoding, uint64_t val) case VVMCS_WIDTH_64: if ( enc.access_type ) { - res &= 0xffffffff; + res = (uint32_t)res; res |= val << 32; } else res = val; break; case VVMCS_WIDTH_32: - res = val & 0xffffffff; + res = (uint32_t)val; break; case VVMCS_WIDTH_NATURAL: default: @@ -2306,7 +2306,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) break; case MSR_IA32_VMX_CR0_FIXED1: /* allow 0-settings for all bits */ - data = 0xffffffff; + data = 0xffffffffU; break; case MSR_IA32_VMX_CR4_FIXED0: /* VMXE bit must be 1 in VMX operation */ diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h index d07fcb2bc9..e056643993 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -187,27 +187,27 @@ bool_t __must_check vmx_vmcs_try_enter(struct vcpu *v); void vmx_vmcs_exit(struct vcpu *v); void vmx_vmcs_reload(struct vcpu *v); -#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 -#define CPU_BASED_USE_TSC_OFFSETING 0x00000008 -#define CPU_BASED_HLT_EXITING 0x00000080 -#define CPU_BASED_INVLPG_EXITING 0x00000200 -#define CPU_BASED_MWAIT_EXITING 0x00000400 -#define CPU_BASED_RDPMC_EXITING 0x00000800 -#define CPU_BASED_RDTSC_EXITING 0x00001000 -#define CPU_BASED_CR3_LOAD_EXITING 0x00008000 -#define CPU_BASED_CR3_STORE_EXITING 0x00010000 -#define CPU_BASED_CR8_LOAD_EXITING 0x00080000 -#define CPU_BASED_CR8_STORE_EXITING 0x00100000 -#define CPU_BASED_TPR_SHADOW 0x00200000 -#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 -#define CPU_BASED_MOV_DR_EXITING 0x00800000 -#define CPU_BASED_UNCOND_IO_EXITING 0x01000000 -#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000 -#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 -#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000 -#define CPU_BASED_MONITOR_EXITING 0x20000000 -#define CPU_BASED_PAUSE_EXITING 0x40000000 -#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 +#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004U +#define CPU_BASED_USE_TSC_OFFSETING 0x00000008U +#define CPU_BASED_HLT_EXITING 0x00000080U +#define CPU_BASED_INVLPG_EXITING 0x00000200U +#define CPU_BASED_MWAIT_EXITING 0x00000400U +#define CPU_BASED_RDPMC_EXITING 0x00000800U +#define CPU_BASED_RDTSC_EXITING 0x00001000U +#define CPU_BASED_CR3_LOAD_EXITING 0x00008000U +#define CPU_BASED_CR3_STORE_EXITING 0x00010000U +#define CPU_BASED_CR8_LOAD_EXITING 0x00080000U +#define CPU_BASED_CR8_STORE_EXITING 0x00100000U +#define CPU_BASED_TPR_SHADOW 0x00200000U +#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000U +#define CPU_BASED_MOV_DR_EXITING 0x00800000U +#define CPU_BASED_UNCOND_IO_EXITING 0x01000000U +#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000U +#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000U +#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000U +#define CPU_BASED_MONITOR_EXITING 0x20000000U +#define CPU_BASED_PAUSE_EXITING 0x40000000U +#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000U extern u32 vmx_cpu_based_exec_control; #define PIN_BASED_EXT_INTR_MASK 0x00000001 @@ -238,26 +238,26 @@ extern u32 vmx_vmexit_control; #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 extern u32 vmx_vmentry_control; -#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 -#define SECONDARY_EXEC_ENABLE_EPT 0x00000002 -#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004 -#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008 -#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 -#define SECONDARY_EXEC_ENABLE_VPID 0x00000020 -#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 -#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 -#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 -#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 -#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 -#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 -#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000 -#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000 -#define SECONDARY_EXEC_ENABLE_PML 0x00020000 -#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 -#define SECONDARY_EXEC_XSAVES 0x00100000 -#define SECONDARY_EXEC_TSC_SCALING 0x02000000 -#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000 -#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000 +#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001U +#define SECONDARY_EXEC_ENABLE_EPT 0x00000002U +#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004U +#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008U +#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010U +#define SECONDARY_EXEC_ENABLE_VPID 0x00000020U +#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040U +#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080U +#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100U +#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200U +#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400U +#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000U +#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000U +#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000U +#define SECONDARY_EXEC_ENABLE_PML 0x00020000U +#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000U +#define SECONDARY_EXEC_XSAVES 0x00100000U +#define SECONDARY_EXEC_TSC_SCALING 0x02000000U +#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000U +#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000U extern u32 vmx_secondary_exec_control; #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 @@ -346,7 +346,7 @@ extern u64 vmx_ept_vpid_cap; #define cpu_has_vmx_notify_vm_exiting \ (vmx_secondary_exec_control & SECONDARY_EXEC_NOTIFY_VM_EXITING) -#define VMCS_RID_TYPE_MASK 0x80000000 +#define VMCS_RID_TYPE_MASK 0x80000000U /* GUEST_INTERRUPTIBILITY_INFO flags. */ #define VMX_INTR_SHADOW_STI 0x00000001 diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h index c84acc221d..d4b335a2bc 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -137,7 +137,7 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) /* * Exit Reasons */ -#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000 +#define VMX_EXIT_REASONS_FAILED_VMENTRY (1u << 31) #define VMX_EXIT_REASONS_BUS_LOCK (1u << 26) #define EXIT_REASON_EXCEPTION_NMI 0 @@ -209,12 +209,12 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) * Note INTR_INFO_NMI_UNBLOCKED_BY_IRET is also used with Exit Qualification * field for EPT violations, PML full and SPP-related event vmexits. */ -#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ -#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ -#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ -#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */ -#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ -#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 +#define INTR_INFO_VECTOR_MASK 0x000000ffU /* 7:0 */ +#define INTR_INFO_INTR_TYPE_MASK 0x00000700U /* 10:8 */ +#define INTR_INFO_DELIVER_CODE_MASK 0x00000800U /* 11 */ +#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x00001000U /* 12 */ +#define INTR_INFO_VALID_MASK 0x80000000U /* 31 */ +#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000U /* * Exit Qualifications for NOTIFY VM EXIT @@ -607,7 +607,7 @@ static inline void vmx_pi_hooks_assign(struct domain *d) {} static inline void vmx_pi_hooks_deassign(struct domain *d) {} #endif -#define APIC_INVALID_DEST 0xffffffff +#define APIC_INVALID_DEST 0xffffffffU /* EPT violation qualifications definitions */ typedef union ept_qual { From patchwork Wed Jul 12 10:32:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB4B2EB64D9 for ; Wed, 12 Jul 2023 10:34:07 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562212.878861 (Exim 4.92) (envelope-from ) id 1qJXAV-00084M-B2; Wed, 12 Jul 2023 10:33:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562212.878861; Wed, 12 Jul 2023 10:33:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAU-000837-Rb; Wed, 12 Jul 2023 10:33:58 +0000 Received: by outflank-mailman (input) for mailman id 562212; Wed, 12 Jul 2023 10:33:56 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAS-0006Dd-NG for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:56 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9a50ef10-209f-11ee-b239-6b7b168915f2; Wed, 12 Jul 2023 12:33:55 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 7E3AD4EE0C88; Wed, 12 Jul 2023 12:33:54 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9a50ef10-209f-11ee-b239-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Paul Durrant , =?utf-8?q?Rog?= =?utf-8?q?er_Pau_Monn=C3=A9?= , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 08/15] xen/pci: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:09 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- Changes in v3: - change 'Signed-off-by' ordering Changes in v2: - minor change to commit title - change commit message --- xen/drivers/passthrough/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 07d1986d33..95846e84f2 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -990,8 +990,8 @@ bool_t __init pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func) vendor = pci_conf_read32(PCI_SBDF(seg, bus, dev, func), PCI_VENDOR_ID); /* some broken boards return 0 or ~0 if a slot is empty: */ - if ( (vendor == 0xffffffff) || (vendor == 0x00000000) || - (vendor == 0x0000ffff) || (vendor == 0xffff0000) ) + if ( (vendor == 0xffffffffU) || (vendor == 0x00000000U) || + (vendor == 0x0000ffffU) || (vendor == 0xffff0000U) ) return 0; return 1; } From patchwork Wed Jul 12 10:32:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98188C001B0 for ; Wed, 12 Jul 2023 10:34:14 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562213.878867 (Exim 4.92) (envelope-from ) id 1qJXAV-0008Cq-VW; Wed, 12 Jul 2023 10:33:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562213.878867; Wed, 12 Jul 2023 10:33:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAV-00087p-G8; Wed, 12 Jul 2023 10:33:59 +0000 Received: by outflank-mailman (input) for mailman id 562213; Wed, 12 Jul 2023 10:33:57 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAT-0006Dd-NS for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:57 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9af0ad29-209f-11ee-b239-6b7b168915f2; Wed, 12 Jul 2023 12:33:56 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id AF8ED4EE0C8B; Wed, 12 Jul 2023 12:33:55 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9af0ad29-209f-11ee-b239-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Juergen Gross , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 09/15] xen/public: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:10 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type. For the sake of uniformity, the following changes are made: - add the 'U' suffix to integer constants before the '?' operator Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Juergen Gross Reviewed-by: Stefano Stabellini --- Changes in v3: - change 'Signed-off-by' ordering - change commit message Changes in v2: - minor change to commit title - change commit message - correct macros code style --- xen/include/public/io/ring.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/include/public/io/ring.h b/xen/include/public/io/ring.h index 025939278b..0cae4367be 100644 --- a/xen/include/public/io/ring.h +++ b/xen/include/public/io/ring.h @@ -36,11 +36,11 @@ typedef unsigned int RING_IDX; /* Round a 32-bit unsigned constant down to the nearest power of two. */ -#define __RD2(_x) (((_x) & 0x00000002) ? 0x2 : ((_x) & 0x1)) -#define __RD4(_x) (((_x) & 0x0000000c) ? __RD2((_x)>>2)<<2 : __RD2(_x)) -#define __RD8(_x) (((_x) & 0x000000f0) ? __RD4((_x)>>4)<<4 : __RD4(_x)) -#define __RD16(_x) (((_x) & 0x0000ff00) ? __RD8((_x)>>8)<<8 : __RD8(_x)) -#define __RD32(_x) (((_x) & 0xffff0000) ? __RD16((_x)>>16)<<16 : __RD16(_x)) +#define __RD2(x) (((x) & 0x00000002U) ? 0x2 : ((x) & 0x1)) +#define __RD4(x) (((x) & 0x0000000cU) ? __RD2((x) >> 2) << 2 : __RD2(x)) +#define __RD8(x) (((x) & 0x000000f0U) ? __RD4((x) >> 4) << 4 : __RD4(x)) +#define __RD16(x) (((x) & 0x0000ff00U) ? __RD8((x) >> 8) << 8 : __RD8(x)) +#define __RD32(x) (((x) & 0xffff0000U) ? __RD16((x) >> 16) << 16 : __RD16(x)) /* * Calculate size of a shared ring, given the total available space for the From patchwork Wed Jul 12 10:32:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4E5CEB64DD for ; Wed, 12 Jul 2023 10:34:14 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562218.878881 (Exim 4.92) (envelope-from ) id 1qJXAX-0000Gd-Ru; Wed, 12 Jul 2023 10:34:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562218.878881; Wed, 12 Jul 2023 10:34:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAX-0000Er-In; Wed, 12 Jul 2023 10:34:01 +0000 Received: by outflank-mailman (input) for mailman id 562218; Wed, 12 Jul 2023 10:34:00 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAV-00061z-Rk for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:33:59 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9bdd7fe3-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:33:58 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id C1E9A4EE0C87; Wed, 12 Jul 2023 12:33:56 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9bdd7fe3-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 10/15] x86/monitor: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:11 +0200 Message-Id: <13ba23be1b7aba72bbae2cdec781eba9d7d4abd3.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- Changes in v3: - change 'Signed-off-by' ordering Changes in v2: - change commit title to make it unique - change commit message --- xen/arch/x86/monitor.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/monitor.c b/xen/arch/x86/monitor.c index d4857faf8a..dc336c239a 100644 --- a/xen/arch/x86/monitor.c +++ b/xen/arch/x86/monitor.c @@ -48,17 +48,17 @@ static unsigned long *monitor_bitmap_for_msr(const struct domain *d, u32 *msr) switch ( *msr ) { - case 0 ... 0x1fff: + case 0 ... 0x1fffU: BUILD_BUG_ON(sizeof(d->arch.monitor.msr_bitmap->low) * 8 <= 0x1fff); return d->arch.monitor.msr_bitmap->low; - case 0x40000000 ... 0x40001fff: + case 0x40000000U ... 0x40001fffU: BUILD_BUG_ON( sizeof(d->arch.monitor.msr_bitmap->hypervisor) * 8 <= 0x1fff); *msr &= 0x1fff; return d->arch.monitor.msr_bitmap->hypervisor; - case 0xc0000000 ... 0xc0001fff: + case 0xc0000000U ... 0xc0001fffU: BUILD_BUG_ON(sizeof(d->arch.monitor.msr_bitmap->high) * 8 <= 0x1fff); *msr &= 0x1fff; return d->arch.monitor.msr_bitmap->high; From patchwork Wed Jul 12 10:32:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20B44EB64DD for ; Wed, 12 Jul 2023 10:37:40 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562282.878936 (Exim 4.92) (envelope-from ) id 1qJXDr-00050S-Qm; Wed, 12 Jul 2023 10:37:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562282.878936; Wed, 12 Jul 2023 10:37:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXDr-00050E-Mq; Wed, 12 Jul 2023 10:37:27 +0000 Received: by outflank-mailman (input) for mailman id 562282; Wed, 12 Jul 2023 10:37:26 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAW-00061z-SE for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:34:00 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9c701b74-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:33:59 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 4138E4EE0C8D; Wed, 12 Jul 2023 12:33:58 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9c701b74-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 11/15] xen/vpci: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:12 +0200 Message-Id: <83741ce06872850e1e3126c1cab056ebc12b97ea.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- Changes in v3: - change 'Signed-off-by' ordering - add 'uint32_t' casts in 'msi.c' and 'msix.c' Changes in v2: - minor change to commit title - change commit message --- xen/drivers/vpci/msi.c | 2 +- xen/drivers/vpci/msix.c | 2 +- xen/drivers/vpci/vpci.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 8f2b59e61a..bf5fe2f981 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -124,7 +124,7 @@ static void cf_check address_hi_write( struct vpci_msi *msi = data; /* Clear and update high part. */ - msi->address &= 0xffffffff; + msi->address = (uint32_t)msi->address; msi->address |= (uint64_t)val << 32; update_msi(pdev, msi); diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 25bde77586..2090168f42 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -531,7 +531,7 @@ static int cf_check msix_write( case PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET: entry->updated = true; - entry->addr &= 0xffffffff; + entry->addr = (uint32_t)entry->addr; entry->addr |= (uint64_t)data << 32; break; diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index d73fa76302..3bec9a4153 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -319,7 +319,7 @@ static void vpci_write_hw(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, static uint32_t merge_result(uint32_t data, uint32_t new, unsigned int size, unsigned int offset) { - uint32_t mask = 0xffffffff >> (32 - 8 * size); + uint32_t mask = 0xffffffffU >> (32 - 8 * size); return (data & ~(mask << (offset * 8))) | ((new & mask) << (offset * 8)); } @@ -402,7 +402,7 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size) data = merge_result(data, tmp_data, size - data_offset, data_offset); } - return data & (0xffffffff >> (32 - 8 * size)); + return data & (0xffffffffU >> (32 - 8 * size)); } /* @@ -427,7 +427,7 @@ static void vpci_write_helper(const struct pci_dev *pdev, data = merge_result(val, data, size, offset); } - r->write(pdev, r->offset, data & (0xffffffff >> (32 - 8 * r->size)), + r->write(pdev, r->offset, data & (0xffffffffU >> (32 - 8 * r->size)), r->private); } From patchwork Wed Jul 12 10:32:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA872EB64DA for ; Wed, 12 Jul 2023 10:37:37 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562261.878919 (Exim 4.92) (envelope-from ) id 1qJXDo-0004Mh-Dy; Wed, 12 Jul 2023 10:37:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562261.878919; Wed, 12 Jul 2023 10:37:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXDo-0004L0-5V; Wed, 12 Jul 2023 10:37:24 +0000 Received: by outflank-mailman (input) for mailman id 562261; Wed, 12 Jul 2023 10:37:22 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAY-0006Dd-Oc for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:34:02 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9d4106b1-209f-11ee-b239-6b7b168915f2; Wed, 12 Jul 2023 12:34:00 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 413254EE0C89; Wed, 12 Jul 2023 12:33:59 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9d4106b1-209f-11ee-b239-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 12/15] xen/x86: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:13 +0200 Message-Id: <78717a3ccee0517eab915156fc474394ae1dcf81.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type. For the sake of uniformity, the following changes are made: - add the 'U' suffix to all first macro's arguments in 'mce-apei.c' - add the 'U' suffix to switch cases in 'cpuid.c' - add 'U' suffixes to 'mask16' in 'stdvga.c' - add the 'U' suffix to macros in 'pci.h' Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- Changes in v3: - change 'Signed-off-by' ordering - change commit message - add 'UL' in 'extable.c' - fix indentation in 'cpu-policy.c' - remove excessive suffixes in 'mce-apei.c' - add 'UL' in 'x86-defns.h' - remove changes to 'sr_mask' and 'gr_mask' in 'stdvga.c' - move 'viridian.c' and 'hyperv-tlfs.h' in a separate commit Changes in v2: - minor change to commit title - change commit message - remove comments from 'gr_mask' in 'stdvga.c' - correct code style in 'trace.h' - add fix in 'extable.c' - remove changes in 'x86-defns.h', 'msr-index.h' and 'xen-x86_64.h' --- xen/arch/x86/apic.c | 2 +- xen/arch/x86/cpu-policy.c | 18 +-- xen/arch/x86/cpu/mcheck/mce-apei.c | 4 +- xen/arch/x86/cpuid.c | 8 +- xen/arch/x86/efi/efi-boot.h | 6 +- xen/arch/x86/extable.c | 2 +- xen/arch/x86/hvm/hypercall.c | 2 +- xen/arch/x86/hvm/irq.c | 2 +- xen/arch/x86/hvm/pmtimer.c | 4 +- xen/arch/x86/hvm/stdvga.c | 50 +++--- xen/arch/x86/hvm/vlapic.c | 6 +- xen/arch/x86/include/asm/apicdef.h | 2 +- xen/arch/x86/include/asm/config.h | 2 +- xen/arch/x86/include/asm/hpet.h | 2 +- xen/arch/x86/include/asm/hvm/trace.h | 4 +- xen/arch/x86/include/asm/hvm/vioapic.h | 2 +- xen/arch/x86/include/asm/msi.h | 2 +- xen/arch/x86/include/asm/msr-index.h | 202 ++++++++++++------------- xen/arch/x86/include/asm/pci.h | 8 +- xen/arch/x86/include/asm/x86-defns.h | 2 +- xen/arch/x86/percpu.c | 2 +- xen/arch/x86/psr.c | 2 +- xen/arch/x86/spec_ctrl.c | 8 +- xen/arch/x86/x86_64/acpi_mmcfg.c | 2 +- xen/arch/x86/x86_64/pci.c | 2 +- xen/arch/x86/x86_emulate/x86_emulate.h | 2 +- xen/lib/x86/cpuid.c | 8 +- xen/lib/x86/policy.c | 2 +- 28 files changed, 179 insertions(+), 179 deletions(-) diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index f71474d47d..03c5c0f2ee 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1211,7 +1211,7 @@ static void __init calibrate_APIC_clock(void) * Setup the APIC counter to maximum. There is no way the lapic * can underflow in the 100ms detection time frame. */ - __setup_APIC_LVTT(0xffffffff); + __setup_APIC_LVTT(0xffffffffU); bus_freq = calibrate_apic_timer(); if ( !bus_freq ) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index f40eeb8be8..5977e21a07 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -321,7 +321,7 @@ static void recalculate_misc(struct cpu_policy *p) p->extd.vendor_edx = p->basic.vendor_edx; p->extd.raw_fms = p->basic.raw_fms; - p->extd.raw[0x1].b &= 0xff00ffff; + p->extd.raw[0x1].b &= 0xff00ffffU; p->extd.e1d |= p->basic._1d & CPUID_COMMON_1D_FEATURES; p->extd.raw[0x8].a &= 0x0000ffff; /* GuestMaxPhysAddr hidden. */ @@ -378,10 +378,10 @@ static void __init calculate_host_policy(void) * this information. */ if ( cpu_has_lfence_dispatch ) - max_extd_leaf = max(max_extd_leaf, 0x80000021); + max_extd_leaf = max(max_extd_leaf, 0x80000021U); - p->extd.max_leaf = 0x80000000 | min_t(uint32_t, max_extd_leaf & 0xffff, - ARRAY_SIZE(p->extd.raw) - 1); + p->extd.max_leaf = 0x80000000U | min_t(uint32_t, max_extd_leaf & 0xffffU, + ARRAY_SIZE(p->extd.raw) - 1); x86_cpu_featureset_to_policy(boot_cpu_data.x86_capability, p); recalculate_xstate(p); @@ -768,11 +768,11 @@ void recalculate_cpuid_policy(struct domain *d) p->basic.max_leaf = min(p->basic.max_leaf, max->basic.max_leaf); p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf); - p->extd.max_leaf = 0x80000000 | min(p->extd.max_leaf & 0xffff, - ((p->x86_vendor & (X86_VENDOR_AMD | - X86_VENDOR_HYGON)) - ? CPUID_GUEST_NR_EXTD_AMD - : CPUID_GUEST_NR_EXTD_INTEL) - 1); + p->extd.max_leaf = 0x80000000U | min(p->extd.max_leaf & 0xffff, + ((p->x86_vendor & (X86_VENDOR_AMD | + X86_VENDOR_HYGON)) + ? CPUID_GUEST_NR_EXTD_AMD + : CPUID_GUEST_NR_EXTD_INTEL) - 1); x86_cpu_policy_to_featureset(p, fs); x86_cpu_policy_to_featureset(max, max_fs); diff --git a/xen/arch/x86/cpu/mcheck/mce-apei.c b/xen/arch/x86/cpu/mcheck/mce-apei.c index 53b6735896..b895020882 100644 --- a/xen/arch/x86/cpu/mcheck/mce-apei.c +++ b/xen/arch/x86/cpu/mcheck/mce-apei.c @@ -37,10 +37,10 @@ #include "mce.h" #define CPER_CREATOR_MCE \ - UUID_LE(0x75a574e3, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c, \ + UUID_LE(0x75a574e3U, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c, \ 0x64, 0x90, 0xb8, 0x9d) #define CPER_SECTION_TYPE_MCE \ - UUID_LE(0xfe08ffbe, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96, \ + UUID_LE(0xfe08ffbeU, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96, \ 0x04, 0x4a, 0x38, 0xfc) /* diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 455a09b2dd..7290a979c6 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -93,7 +93,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, } break; - case 0x40000000 ... 0x400000ff: + case 0x40000000U ... 0x400000ffU: if ( is_viridian_domain(d) ) return cpuid_viridian_leaves(v, leaf, subleaf, res); @@ -103,10 +103,10 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, * Intel reserve up until 0x4fffffff for hypervisor use. AMD reserve * only until 0x400000ff, but we already use double that. */ - case 0x40000100 ... 0x400001ff: + case 0x40000100U ... 0x400001ffU: return cpuid_hypervisor_leaves(v, leaf, subleaf, res); - case 0x80000000 ... 0x80000000 + CPUID_GUEST_NR_EXTD - 1: + case 0x80000000U ... 0x80000000U + CPUID_GUEST_NR_EXTD - 1: ASSERT((p->extd.max_leaf & 0xffff) < ARRAY_SIZE(p->extd.raw)); if ( (leaf & 0xffff) > min_t(uint32_t, p->extd.max_leaf & 0xffff, ARRAY_SIZE(p->extd.raw) - 1) ) @@ -352,7 +352,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, } break; - case 0x80000001: + case 0x80000001U: /* SYSCALL is hidden outside of long mode on Intel. */ if ( p->x86_vendor == X86_VENDOR_INTEL && is_hvm_domain(d) && !hvm_long_mode_active(v) ) diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h index 92f4cfe8bd..eebc54180b 100644 --- a/xen/arch/x86/efi/efi-boot.h +++ b/xen/arch/x86/efi/efi-boot.h @@ -740,16 +740,16 @@ static void __init efi_arch_handle_module(const struct file *file, static void __init efi_arch_cpu(void) { - uint32_t eax = cpuid_eax(0x80000000); + uint32_t eax = cpuid_eax(0x80000000U); uint32_t *caps = boot_cpu_data.x86_capability; boot_tsc_stamp = rdtsc(); caps[FEATURESET_1c] = cpuid_ecx(1); - if ( (eax >> 16) == 0x8000 && eax > 0x80000000 ) + if ( (eax >> 16) == 0x8000 && eax > 0x80000000U ) { - caps[FEATURESET_e1d] = cpuid_edx(0x80000001); + caps[FEATURESET_e1d] = cpuid_edx(0x80000001U); /* * This check purposefully doesn't use cpu_has_nx because diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c index c3771c2e39..0e8694c188 100644 --- a/xen/arch/x86/extable.c +++ b/xen/arch/x86/extable.c @@ -141,7 +141,7 @@ static int __init cf_check stub_selftest(void) .rax = 0x0123456789abcdef, .res.fields.trapnr = X86_EXC_GP }, { .opc = { endbr64, 0x02, 0x04, 0x04, 0xc3 }, /* add (%rsp,%rax),%al */ - .rax = 0xfedcba9876543210, + .rax = 0xfedcba9876543210UL, .res.fields.trapnr = X86_EXC_SS }, { .opc = { endbr64, 0xcc, 0xc3, 0xc3, 0xc3 }, /* int3 */ .res.fields.trapnr = X86_EXC_BP }, diff --git a/xen/arch/x86/hvm/hypercall.c b/xen/arch/x86/hvm/hypercall.c index 20d266ffd5..eeb73e1aa5 100644 --- a/xen/arch/x86/hvm/hypercall.c +++ b/xen/arch/x86/hvm/hypercall.c @@ -129,7 +129,7 @@ int hvm_hypercall(struct cpu_user_regs *regs) break; } - if ( (eax & 0x80000000) && is_viridian_domain(currd) ) + if ( (eax & 0x80000000U) && is_viridian_domain(currd) ) { int ret; diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c index 1258371eb0..5c00127cfc 100644 --- a/xen/arch/x86/hvm/irq.c +++ b/xen/arch/x86/hvm/irq.c @@ -383,7 +383,7 @@ int hvm_inject_msi(struct domain *d, uint64_t addr, uint32_t data) if ( !vector ) { - int pirq = ((addr >> 32) & 0xffffff00) | dest; + int pirq = ((addr >> 32) & 0xffffff00U) | dest; if ( pirq > 0 ) { diff --git a/xen/arch/x86/hvm/pmtimer.c b/xen/arch/x86/hvm/pmtimer.c index 2145c531b6..eb4a455763 100644 --- a/xen/arch/x86/hvm/pmtimer.c +++ b/xen/arch/x86/hvm/pmtimer.c @@ -40,8 +40,8 @@ #define SCI_IRQ 9 /* We provide a 32-bit counter (must match the TMR_VAL_EXT bit in the FADT) */ -#define TMR_VAL_MASK (0xffffffff) -#define TMR_VAL_MSB (0x80000000) +#define TMR_VAL_MASK (0xffffffffU) +#define TMR_VAL_MSB (0x80000000U) /* Dispatch SCIs based on the PM1a_STS and PM1a_EN registers */ static void pmt_update_sci(PMTState *s) diff --git a/xen/arch/x86/hvm/stdvga.c b/xen/arch/x86/hvm/stdvga.c index 798a9a0549..d3dfb9b689 100644 --- a/xen/arch/x86/hvm/stdvga.c +++ b/xen/arch/x86/hvm/stdvga.c @@ -39,22 +39,22 @@ #define PAT(x) (x) static const uint32_t mask16[16] = { - PAT(0x00000000), - PAT(0x000000ff), - PAT(0x0000ff00), - PAT(0x0000ffff), - PAT(0x00ff0000), - PAT(0x00ff00ff), - PAT(0x00ffff00), - PAT(0x00ffffff), - PAT(0xff000000), - PAT(0xff0000ff), - PAT(0xff00ff00), - PAT(0xff00ffff), - PAT(0xffff0000), - PAT(0xffff00ff), - PAT(0xffffff00), - PAT(0xffffffff), + PAT(0x00000000U), + PAT(0x000000ffU), + PAT(0x0000ff00U), + PAT(0x0000ffffU), + PAT(0x00ff0000U), + PAT(0x00ff00ffU), + PAT(0x00ffff00U), + PAT(0x00ffffffU), + PAT(0xff000000U), + PAT(0xff0000ffU), + PAT(0xff00ff00U), + PAT(0xff00ffffU), + PAT(0xffff0000U), + PAT(0xffff00ffU), + PAT(0xffffff00U), + PAT(0xffffffffU), }; /* force some bits to zero */ @@ -70,15 +70,15 @@ static const uint8_t sr_mask[8] = { }; static const uint8_t gr_mask[9] = { - (uint8_t)~0xf0, /* 0x00 */ - (uint8_t)~0xf0, /* 0x01 */ - (uint8_t)~0xf0, /* 0x02 */ - (uint8_t)~0xe0, /* 0x03 */ - (uint8_t)~0xfc, /* 0x04 */ - (uint8_t)~0x84, /* 0x05 */ - (uint8_t)~0xf0, /* 0x06 */ - (uint8_t)~0xf0, /* 0x07 */ - (uint8_t)~0x00, /* 0x08 */ + (uint8_t)~0xf0, + (uint8_t)~0xf0, + (uint8_t)~0xf0, + (uint8_t)~0xe0, + (uint8_t)~0xfc, + (uint8_t)~0x84, + (uint8_t)~0xf0, + (uint8_t)~0xf0, + (uint8_t)~0x00, }; static uint8_t *vram_getb(struct hvm_hw_stdvga *s, unsigned int a) diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index c7ce82d064..a8e87c4446 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -237,7 +237,7 @@ bool_t vlapic_match_dest( case APIC_DEST_NOSHORT: if ( dest_mode ) return vlapic_match_logical_addr(target, dest); - return (dest == _VLAPIC_ID(target, 0xffffffff)) || + return (dest == _VLAPIC_ID(target, 0xffffffffU)) || (dest == VLAPIC_ID(target)); case APIC_DEST_SELF: @@ -467,7 +467,7 @@ static bool_t is_multicast_dest(struct vlapic *vlapic, unsigned int short_hand, return short_hand != APIC_DEST_SELF; if ( vlapic_x2apic_mode(vlapic) ) - return dest_mode ? hweight16(dest) > 1 : dest == 0xffffffff; + return dest_mode ? hweight16(dest) > 1 : dest == 0xffffffffU; if ( dest_mode ) return hweight8(dest & @@ -831,7 +831,7 @@ void vlapic_reg_write(struct vcpu *v, unsigned int reg, uint32_t val) break; case APIC_ICR2: - vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000); + vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000U); break; case APIC_LVTT: /* LVT Timer Reg */ diff --git a/xen/arch/x86/include/asm/apicdef.h b/xen/arch/x86/include/asm/apicdef.h index 2440d83c8d..7f21d3f49c 100644 --- a/xen/arch/x86/include/asm/apicdef.h +++ b/xen/arch/x86/include/asm/apicdef.h @@ -8,7 +8,7 @@ * Ingo Molnar , 1999, 2000 */ -#define APIC_DEFAULT_PHYS_BASE 0xfee00000 +#define APIC_DEFAULT_PHYS_BASE 0xfee00000U #define APIC_ID 0x20 #define APIC_ID_MASK (0xFFu<<24) diff --git a/xen/arch/x86/include/asm/config.h b/xen/arch/x86/include/asm/config.h index fbc4bb3416..bbced338be 100644 --- a/xen/arch/x86/include/asm/config.h +++ b/xen/arch/x86/include/asm/config.h @@ -257,7 +257,7 @@ extern unsigned char boot_edid_info[128]; #endif /* CONFIG_PV32 */ #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START -#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000 +#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000U #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \ ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2) diff --git a/xen/arch/x86/include/asm/hpet.h b/xen/arch/x86/include/asm/hpet.h index 9919f74730..c5e8e9c8db 100644 --- a/xen/arch/x86/include/asm/hpet.h +++ b/xen/arch/x86/include/asm/hpet.h @@ -41,7 +41,7 @@ #define HPET_TN_ROUTE 0x3e00 #define HPET_TN_FSB 0x4000 #define HPET_TN_FSB_CAP 0x8000 -#define HPET_TN_RESERVED 0xffff0081 +#define HPET_TN_RESERVED 0xffff0081U #define HPET_TN_INT_ROUTE_CAP (0xffffffffULL << 32) diff --git a/xen/arch/x86/include/asm/hvm/trace.h b/xen/arch/x86/include/asm/hvm/trace.h index 696e42eb94..0437966d1f 100644 --- a/xen/arch/x86/include/asm/hvm/trace.h +++ b/xen/arch/x86/include/asm/hvm/trace.h @@ -58,7 +58,7 @@ #define DO_TRC_HVM_VLAPIC DEFAULT_HVM_MISC -#define TRC_PAR_LONG(par) ((par)&0xFFFFFFFF),((par)>>32) +#define TRC_PAR_LONG(par) ((par) & 0xFFFFFFFFU), ((par) >> 32) #define TRACE_2_LONG_2D(_e, d1, d2, ...) \ TRACE_4D(_e, d1, d2) @@ -93,7 +93,7 @@ HVMTRACE_ND(evt, 0, 0) #define HVMTRACE_LONG_1D(evt, d1) \ - HVMTRACE_2D(evt ## 64, (d1) & 0xFFFFFFFF, (d1) >> 32) + HVMTRACE_2D(evt ## 64, (d1) & 0xFFFFFFFFU, (d1) >> 32) #define HVMTRACE_LONG_2D(evt, d1, d2, ...) \ HVMTRACE_3D(evt ## 64, d1, d2) #define HVMTRACE_LONG_3D(evt, d1, d2, d3, ...) \ diff --git a/xen/arch/x86/include/asm/hvm/vioapic.h b/xen/arch/x86/include/asm/hvm/vioapic.h index 2944ec20dd..68af6dce79 100644 --- a/xen/arch/x86/include/asm/hvm/vioapic.h +++ b/xen/arch/x86/include/asm/hvm/vioapic.h @@ -32,7 +32,7 @@ #define VIOAPIC_EDGE_TRIG 0 #define VIOAPIC_LEVEL_TRIG 1 -#define VIOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000 +#define VIOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000U #define VIOAPIC_MEM_LENGTH 0x100 /* Direct registers. */ diff --git a/xen/arch/x86/include/asm/msi.h b/xen/arch/x86/include/asm/msi.h index a53ade95c9..d89723d009 100644 --- a/xen/arch/x86/include/asm/msi.h +++ b/xen/arch/x86/include/asm/msi.h @@ -37,7 +37,7 @@ */ #define MSI_ADDR_BASE_HI 0 -#define MSI_ADDR_BASE_LO 0xfee00000 +#define MSI_ADDR_BASE_LO 0xfee00000U #define MSI_ADDR_BASE_MASK (~0xfffff) #define MSI_ADDR_HEADER MSI_ADDR_BASE_LO diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 4f861c0bb4..69ca8677c0 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -30,7 +30,7 @@ #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 #define MSR_CTC_THREAD_MASK 0x0000ffff -#define MSR_CTC_CORE_MASK 0xffff0000 +#define MSR_CTC_CORE_MASK 0xffff0000U #define MSR_SPEC_CTRL 0x00000048 #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) @@ -181,35 +181,35 @@ (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \ EFER_AIBRSE) -#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ -#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ -#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ -#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ -#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ -#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ -#define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */ -#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ +#define MSR_STAR 0xc0000081U /* legacy mode SYSCALL target */ +#define MSR_LSTAR 0xc0000082U /* long mode SYSCALL target */ +#define MSR_CSTAR 0xc0000083U /* compat mode SYSCALL target */ +#define MSR_SYSCALL_MASK 0xc0000084U /* EFLAGS mask for syscall */ +#define MSR_FS_BASE 0xc0000100U /* 64bit FS base */ +#define MSR_GS_BASE 0xc0000101U /* 64bit GS base */ +#define MSR_SHADOW_GS_BASE 0xc0000102U /* SwapGS GS shadow */ +#define MSR_TSC_AUX 0xc0000103U /* Auxiliary TSC */ -#define MSR_K8_SYSCFG 0xc0010010 +#define MSR_K8_SYSCFG 0xc0010010U #define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18) #define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19) #define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20) #define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21) #define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22) -#define MSR_K8_IORR_BASE0 0xc0010016 -#define MSR_K8_IORR_MASK0 0xc0010017 -#define MSR_K8_IORR_BASE1 0xc0010018 -#define MSR_K8_IORR_MASK1 0xc0010019 +#define MSR_K8_IORR_BASE0 0xc0010016U +#define MSR_K8_IORR_MASK0 0xc0010017U +#define MSR_K8_IORR_BASE1 0xc0010018U +#define MSR_K8_IORR_MASK1 0xc0010019U -#define MSR_K8_TSEG_BASE 0xc0010112 /* AMD doc: SMMAddr */ -#define MSR_K8_TSEG_MASK 0xc0010113 /* AMD doc: SMMMask */ +#define MSR_K8_TSEG_BASE 0xc0010112U /* AMD doc: SMMAddr */ +#define MSR_K8_TSEG_MASK 0xc0010113U /* AMD doc: SMMMask */ -#define MSR_K8_VM_CR 0xc0010114 +#define MSR_K8_VM_CR 0xc0010114U #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1) #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4) -#define MSR_VIRT_SPEC_CTRL 0xc001011f /* Layout matches MSR_SPEC_CTRL */ +#define MSR_VIRT_SPEC_CTRL 0xc001011fU /* Layout matches MSR_SPEC_CTRL */ /* * Legacy MSR constants in need of cleanup. No new MSRs below this comment. @@ -293,7 +293,7 @@ #define CMCI_EN (1UL<<30) #define CMCI_THRESHOLD_MASK 0x7FFF -#define MSR_AMD64_MC0_MASK 0xc0010044 +#define MSR_AMD64_MC0_MASK 0xc0010044U #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) @@ -325,83 +325,83 @@ /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */ -#define MSR_K7_EVNTSEL0 0xc0010000 -#define MSR_K7_PERFCTR0 0xc0010004 -#define MSR_K7_EVNTSEL1 0xc0010001 -#define MSR_K7_PERFCTR1 0xc0010005 -#define MSR_K7_EVNTSEL2 0xc0010002 -#define MSR_K7_PERFCTR2 0xc0010006 -#define MSR_K7_EVNTSEL3 0xc0010003 -#define MSR_K7_PERFCTR3 0xc0010007 -#define MSR_K8_TOP_MEM1 0xc001001a -#define MSR_K7_CLK_CTL 0xc001001b -#define MSR_K8_TOP_MEM2 0xc001001d - -#define MSR_K8_HWCR 0xc0010015 +#define MSR_K7_EVNTSEL0 0xc0010000U +#define MSR_K7_PERFCTR0 0xc0010004U +#define MSR_K7_EVNTSEL1 0xc0010001U +#define MSR_K7_PERFCTR1 0xc0010005U +#define MSR_K7_EVNTSEL2 0xc0010002U +#define MSR_K7_PERFCTR2 0xc0010006U +#define MSR_K7_EVNTSEL3 0xc0010003U +#define MSR_K7_PERFCTR3 0xc0010007U +#define MSR_K8_TOP_MEM1 0xc001001aU +#define MSR_K7_CLK_CTL 0xc001001bU +#define MSR_K8_TOP_MEM2 0xc001001dU + +#define MSR_K8_HWCR 0xc0010015U #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24) #define K8_HWCR_CPUID_USER_DIS (1ULL << 35) -#define MSR_K7_FID_VID_CTL 0xc0010041 -#define MSR_K7_FID_VID_STATUS 0xc0010042 -#define MSR_K8_PSTATE_LIMIT 0xc0010061 -#define MSR_K8_PSTATE_CTRL 0xc0010062 -#define MSR_K8_PSTATE_STATUS 0xc0010063 -#define MSR_K8_PSTATE0 0xc0010064 -#define MSR_K8_PSTATE1 0xc0010065 -#define MSR_K8_PSTATE2 0xc0010066 -#define MSR_K8_PSTATE3 0xc0010067 -#define MSR_K8_PSTATE4 0xc0010068 -#define MSR_K8_PSTATE5 0xc0010069 -#define MSR_K8_PSTATE6 0xc001006A -#define MSR_K8_PSTATE7 0xc001006B -#define MSR_K8_ENABLE_C1E 0xc0010055 -#define MSR_K8_VM_HSAVE_PA 0xc0010117 - -#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200 -#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201 -#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202 -#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203 -#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204 -#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205 -#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206 -#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207 -#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208 -#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209 -#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020a -#define MSR_AMD_FAM15H_PERFCTR5 0xc001020b - -#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002 -#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003 -#define MSR_K8_FEATURE_MASK 0xc0011004 -#define MSR_K8_EXT_FEATURE_MASK 0xc0011005 +#define MSR_K7_FID_VID_CTL 0xc0010041U +#define MSR_K7_FID_VID_STATUS 0xc0010042U +#define MSR_K8_PSTATE_LIMIT 0xc0010061U +#define MSR_K8_PSTATE_CTRL 0xc0010062U +#define MSR_K8_PSTATE_STATUS 0xc0010063U +#define MSR_K8_PSTATE0 0xc0010064U +#define MSR_K8_PSTATE1 0xc0010065U +#define MSR_K8_PSTATE2 0xc0010066U +#define MSR_K8_PSTATE3 0xc0010067U +#define MSR_K8_PSTATE4 0xc0010068U +#define MSR_K8_PSTATE5 0xc0010069U +#define MSR_K8_PSTATE6 0xc001006AU +#define MSR_K8_PSTATE7 0xc001006BU +#define MSR_K8_ENABLE_C1E 0xc0010055U +#define MSR_K8_VM_HSAVE_PA 0xc0010117U + +#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200U +#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201U +#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202U +#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203U +#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204U +#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205U +#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206U +#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207U +#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208U +#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209U +#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020aU +#define MSR_AMD_FAM15H_PERFCTR5 0xc001020bU + +#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002U +#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003U +#define MSR_K8_FEATURE_MASK 0xc0011004U +#define MSR_K8_EXT_FEATURE_MASK 0xc0011005U /* AMD64 MSRs */ -#define MSR_AMD64_NB_CFG 0xc001001f +#define MSR_AMD64_NB_CFG 0xc001001fU #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 -#define MSR_AMD64_LS_CFG 0xc0011020 -#define MSR_AMD64_IC_CFG 0xc0011021 -#define MSR_AMD64_DC_CFG 0xc0011022 -#define MSR_AMD64_DE_CFG 0xc0011029 +#define MSR_AMD64_LS_CFG 0xc0011020U +#define MSR_AMD64_IC_CFG 0xc0011021U +#define MSR_AMD64_DC_CFG 0xc0011022U +#define MSR_AMD64_DE_CFG 0xc0011029U #define AMD64_DE_CFG_LFENCE_SERIALISE (_AC(1, ULL) << 1) -#define MSR_AMD64_EX_CFG 0xc001102c -#define MSR_AMD64_DE_CFG2 0xc00110e3 +#define MSR_AMD64_EX_CFG 0xc001102cU +#define MSR_AMD64_DE_CFG2 0xc00110e3U -#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027 -#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019 -#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101a -#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101b +#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027U +#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019U +#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101aU +#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101bU /* AMD Family10h machine check MSRs */ -#define MSR_F10_MC4_MISC1 0xc0000408 -#define MSR_F10_MC4_MISC2 0xc0000409 -#define MSR_F10_MC4_MISC3 0xc000040A +#define MSR_F10_MC4_MISC1 0xc0000408U +#define MSR_F10_MC4_MISC2 0xc0000409U +#define MSR_F10_MC4_MISC3 0xc000040AU /* AMD Family10h Bus Unit MSRs */ -#define MSR_F10_BU_CFG 0xc0011023 -#define MSR_F10_BU_CFG2 0xc001102a +#define MSR_F10_BU_CFG 0xc0011023U +#define MSR_F10_BU_CFG2 0xc001102aU /* Other AMD Fam10h MSRs */ -#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 +#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058U #define FAM10H_MMIO_CONF_ENABLE (1<<0) #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 @@ -410,31 +410,31 @@ /* AMD Microcode MSRs */ #define MSR_AMD_PATCHLEVEL 0x0000008b -#define MSR_AMD_PATCHLOADER 0xc0010020 +#define MSR_AMD_PATCHLOADER 0xc0010020U /* AMD TSC RATE MSR */ -#define MSR_AMD64_TSC_RATIO 0xc0000104 +#define MSR_AMD64_TSC_RATIO 0xc0000104U /* AMD Lightweight Profiling MSRs */ -#define MSR_AMD64_LWP_CFG 0xc0000105 -#define MSR_AMD64_LWP_CBADDR 0xc0000106 +#define MSR_AMD64_LWP_CFG 0xc0000105U +#define MSR_AMD64_LWP_CBADDR 0xc0000106U /* AMD OS Visible Workaround MSRs */ -#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140 -#define MSR_AMD_OSVW_STATUS 0xc0010141 +#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140U +#define MSR_AMD_OSVW_STATUS 0xc0010141U /* AMD Protected Processor Inventory Number */ -#define MSR_AMD_PPIN_CTL 0xc00102f0 -#define MSR_AMD_PPIN 0xc00102f1 +#define MSR_AMD_PPIN_CTL 0xc00102f0U +#define MSR_AMD_PPIN 0xc00102f1U /* K6 MSRs */ -#define MSR_K6_EFER 0xc0000080 -#define MSR_K6_STAR 0xc0000081 -#define MSR_K6_WHCR 0xc0000082 -#define MSR_K6_UWCCR 0xc0000085 -#define MSR_K6_EPMR 0xc0000086 -#define MSR_K6_PSOR 0xc0000087 -#define MSR_K6_PFIR 0xc0000088 +#define MSR_K6_EFER 0xc0000080U +#define MSR_K6_STAR 0xc0000081U +#define MSR_K6_WHCR 0xc0000082U +#define MSR_K6_UWCCR 0xc0000085U +#define MSR_K6_EPMR 0xc0000086U +#define MSR_K6_PSOR 0xc0000087U +#define MSR_K6_PFIR 0xc0000088U /* Centaur-Hauls/IDT defined MSRs. */ #define MSR_IDT_FCR1 0x00000107 @@ -459,10 +459,10 @@ #define MSR_VIA_BCR2 0x00001147 /* Transmeta defined MSRs */ -#define MSR_TMTA_LONGRUN_CTRL 0x80868010 -#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 -#define MSR_TMTA_LRTI_READOUT 0x80868018 -#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a +#define MSR_TMTA_LONGRUN_CTRL 0x80868010U +#define MSR_TMTA_LONGRUN_FLAGS 0x80868011U +#define MSR_TMTA_LRTI_READOUT 0x80868018U +#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801aU /* Intel defined MSRs. */ #define MSR_IA32_P5_MC_ADDR 0x00000000 diff --git a/xen/arch/x86/include/asm/pci.h b/xen/arch/x86/include/asm/pci.h index f4a58c8acf..e1dd12eb19 100644 --- a/xen/arch/x86/include/asm/pci.h +++ b/xen/arch/x86/include/asm/pci.h @@ -3,10 +3,10 @@ #include -#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00) >> 8) -#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fc) -#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000) >> 16) -#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000)) +#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00U) >> 8) +#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fcU) +#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000U) >> 16) +#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000U)) #define IS_SNB_GFX(id) (id == 0x01068086 || id == 0x01168086 \ || id == 0x01268086 || id == 0x01028086 \ diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h index e350227e57..f091bc9cf2 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -103,7 +103,7 @@ /* * Debug status flags in DR6. */ -#define X86_DR6_DEFAULT 0xffff0ff0 /* Default %dr6 value. */ +#define X86_DR6_DEFAULT 0xffff0ff0UL /* Default %dr6 value. */ /* * Debug control flags in DR7. diff --git a/xen/arch/x86/percpu.c b/xen/arch/x86/percpu.c index 288050cdba..1ebeb65ad6 100644 --- a/xen/arch/x86/percpu.c +++ b/xen/arch/x86/percpu.c @@ -12,7 +12,7 @@ unsigned long __per_cpu_offset[NR_CPUS]; * possible #PF at (NULL + a little) which has security implications in the * context of PV guests. */ -#define INVALID_PERCPU_AREA (0x8000000000000000L - (long)__per_cpu_start) +#define INVALID_PERCPU_AREA (0x8000000000000000UL - (long)__per_cpu_start) #define PERCPU_ORDER get_order_from_bytes(__per_cpu_data_end - __per_cpu_start) void __init percpu_init_areas(void) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index a1e0af27c5..5581b4717a 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -191,7 +191,7 @@ static struct feat_node *feat_l2_cat; static struct feat_node *feat_mba; /* Common functions */ -#define cat_default_val(len) (0xffffffff >> (32 - (len))) +#define cat_default_val(len) (0xffffffffU >> (32 - (len))) /* * get_cdp_data - get DATA COS register value from input COS ID. diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 4081cef200..b030ad8a5b 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -398,8 +398,8 @@ static void __init print_details(enum ind_thunk thunk) cpuid_count(7, 0, &max, &tmp, &tmp, &_7d0); if ( max >= 2 ) cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2); - if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 ) - cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp); + if ( boot_cpu_data.extended_cpuid_level >= 0x80000008U ) + cpuid(0x80000008U, &tmp, &e8b, &tmp, &tmp); if ( cpu_has_arch_caps ) rdmsrl(MSR_ARCH_CAPABILITIES, caps); @@ -1337,8 +1337,8 @@ void __init init_speculation_mitigations(void) * TODO: Adjust cpu_has_svm_spec_ctrl to be usable earlier on boot. */ if ( opt_msr_sc_hvm && - (boot_cpu_data.extended_cpuid_level >= 0x8000000a) && - (cpuid_edx(0x8000000a) & (1u << SVM_FEATURE_SPEC_CTRL)) ) + (boot_cpu_data.extended_cpuid_level >= 0x8000000aU) && + (cpuid_edx(0x8000000aU) & (1u << SVM_FEATURE_SPEC_CTRL)) ) setup_force_cpu_cap(X86_FEATURE_SC_MSR_HVM); } diff --git a/xen/arch/x86/x86_64/acpi_mmcfg.c b/xen/arch/x86/x86_64/acpi_mmcfg.c index 2159c68189..cdde7e453c 100644 --- a/xen/arch/x86/x86_64/acpi_mmcfg.c +++ b/xen/arch/x86/x86_64/acpi_mmcfg.c @@ -50,7 +50,7 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, { int year; - if (cfg->address < 0xFFFFFFFF) + if (cfg->address < 0xFFFFFFFFU) return 0; if (!strncmp(mcfg->header.oem_id, "SGI", 3)) diff --git a/xen/arch/x86/x86_64/pci.c b/xen/arch/x86/x86_64/pci.c index aad1c3f7cf..8d33429103 100644 --- a/xen/arch/x86/x86_64/pci.c +++ b/xen/arch/x86/x86_64/pci.c @@ -9,7 +9,7 @@ #include #define PCI_CONF_ADDRESS(sbdf, reg) \ - (0x80000000 | ((sbdf).bdf << 8) | ((reg) & ~3)) + (0x80000000U | ((sbdf).bdf << 8) | ((reg) & ~3)) uint8_t pci_conf_read8(pci_sbdf_t sbdf, unsigned int reg) { diff --git a/xen/arch/x86/x86_emulate/x86_emulate.h b/xen/arch/x86/x86_emulate/x86_emulate.h index 698750267a..d92be69d84 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.h +++ b/xen/arch/x86/x86_emulate/x86_emulate.h @@ -620,7 +620,7 @@ struct x86_emulate_ctxt * below). * Hence no separate #define-s get added. */ -#define X86EMUL_OPC_EXT_MASK 0xffff0000 +#define X86EMUL_OPC_EXT_MASK 0xffff0000U #define X86EMUL_OPC(ext, byte) ((uint8_t)(byte) | \ MASK_INSR((ext), X86EMUL_OPC_EXT_MASK)) /* diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c index 07e5501914..a4ea579ebe 100644 --- a/xen/lib/x86/cpuid.c +++ b/xen/lib/x86/cpuid.c @@ -217,10 +217,10 @@ void x86_cpu_policy_fill_native(struct cpu_policy *p) } /* Extended leaves. */ - cpuid_leaf(0x80000000, &p->extd.raw[0]); + cpuid_leaf(0x80000000U, &p->extd.raw[0]); for ( i = 1; i <= MIN(p->extd.max_leaf & 0xffffU, ARRAY_SIZE(p->extd.raw) - 1); ++i ) - cpuid_leaf(0x80000000 + i, &p->extd.raw[i]); + cpuid_leaf(0x80000000U + i, &p->extd.raw[i]); /* Don't report leaves from possible lower level hypervisor, for now. */ p->hv_limit = 0; @@ -421,7 +421,7 @@ int x86_cpuid_copy_to_buffer(const struct cpu_policy *p, /* Extended leaves. */ for ( leaf = 0; leaf <= MIN(p->extd.max_leaf & 0xfffful, ARRAY_SIZE(p->extd.raw) - 1); ++leaf ) - COPY_LEAF(0x80000000 | leaf, XEN_CPUID_NO_SUBLEAF, &p->extd.raw[leaf]); + COPY_LEAF(0x80000000U | leaf, XEN_CPUID_NO_SUBLEAF, &p->extd.raw[leaf]); #undef COPY_LEAF @@ -521,7 +521,7 @@ int x86_cpuid_copy_from_buffer(struct cpu_policy *p, p->hv2_limit = l.a; break; - case 0x80000000 ... 0x80000000 + ARRAY_SIZE(p->extd.raw) - 1: + case 0x80000000U ... 0x80000000U + ARRAY_SIZE(p->extd.raw) - 1: if ( data.subleaf != XEN_CPUID_NO_SUBLEAF ) goto out_of_range; diff --git a/xen/lib/x86/policy.c b/xen/lib/x86/policy.c index a9c60000af..f033d22785 100644 --- a/xen/lib/x86/policy.c +++ b/xen/lib/x86/policy.c @@ -22,7 +22,7 @@ int x86_cpu_policies_are_compatible(const struct cpu_policy *host, FAIL_CPUID(7, 0); if ( guest->extd.max_leaf > host->extd.max_leaf ) - FAIL_CPUID(0x80000000, NA); + FAIL_CPUID(0x80000000U, NA); /* TODO: Audit more CPUID data. */ From patchwork Wed Jul 12 10:32:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by 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(mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9e15446a-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:34:02 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 9949A4EE074E; Wed, 12 Jul 2023 12:34:00 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9e15446a-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Paul Durrant , Wei Liu , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 13/15] x86/viridian: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:14 +0200 Message-Id: <925b70ccf1140945d6a1e73263c84e3b6db12ec8.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type and also to other literals used in the same contexts or near violations, when their positive nature is immediately clear. The latter changes are done for the sake of uniformity. Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- Changes in v3: - create this commit for 'viridian.c' and 'hyperv-tlfs.h' --- xen/arch/x86/hvm/viridian/viridian.c | 2 +- xen/arch/x86/include/asm/guest/hyperv-tlfs.h | 28 ++++++++++---------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/hvm/viridian/viridian.c b/xen/arch/x86/hvm/viridian/viridian.c index 7405c117bc..61171e3363 100644 --- a/xen/arch/x86/hvm/viridian/viridian.c +++ b/xen/arch/x86/hvm/viridian/viridian.c @@ -291,7 +291,7 @@ static void enable_hypercall_page(struct domain *d) * calling convention) to differentiate Xen and Viridian hypercalls. */ *(u8 *)(p + 0) = 0x0d; /* orl $0x80000000, %eax */ - *(u32 *)(p + 1) = 0x80000000; + *(u32 *)(p + 1) = 0x80000000U; *(u8 *)(p + 5) = 0x0f; /* vmcall/vmmcall */ *(u8 *)(p + 6) = 0x01; *(u8 *)(p + 7) = (cpu_has_vmx ? 0xc1 : 0xd9); diff --git a/xen/arch/x86/include/asm/guest/hyperv-tlfs.h b/xen/arch/x86/include/asm/guest/hyperv-tlfs.h index 38f997a0c8..a6915ad731 100644 --- a/xen/arch/x86/include/asm/guest/hyperv-tlfs.h +++ b/xen/arch/x86/include/asm/guest/hyperv-tlfs.h @@ -471,30 +471,30 @@ typedef struct _HV_REFERENCE_TSC_PAGE { /* Define hypervisor message types. */ enum hv_message_type { - HVMSG_NONE = 0x00000000, + HVMSG_NONE = 0x00000000U, /* Memory access messages. */ - HVMSG_UNMAPPED_GPA = 0x80000000, - HVMSG_GPA_INTERCEPT = 0x80000001, + HVMSG_UNMAPPED_GPA = 0x80000000U, + HVMSG_GPA_INTERCEPT = 0x80000001U, /* Timer notification messages. */ - HVMSG_TIMER_EXPIRED = 0x80000010, + HVMSG_TIMER_EXPIRED = 0x80000010U, /* Error messages. */ - HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, - HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, - HVMSG_UNSUPPORTED_FEATURE = 0x80000022, + HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020U, + HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021U, + HVMSG_UNSUPPORTED_FEATURE = 0x80000022U, /* Trace buffer complete messages. */ - HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, + HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040U, /* Platform-specific processor intercept messages. */ - HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, - HVMSG_X64_MSR_INTERCEPT = 0x80010001, - HVMSG_X64_CPUID_INTERCEPT = 0x80010002, - HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, - HVMSG_X64_APIC_EOI = 0x80010004, - HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 + HVMSG_X64_IOPORT_INTERCEPT = 0x80010000U, + HVMSG_X64_MSR_INTERCEPT = 0x80010001U, + HVMSG_X64_CPUID_INTERCEPT = 0x80010002U, + HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003U, + HVMSG_X64_APIC_EOI = 0x80010004U, + HVMSG_X64_LEGACY_FP_ERROR = 0x80010005U }; /* Define synthetic interrupt controller message flags. */ From patchwork Wed Jul 12 10:32:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B47EBEB64D9 for ; Wed, 12 Jul 2023 10:37:40 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562258.878909 (Exim 4.92) (envelope-from ) id 1qJXDn-0004Co-UV; Wed, 12 Jul 2023 10:37:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562258.878909; Wed, 12 Jul 2023 10:37:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXDn-0004Bl-Pg; Wed, 12 Jul 2023 10:37:23 +0000 Received: by outflank-mailman (input) for mailman id 562258; Wed, 12 Jul 2023 10:37:22 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAc-00061z-BS for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:34:06 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9edd3c6f-209f-11ee-8611-37d641c3527e; Wed, 12 Jul 2023 12:34:03 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id F15154EE0C8F; Wed, 12 Jul 2023 12:34:01 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9edd3c6f-209f-11ee-8611-37d641c3527e From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 14/15] ACPI/APEI: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:15 +0200 Message-Id: <9fa7f3b467b7efbe1c9f80269c4af942fbebea8d.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type. For the sake of uniformity, the following changes are made: - add the 'U' suffix to all first macro's arguments in 'cper.h' Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Acked-by: Jan Beulich --- Changes in v3: - create this commit for 'cper.h' --- xen/include/xen/cper.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/include/xen/cper.h b/xen/include/xen/cper.h index f8e5272bc1..7c6a4c45ce 100644 --- a/xen/include/xen/cper.h +++ b/xen/include/xen/cper.h @@ -56,7 +56,7 @@ static inline uint64_t cper_next_record_id(void) #define CPER_SIG_RECORD "CPER" #define CPER_SIG_SIZE 4 /* Used in signature_end field in struct cper_record_header */ -#define CPER_SIG_END 0xffffffff +#define CPER_SIG_END 0xffffffffU /* * CPER record header revision, used in revision field in struct @@ -80,35 +80,35 @@ static inline uint64_t cper_next_record_id(void) * Corrected Machine Check */ #define CPER_NOTIFY_CMC \ - UUID_LE(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \ + UUID_LE(0x2DCE8BB1U, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \ 0xEB, 0xD4, 0xF8, 0x90) /* Corrected Platform Error */ #define CPER_NOTIFY_CPE \ - UUID_LE(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \ + UUID_LE(0x4E292F96U, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81, \ 0xF2, 0x7E, 0xBE, 0xEE) /* Machine Check Exception */ #define CPER_NOTIFY_MCE \ - UUID_LE(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \ + UUID_LE(0xE8F56FFEU, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \ 0xE1, 0x49, 0x13, 0xBB) /* PCI Express Error */ #define CPER_NOTIFY_PCIE \ - UUID_LE(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \ + UUID_LE(0xCF93C01FU, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D, \ 0xAF, 0x67, 0xC1, 0x04) /* INIT Record (for IPF) */ #define CPER_NOTIFY_INIT \ - UUID_LE(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \ + UUID_LE(0xCC5263E8U, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B, \ 0xD3, 0x9B, 0xC9, 0x8E) /* Non-Maskable Interrupt */ #define CPER_NOTIFY_NMI \ - UUID_LE(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \ + UUID_LE(0x5BAD89FFU, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24, \ 0x85, 0xD6, 0xE9, 0x8A) /* BOOT Error Record */ #define CPER_NOTIFY_BOOT \ - UUID_LE(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \ + UUID_LE(0x3D61A466U, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \ 0xD4, 0x64, 0xB3, 0x8F) /* DMA Remapping Error */ #define CPER_NOTIFY_DMAR \ - UUID_LE(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \ + UUID_LE(0x667DD791U, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \ 0x72, 0x2D, 0xEB, 0x41) /* From patchwork Wed Jul 12 10:32:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simone Ballarin X-Patchwork-Id: 13310090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6BB1EB64D9 for ; Wed, 12 Jul 2023 10:37:37 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.562257.878905 (Exim 4.92) (envelope-from ) id 1qJXDn-0004Am-Kr; Wed, 12 Jul 2023 10:37:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 562257.878905; Wed, 12 Jul 2023 10:37:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXDn-0004Ad-G1; Wed, 12 Jul 2023 10:37:23 +0000 Received: by outflank-mailman (input) for mailman id 562257; Wed, 12 Jul 2023 10:37:22 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qJXAb-0006Dd-EF for xen-devel@lists.xenproject.org; Wed, 12 Jul 2023 10:34:05 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9fa98df3-209f-11ee-b239-6b7b168915f2; Wed, 12 Jul 2023 12:34:04 +0200 (CEST) Received: from beta.bugseng.com (unknown [37.161.151.90]) by support.bugseng.com (Postfix) with ESMTPSA id 4CB734EE0737; Wed, 12 Jul 2023 12:34:03 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9fa98df3-209f-11ee-b239-6b7b168915f2 From: Simone Ballarin To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Gianluca Luparini , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Michal Orzel , Xenia Ragiadakou , Ayan Kumar Halder , Simone Ballarin Subject: [XEN PATCH v3 15/15] xen: fix violations of MISRA C:2012 Rule 7.2 Date: Wed, 12 Jul 2023 12:32:16 +0200 Message-Id: <7a58c9341d10ef79e117ac35da048bbb088ec5d0.1689152719.git.gianluca.luparini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 From: Gianluca Luparini The xen sources contains violations of MISRA C:2012 Rule 7.2 whose headline states: "A 'u' or 'U' suffix shall be applied to all integer constants that are represented in an unsigned type". Add the 'U' suffix to integers literals with unsigned type. Fot the sake of uniformity, the following changes are made: - add the 'U' suffix to all integer constants before the '?' operator in 'bitops.h' Signed-off-by: Gianluca Luparini Signed-off-by: Simone Ballarin Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- Changes in v3: - change 'Signed-off-by' ordering - change commit message - fix in 'muldiv64.c' - add changes to 'bitops.h' macros - move 'cper.h' in a separate commit Changes in v2: - minor change to commit title - change commit message - add '(uint32_t)' in 'muldiv64.c' for consistency - add fix in 'vesa.c' --- xen/common/gunzip.c | 2 +- xen/common/xmalloc_tlsf.c | 2 +- xen/drivers/char/ehci-dbgp.c | 4 ++-- xen/drivers/video/vesa.c | 2 +- xen/include/public/memory.h | 2 +- xen/include/public/sysctl.h | 4 ++-- xen/include/xen/bitops.h | 10 +++++----- xen/lib/muldiv64.c | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) diff --git a/xen/common/gunzip.c b/xen/common/gunzip.c index 71ec5f26be..b810499be2 100644 --- a/xen/common/gunzip.c +++ b/xen/common/gunzip.c @@ -11,7 +11,7 @@ static unsigned char *__initdata window; static memptr __initdata free_mem_ptr; static memptr __initdata free_mem_end_ptr; -#define WSIZE 0x80000000 +#define WSIZE 0x80000000U static unsigned char *__initdata inbuf; static unsigned int __initdata insize; diff --git a/xen/common/xmalloc_tlsf.c b/xen/common/xmalloc_tlsf.c index 75bdf18c4e..c21bf71e88 100644 --- a/xen/common/xmalloc_tlsf.c +++ b/xen/common/xmalloc_tlsf.c @@ -46,7 +46,7 @@ #define BHDR_OVERHEAD (sizeof(struct bhdr) - MIN_BLOCK_SIZE) #define PTR_MASK (sizeof(void *) - 1) -#define BLOCK_SIZE_MASK (0xFFFFFFFF - PTR_MASK) +#define BLOCK_SIZE_MASK (0xFFFFFFFFU - PTR_MASK) #define GET_NEXT_BLOCK(addr, r) ((struct bhdr *) \ ((char *)(addr) + (r))) diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c index bb9d3198d9..4d8d765122 100644 --- a/xen/drivers/char/ehci-dbgp.c +++ b/xen/drivers/char/ehci-dbgp.c @@ -375,12 +375,12 @@ static inline u32 dbgp_pid_write_update(u32 x, u32 tok) static u8 data0 = USB_PID_DATA1; data0 ^= USB_PID_DATA0 ^ USB_PID_DATA1; - return (x & 0xffff0000) | (data0 << 8) | (tok & 0xff); + return (x & 0xffff0000U) | (data0 << 8) | (tok & 0xffU); } static inline u32 dbgp_pid_read_update(u32 x, u32 tok) { - return (x & 0xffffff00) | (tok & 0xff); + return (x & 0xffffff00U) | (tok & 0xffU); } static inline void dbgp_set_data(struct ehci_dbg_port __iomem *ehci_debug, diff --git a/xen/drivers/video/vesa.c b/xen/drivers/video/vesa.c index c41f6b8d40..b007ff5678 100644 --- a/xen/drivers/video/vesa.c +++ b/xen/drivers/video/vesa.c @@ -123,7 +123,7 @@ void __init vesa_init(void) if ( vlfb_info.bits_per_pixel > 8 ) { /* Light grey in truecolor. */ - unsigned int grey = 0xaaaaaaaa; + unsigned int grey = 0xaaaaaaaaU; lfbp.pixel_on = ((grey >> (32 - vlfb_info. red_size)) << vlfb_info. red_pos) | ((grey >> (32 - vlfb_info.green_size)) << vlfb_info.green_pos) | diff --git a/xen/include/public/memory.h b/xen/include/public/memory.h index c5f0d31e23..5e545ae9a4 100644 --- a/xen/include/public/memory.h +++ b/xen/include/public/memory.h @@ -234,7 +234,7 @@ struct xen_add_to_physmap { unsigned int space; /* => enum phys_map_space */ -#define XENMAPIDX_grant_table_status 0x80000000 +#define XENMAPIDX_grant_table_status 0x80000000U /* Index into space being mapped. */ xen_ulong_t idx; diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index 33e86ace51..fa7147de47 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -384,7 +384,7 @@ struct xen_sysctl_pm_op { struct xen_set_cpufreq_para set_para; uint64_aligned_t get_avgfreq; uint32_t set_sched_opt_smt; -#define XEN_SYSCTL_CX_UNLIMITED 0xffffffff +#define XEN_SYSCTL_CX_UNLIMITED 0xffffffffU uint32_t get_max_cstate; uint32_t set_max_cstate; } u; @@ -547,7 +547,7 @@ struct xen_sysctl_numainfo { #define XEN_SYSCTL_CPUPOOL_OP_RMCPU 5 /* R */ #define XEN_SYSCTL_CPUPOOL_OP_MOVEDOMAIN 6 /* M */ #define XEN_SYSCTL_CPUPOOL_OP_FREEINFO 7 /* F */ -#define XEN_SYSCTL_CPUPOOL_PAR_ANY 0xFFFFFFFF +#define XEN_SYSCTL_CPUPOOL_PAR_ANY 0xFFFFFFFFU struct xen_sysctl_cpupool_op { uint32_t op; /* IN */ uint32_t cpupool_id; /* IN: CDIARM OUT: CI */ diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index 4cd0310789..e926047932 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -227,11 +227,11 @@ static inline __u32 ror32(__u32 word, unsigned int shift) } /* base-2 logarithm */ -#define __L2(_x) (((_x) & 0x00000002) ? 1 : 0) -#define __L4(_x) (((_x) & 0x0000000c) ? ( 2 + __L2( (_x)>> 2)) : __L2( _x)) -#define __L8(_x) (((_x) & 0x000000f0) ? ( 4 + __L4( (_x)>> 4)) : __L4( _x)) -#define __L16(_x) (((_x) & 0x0000ff00) ? ( 8 + __L8( (_x)>> 8)) : __L8( _x)) -#define ilog2(_x) (((_x) & 0xffff0000) ? (16 + __L16((_x)>>16)) : __L16(_x)) +#define __L2(x) (((x) & 0x00000002U) ? 1 : 0) +#define __L4(x) (((x) & 0x0000000cU) ? ( 2 + __L2( (x) >> 2)) : __L2( x)) +#define __L8(x) (((x) & 0x000000f0U) ? ( 4 + __L4( (x) >> 4)) : __L4( x)) +#define __L16(x) (((x) & 0x0000ff00U) ? ( 8 + __L8( (x) >> 8)) : __L8( x)) +#define ilog2(x) (((x) & 0xffff0000U) ? (16 + __L16((x) >> 16)) : __L16(x)) /** * for_each_set_bit - iterate over every set bit in a memory region diff --git a/xen/lib/muldiv64.c b/xen/lib/muldiv64.c index 78177ce616..a51cbc8767 100644 --- a/xen/lib/muldiv64.c +++ b/xen/lib/muldiv64.c @@ -27,7 +27,7 @@ uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) rh = (uint64_t)u.l.high * (uint64_t)b; rh += (rl >> 32); res.l.high = rh / c; - res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; + res.l.low = (((rh % c) << 32) + ((uint32_t)rl)) / c; return res.ll; #endif