From patchwork Mon Jul 17 15:27:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13315942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6EC9C04A6A for ; Mon, 17 Jul 2023 15:28:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229670AbjGQP2c (ORCPT ); Mon, 17 Jul 2023 11:28:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232220AbjGQP16 (ORCPT ); Mon, 17 Jul 2023 11:27:58 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20FEA2128 for ; Mon, 17 Jul 2023 08:27:28 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1b89e3715acso22502555ad.3 for ; Mon, 17 Jul 2023 08:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689607647; x=1692199647; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=T195FWXfqucyEBgiIGQAY+Lmu6WGEseWSNrrUvHiu4k=; b=kOoTOacFJO9+uHVWHHqMzZUX8/dwgTKGK16Eo5ITJVuv8lBgElCfJCMjxew+K8LFhS 0GysunMasR920l3SSl3P1E9H6MG66vreYE/A/hoaEEJom/uKr7dGst7zkry0m4tU49E3 tvH8jPnZrUJ3n4XKLeUkSZ/GdivDj+baCykn44EudzfpfOvTXDaDSw3twySIRBSrD8pS uorNxDt+Xg1bfg7pWfLzylmCrMXSCayowem3n4taDuSjy3E+hAsxqwYdpbZBKJsCKwNW jwfXjyOrHVd8AasOuj+dAbxTjBnEw2867xWLAV6e4Fexi+xj9wlHjDFJehhW18rNQh2o EnsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607647; x=1692199647; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=T195FWXfqucyEBgiIGQAY+Lmu6WGEseWSNrrUvHiu4k=; b=U5XbE4md0EwwSDYJpbDbv0dG2ueGLl2+J6OMKLTB5xt03gprGj+pJt2cS3WBVjmoBi uk45kkNMDGunEuugEehPCJOYk63DIN4M0zgmZ/41JLdcsWLCo144EVInCo//JqVc9IK6 lM1x9CFAEUJCl890JXO1Q3PqfypJbzH3G59GXDsBL1t4rDFwhudCKlkKcVIKz+S4Vsqq oJ5UBM08ZTJVdt//ayWWj295cVdmNzg+m6jsmvHwKiCtt4EIDEYThTzdjZu5hRwOjRSC A1SddZJw8xNtk0JbHZKx1Cg4q1XXqnnXqUeKZ5lBsT8ZjmhzSFzpouMVV2J8tUv1ncea Be5w== X-Gm-Message-State: ABy/qLZEuQrDgtvz6s4reWiYhWTfbtXX6A5iCSLXu8SPHD11rD+j8GHw DBBA2ZkZ7a+Sb13B3aEwraglsfCu/WTGQ+GlbKuYtyU6VuCBrtSAkfli2X83mkgSXXsZR1h811y 3MwMmOd0odfRGh6gpGyN7snCuTO80PvI3TDaRr6rvqQ37z3N8FEbGTpGDHIhPh1wrTw3esuY= X-Google-Smtp-Source: APBJJlHIl7j3tQllnrhzxMlMfd0kK1zkhxUn4crAb5Cbfzt/zjRHX6e+NgOaoE/NYrO8gVVSsE2pUunvbNtvgstR8g== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:902:d503:b0:1b8:8c7:31e6 with SMTP id b3-20020a170902d50300b001b808c731e6mr83plg.1.1689607646689; Mon, 17 Jul 2023 08:27:26 -0700 (PDT) Date: Mon, 17 Jul 2023 15:27:18 +0000 In-Reply-To: <20230717152722.1837864-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230717152722.1837864-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230717152722.1837864-2-jingzhangos@google.com> Subject: [PATCH v6 1/5] KVM: arm64: Use guest ID register values for the sake of emulation From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since KVM now supports per-VM ID registers, use per-VM ID register values for the sake of emulation for DBGDIDR and LORegion. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index bd3431823ec5..c1a5ec1a016e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -379,7 +379,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + u64 val = IDREG(vcpu->kvm, SYS_ID_AA64MMFR1_EL1); u32 sr = reg_to_encoding(r); if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { @@ -2429,8 +2429,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu, if (p->is_write) { return ignore_write(vcpu, p); } else { - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + u64 dfr = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); + u64 pfr = IDREG(vcpu->kvm, SYS_ID_AA64PFR0_EL1); u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | From patchwork Mon Jul 17 15:27:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13315945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0045EB64DC for ; Mon, 17 Jul 2023 15:28:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231666AbjGQP2h (ORCPT ); Mon, 17 Jul 2023 11:28:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232246AbjGQP17 (ORCPT ); Mon, 17 Jul 2023 11:27:59 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13820268B for ; Mon, 17 Jul 2023 08:27:30 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id d2e1a72fcca58-666e3dad70aso4087891b3a.0 for ; Mon, 17 Jul 2023 08:27:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689607648; x=1692199648; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=cSCQIj8rChbfCOl6GeXcnV+0FBKWws4kYFyMtOPVmVQ=; b=V2uLwfsnnPM44DdfSQuu1BkbVTyIjO+vUCUDSmyhWMMoTCHvDN9UlrJpA7P7bPfLxm t1BfUdLH5F3+dd/VgujBZvSpbytgIvASd0zwKVwixZSrLGg7JiA4ZgffOl3mHCqzlN+z RNf5Tq4MwCrSdkLG1NP55PRDCKJtZGkF6MYGpqiC9Wn5tMI4qRny3AVKOPKKjboSvGuB kOumAIzirxwPQNF4ulL02KMJlm7oEiKBWKr+1b+A3fk6L/Hk1paiapzRuohn0azeqPtG C8O+lqIKUe4D9ST/bOasewSFmLQalLrzH57c/XGUghh+PixoGr25ah87368yGdvMh5vY kdZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607648; x=1692199648; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cSCQIj8rChbfCOl6GeXcnV+0FBKWws4kYFyMtOPVmVQ=; b=a2Gxoi+Ki4P8vpzB2jRXIQ4PukbDRY8APoNiuIkHpvb++tuWZeZVdIy9frhwikqHXb B6vn0a2AJczPrRL0VCzT8J/tYlBCpjeyDrE0ZUMKw3AypVy2fP66SE3cXPwwBwgG6Dma kSoZrgi5M2fXWvO0vlqWz7lRDP/U5nH1QFh41bX3jheHZzsAzRsnexblvGdNuPPHWmIR Ft/vwAfiLr/7yCeMzeTVXhSRmbRl65uzUxVyMDQYboJ11O96/88zwAZ/QndM5BMb1Dgv Zo4bBJ0r9kyhb3r1E7EqZb2xaAVybnGBVFuS+ukmtulTETzl+4SW+Gdr/65FP8pFforu 7tAA== X-Gm-Message-State: ABy/qLYRq+bI1qWpOVCS2uw8+sYUy5DRROb7bq6RD/rB32vHTG5b7sUR 1r/WFvLkuxAQGAxJCmIitDZ/M1JXCqSu7upbBevAs4CdZQ4VFuCJLqycWpcijEU9oXvvS7v83T7 Fooy7iW4SS415FrA0ht9LKC9+DqH3fz19dukN0YPDgryQa+0tNxNXUR6kmozUhNZxcpMLBCw= X-Google-Smtp-Source: APBJJlHt5JMRokoEdyLMXkVYl8bnTRXYt/VFatAnJx6tuzaITGsTM+Lynn51ngja4faQCfp0q8cLKIGAaMaUG6THSA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a05:6a00:3992:b0:668:9181:8e20 with SMTP id fi18-20020a056a00399200b0066891818e20mr135009pfb.1.1689607648372; Mon, 17 Jul 2023 08:27:28 -0700 (PDT) Date: Mon, 17 Jul 2023 15:27:19 +0000 In-Reply-To: <20230717152722.1837864-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230717152722.1837864-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230717152722.1837864-3-jingzhangos@google.com> Subject: [PATCH v6 2/5] KVM: arm64: Reject attempts to set invalid debug arch version From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Oliver Upton The debug architecture is mandatory in ARMv8, so KVM should not allow userspace to configure a vCPU with less than that. Of course, this isn't handled elegantly by the generic ID register plumbing, as the respective ID register fields have a nonzero starting value. Add an explicit check for debug versions less than v8 of the architecture. Signed-off-by: Oliver Upton Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c1a5ec1a016e..053d8057ff1e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1216,8 +1216,14 @@ static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, /* Some features have different safe value type in KVM than host features */ switch (id) { case SYS_ID_AA64DFR0_EL1: - if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT) + switch (kvm_ftr.shift) { + case ID_AA64DFR0_EL1_PMUVer_SHIFT: kvm_ftr.type = FTR_LOWER_SAFE; + break; + case ID_AA64DFR0_EL1_DebugVer_SHIFT: + kvm_ftr.type = FTR_LOWER_SAFE; + break; + } break; case SYS_ID_DFR0_EL1: if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) @@ -1469,14 +1475,22 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return val; } +#define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ +({ \ + u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ + (val) &= ~reg##_##field##_MASK; \ + (val) |= FIELD_PREP(reg##_##field##_MASK, \ + min(__f_val, (u64)reg##_##field##_##limit)); \ + (val); \ +}) + static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); /* Limit debug to ARMv8.0 */ - val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; - val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); /* * Only initialize the PMU version if the vCPU was configured with one. @@ -1496,6 +1510,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { + u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); /* @@ -1515,6 +1530,13 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; + /* + * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a + * nonzero minimum safe value. + */ + if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } @@ -1528,6 +1550,8 @@ static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, if (kvm_vcpu_has_pmu(vcpu)) val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); + return val; } @@ -1536,6 +1560,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, u64 val) { u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); + u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { val &= ~ID_DFR0_EL1_PerfMon_MASK; @@ -1551,6 +1576,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) return -EINVAL; + if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } From patchwork Mon Jul 17 15:27:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13315947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B21D6EB64DC for ; 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Mon, 17 Jul 2023 08:27:30 -0700 (PDT) Date: Mon, 17 Jul 2023 15:27:20 +0000 In-Reply-To: <20230717152722.1837864-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230717152722.1837864-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230717152722.1837864-4-jingzhangos@google.com> Subject: [PATCH v6 3/5] KVM: arm64: Enable writable for ID_AA64PFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org All valid fields in ID_AA64PFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 053d8057ff1e..fab525508510 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2042,7 +2042,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_reg, .reset = read_sanitised_id_aa64pfr0_el1, - .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), From patchwork Mon Jul 17 15:27:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13315946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFA7AC001DF for ; Mon, 17 Jul 2023 15:28:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229903AbjGQP2k (ORCPT ); Mon, 17 Jul 2023 11:28:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbjGQP2B (ORCPT ); Mon, 17 Jul 2023 11:28:01 -0400 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6632919B0 for ; Mon, 17 Jul 2023 08:27:33 -0700 (PDT) Received: by mail-pf1-x449.google.com with SMTP id d2e1a72fcca58-668728bb904so4033442b3a.2 for ; Mon, 17 Jul 2023 08:27:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689607653; x=1692199653; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=5mV2IQqjJWtXV0PBatZiBNfFvtLn0ngWE8+KQeRLOuQ=; b=qm7jCuMGI1Mba8afWkB5TQIv1cP7qNZPaBN/f7uEc95NpTwIrp6JKD6gRmDnRas6SA hKWz3eQh08Nxj5N9oXcrKW+yfrKo119N0LNYhGanZOznYQnpeBtgicuhvzDlP/BddKfP rlFQbc19xL0TNZ/4gcOkHrqeAt6/Lh8BQ9Z+L6H1+leLnUn253uACBCo+AygTvkGjIAG nEqm5rY8/DjGvLpRAz1TV+wuo1TwLDKupzMJmuyDtoRsAEZdOQeNoDcQ9ERejIaZZsL9 DLIDOzCenx70HCkeBlqXxlVnTnyMCnIYdWkxurspO7jgVDpi/JCTNd5Hjh+Qk67mLW9U iQpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607653; x=1692199653; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5mV2IQqjJWtXV0PBatZiBNfFvtLn0ngWE8+KQeRLOuQ=; b=gQkpCZyIVxoDfXt9QB08wBSyCx2ByUUeasc8ihvVK5LQdTIcS1BG+WeV4cpHMgRjWX S3+Q7+Pys5S5+hl9gzVH2TYxlS1UcHqVwOr+TV9ZM5fh4gQoaix85x44i5Pije6Py1QW bNy9pH+7xGJUMOf3HGpoyQZB0N07TMy7U0AFL2K3b/5HgBoqB4kxG15u/99QWjgjY1aV 3JO4Z9UByQSh/kra4fZYL9XJX9tBGjMDgQ1XaWNHmDFKoDEYba2f9lAhhvvszf9a1ciA 3Mr6Q3yq46RJ31jwDFUoLkT7Zr2YRCO0GK7QngfmfpQAA9b5dl14bYqk6kYA18SRl7ZJ /23g== X-Gm-Message-State: ABy/qLZn3MjYYzMaMyFIvnRkvyKrR1qRLoToU5a+qcg4kCdvpQUdDV9a hlM9wv+PTye5zx31qyiMtd6BNkyxzQpUGbCUztQHSdb70Mxu29RU7nj8fGrExoLTNZ4tj5cLLVf RLAFnGnwRD18FkCnP1q/ireWkOVrEsiaJWHseTwKHxibrq25IYruhDeC9RiOSZgRn5Cb6uVU= X-Google-Smtp-Source: APBJJlGWPC7Roh8Pd0zejhfDsSo3VBfRNb6G9bRpZN3JPepGli2gJO4trCOigT9eujUPRt4Q/PqJoaBeAl+3o8yMZw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a05:6a00:3a13:b0:668:95c1:b507 with SMTP id fj19-20020a056a003a1300b0066895c1b507mr145112pfb.6.1689607652562; Mon, 17 Jul 2023 08:27:32 -0700 (PDT) Date: Mon, 17 Jul 2023 15:27:21 +0000 In-Reply-To: <20230717152722.1837864-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230717152722.1837864-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230717152722.1837864-5-jingzhangos@google.com> Subject: [PATCH v6 4/5] KVM: arm64: Enable writable for ID_AA64MMFR{0, 1, 2, 3}_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Enable writable from userspace for ID_AA64MMFR{0, 1, 2, 3}_EL1. Added a macro for defining general writable idregs. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index fab525508510..5fbf14320ad9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1346,9 +1346,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS); break; - case SYS_ID_AA64MMFR2_EL1: - val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; - break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -1582,6 +1579,18 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, return set_id_reg(vcpu, rd, val); } +static u64 read_sanitised_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + u64 val; + u32 id = reg_to_encoding(rd); + + val = read_sanitised_ftr_reg(id); + val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; + + return val; +} + /* * cpufeature ID register user accessors * @@ -1856,6 +1865,16 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, .val = 0, \ } +#define ID_SANITISED_WRITABLE(name) { \ + SYS_DESC(SYS_##name), \ + .access = access_id_reg, \ + .get_user = get_id_reg, \ + .set_user = set_id_reg, \ + .visibility = id_visibility, \ + .reset = kvm_read_sanitised_id_reg, \ + .val = GENMASK(63, 0), \ +} + /* sys_reg_desc initialiser for known cpufeature ID registers */ #define AA32_ID_SANITISED(name) { \ SYS_DESC(SYS_##name), \ @@ -2077,10 +2096,15 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(6,7), /* CRm=7 */ - ID_SANITISED(ID_AA64MMFR0_EL1), - ID_SANITISED(ID_AA64MMFR1_EL1), - ID_SANITISED(ID_AA64MMFR2_EL1), - ID_SANITISED(ID_AA64MMFR3_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR0_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR1_EL1), + { SYS_DESC(SYS_ID_AA64MMFR2_EL1), + .access = access_id_reg, + .get_user = get_id_reg, + .set_user = set_id_reg, + .reset = read_sanitised_id_aa64mmfr2_el1, + .val = GENMASK(63, 0), }, + ID_SANITISED_WRITABLE(ID_AA64MMFR3_EL1), ID_UNALLOCATED(7,4), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6), From patchwork Mon Jul 17 15:27:22 2023 Content-Type: text/plain; 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Mon, 17 Jul 2023 08:27:34 -0700 (PDT) Date: Mon, 17 Jul 2023 15:27:22 +0000 In-Reply-To: <20230717152722.1837864-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230717152722.1837864-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230717152722.1837864-6-jingzhangos@google.com> Subject: [PATCH v6 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a test to verify setting ID registers from userapce is handled correctly by KVM. Signed-off-by: Jing Zhang --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/aarch64/set_id_regs.c | 163 ++++++++++++++++++ 2 files changed, 164 insertions(+) create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index c692cc86e7da..87ceadc1292a 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -144,6 +144,7 @@ TEST_GEN_PROGS_aarch64 += aarch64/get-reg-list TEST_GEN_PROGS_aarch64 += aarch64/hypercalls TEST_GEN_PROGS_aarch64 += aarch64/page_fault_test TEST_GEN_PROGS_aarch64 += aarch64/psci_test +TEST_GEN_PROGS_aarch64 += aarch64/set_id_regs TEST_GEN_PROGS_aarch64 += aarch64/smccc_filter TEST_GEN_PROGS_aarch64 += aarch64/vcpu_width_config TEST_GEN_PROGS_aarch64 += aarch64/vgic_init diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c new file mode 100644 index 000000000000..e2242ef36bab --- /dev/null +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * set_id_regs - Test for setting ID register from usersapce. + * + * Copyright (c) 2023 Google LLC. + * + * + * Test that KVM supports setting ID registers from userspace and handles the + * feature set correctly. + */ + +#include +#include "kvm_util.h" +#include "processor.h" +#include "test_util.h" +#include + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +struct reg_feature { + uint64_t reg; + uint64_t ftr_mask; +}; + +static void guest_code(void) +{ + for (;;) + GUEST_SYNC(0); +} + +static struct reg_feature lower_safe_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS) }, + { KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1), ARM64_FEATURE_MASK(ID_DFR0_COPDBG) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), ARM64_FEATURE_MASK(ID_AA64PFR0_EL3) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN4) }, +}; + +static void test_user_set_lower_safe(struct kvm_vcpu *vcpu) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lower_safe_reg_ftrs); i++) { + struct reg_feature *reg_ftr = lower_safe_reg_ftrs + i; + uint64_t val, new_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + + /* Set a safe value for the feature */ + if (ftr > 0) + ftr--; + + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + + vcpu_set_reg(vcpu, reg_ftr->reg, val); + vcpu_get_reg(vcpu, reg_ftr->reg, &new_val); + ASSERT_EQ(new_val, val); + } +} + +static struct reg_feature exact_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER) }, +}; + +static void test_user_set_exact(struct kvm_vcpu *vcpu) +{ + int i, r; + + for (i = 0; i < ARRAY_SIZE(exact_reg_ftrs); i++) { + struct reg_feature *reg_ftr = exact_reg_ftrs + i; + uint64_t val, old_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + old_val = val; + + /* Exact match */ + vcpu_set_reg(vcpu, reg_ftr->reg, val); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + + /* Smaller value */ + if (ftr > 0) + ftr--; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + + /* Bigger value */ + ftr += 2; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + } +} + +static struct reg_feature fail_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS) }, + { KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1), ARM64_FEATURE_MASK(ID_DFR0_MPROFDBG) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), ARM64_FEATURE_MASK(ID_AA64PFR0_EL2) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN64) }, +}; + +static void test_user_set_fail(struct kvm_vcpu *vcpu) +{ + int i, r; + + for (i = 0; i < ARRAY_SIZE(fail_reg_ftrs); i++) { + struct reg_feature *reg_ftr = fail_reg_ftrs + i; + uint64_t val, old_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + + /* Set a invalid value (too big) for the feature */ + ftr++; + + old_val = val; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + } +} + +int main(void) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + + ksft_print_header(); + ksft_set_plan(3); + + test_user_set_lower_safe(vcpu); + ksft_test_result_pass("test_user_set_lower_safe\n"); + + test_user_set_exact(vcpu); + ksft_test_result_pass("test_user_set_exact\n"); + + test_user_set_fail(vcpu); + ksft_test_result_pass("test_user_set_fail\n"); + + kvm_vm_free(vm); + + ksft_finished(); +}