From patchwork Tue Jul 18 16:45:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13317445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31E0FEB64DD for ; Tue, 18 Jul 2023 16:45:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232142AbjGRQpe (ORCPT ); Tue, 18 Jul 2023 12:45:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229476AbjGRQpc (ORCPT ); Tue, 18 Jul 2023 12:45:32 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 062FE118 for ; Tue, 18 Jul 2023 09:45:30 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-1b888bdacbcso30814125ad.2 for ; Tue, 18 Jul 2023 09:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689698729; x=1692290729; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=T195FWXfqucyEBgiIGQAY+Lmu6WGEseWSNrrUvHiu4k=; b=IG7T43kRHhKHqmEiMzHxNeQ56Cb0139AlcIhz2Mi/+JW/VCHRl4rYafsJFi/e2JFEi mIvhqJWXlfvC82JAWuBBk2Xi24o18hCzneiWW6VW8aULpxR+CjOWv13HmkdpoJv3DurC L2DbZRk4IwjvXC9sEiXHpWWw4Pc4Jue5D+o42rmQouFteNkDuRc4NNc9C/siUP8Ry8P8 D1oQnTyl/+aQ9787SxzIRkNdmje0ThG0RirnnIxVV7XnJB3HUNsYN5zxe8aZ/tadDsK4 akk9re/Kek0AM0PZ7I9ayA5J3l4ygxCa63qtk6CUH6Sjsz6434l1UfEiaefJAIXWtM/D F3Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689698729; x=1692290729; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=T195FWXfqucyEBgiIGQAY+Lmu6WGEseWSNrrUvHiu4k=; b=l3xn/DTguCM+ay0nybZPz4NBKZgjoS4xnWsIG4/Uot0lJBHLW5GZgMefAQN6NKNoOS LSBU/Zue0faca0Flpjgu2CwN0pqEAezZOAOkIjbXXvimxCOGUqh84XIgQLXkV0kIZYik iDUkkbYeHLir19TMrHUPwZru9y7AdGXJMNnP9YXqpsVMAEc0uu7P09N5otVOfZEqtJtQ pUB0HczWgYBBGi8Koeyv02IB81QeNd8kpnY2F+UvEKcu2B9eQc8dBwIu6EFRJi2gKXWn EEbnWl6v74/Q23zlc+Q9UcDWzyEEQOUR5nuCZsCI8+ZmUHFXXOHdXvADwFw+8c/XjCPM 0mhA== X-Gm-Message-State: ABy/qLY+dliYpb9jr0z/jy6bvbxYEZ6Xjof/qjd5OxZ9taXvBVhW7FxM c0yTWYO6DWhDrreZxzTIvQ7wzmeYX7PoEPGHhz3mvPhGVnHAgIUm8idm41HB+kn8nCOACNzMeFV JTHuTQmwAuPxF3xz8D8xLWPBU1x5NYeFNToQdmQkrJBm+RZ1nAtEH+eGiQIeMxC51m+/ThmQ= X-Google-Smtp-Source: APBJJlGDtopDEFCCENvpj9bk0ucRozmxIamafw8OCk4paTc3ega52yzZuM1x2wqjc5oWp4XpUi/NXDGnD1HR1/9cuQ== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:902:c952:b0:1b7:edcd:8dcf with SMTP id i18-20020a170902c95200b001b7edcd8dcfmr1194pla.4.1689698728793; Tue, 18 Jul 2023 09:45:28 -0700 (PDT) Date: Tue, 18 Jul 2023 16:45:17 +0000 In-Reply-To: <20230718164522.3498236-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230718164522.3498236-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230718164522.3498236-2-jingzhangos@google.com> Subject: [PATCH v6 1/6] KVM: arm64: Use guest ID register values for the sake of emulation From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since KVM now supports per-VM ID registers, use per-VM ID register values for the sake of emulation for DBGDIDR and LORegion. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index bd3431823ec5..c1a5ec1a016e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -379,7 +379,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + u64 val = IDREG(vcpu->kvm, SYS_ID_AA64MMFR1_EL1); u32 sr = reg_to_encoding(r); if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { @@ -2429,8 +2429,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu, if (p->is_write) { return ignore_write(vcpu, p); } else { - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + u64 dfr = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); + u64 pfr = IDREG(vcpu->kvm, SYS_ID_AA64PFR0_EL1); u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | From patchwork Tue Jul 18 16:45:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13317446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88614C001DC for ; Tue, 18 Jul 2023 16:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229476AbjGRQpf (ORCPT ); Tue, 18 Jul 2023 12:45:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231707AbjGRQpd (ORCPT ); Tue, 18 Jul 2023 12:45:33 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A102E10E5 for ; Tue, 18 Jul 2023 09:45:32 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1b8a4571c1aso30890555ad.0 for ; Tue, 18 Jul 2023 09:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689698732; x=1692290732; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=cSCQIj8rChbfCOl6GeXcnV+0FBKWws4kYFyMtOPVmVQ=; b=OFsJK+dXwdPf0RBHA0ktO8jyJwBWRS1dwKOOctx+6jTzsxE7Cm7G+aqSattjLShdXu Z1qEeVo/XnXv038/OcnI7aY4yaf6gIrxk7Yu8buHeU93ihINCwy+xSarl5JDKHVGZC+M 3Og0PhCKsDnvJjLI3hTMWIVp5uuq5wD2KrEv5IJeN8vWscPpElLbacdMXDahXUUuLz7d GxQzZMyPLVQndGVszsOp5ZJPzng4Dpv/fwzxPF2B7kiwaO1r9/xsTEi+b60g6UHQrIO9 wzQl8Px7jc6UzlzwbUibnrBIsenNSSeqRnlyMjAcq0uuiL0RJEauLpErf+JQ/a9OtAnU 6jNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689698732; x=1692290732; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cSCQIj8rChbfCOl6GeXcnV+0FBKWws4kYFyMtOPVmVQ=; b=UZlJ4Ro4/QX+fuywZfFXCS0sqwWrjGADIEZW8iU87piurYKyxGKlv7U9YA8hgPrN/R 9kkuDx1HCXixesGIIwGNqSTjpiJmJFkf2eW5msyQ1lf9NHJkra1nrogvhkQ2hJ5zn8kE bAmi/1w8gaBB/27Pzi/ACMududcxn3Rmk9w848MwvPBUkUKqOEcWqS3zRspHCqYHbJKy yetMoWqRanBeNFnMN8EONhYNn0EqTaOvkIToRDdQwxwbpFfU0f9RSk+tDnooO4qw08DT LOENpQGywi982huDHZ6W7iiB6m9UfvSn44Tjmr4nFEhlk1ulLyvFm7fZTLyVNkalV4n2 Jg8Q== X-Gm-Message-State: ABy/qLbRro0cWPSXEf7wHNCww3z+7ti2qQF56tJq41SNRTNMAOhpvnh3 KQMZCdQ7COqipbzznWflxwqia9CcYRkJPtsHoR+VPNZIss6p56rK9dXGNdQq4qZ/b6FE+PZNVmE 8oQCH3BtMv8UEZ8OhM5bp2en8FRQg3wKebz952JcIk98NoAUEN3Uerak+wTd1MosBlPBSrnk= X-Google-Smtp-Source: APBJJlEvf6ms5QOH822cn1EVJyhNAJK5wSXxGxatRmMDn9eETOI47IUA/zPlPUd4v3/huIcfn7gFBUTLmfU4n0bWaA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:902:e812:b0:1ae:6895:cb96 with SMTP id u18-20020a170902e81200b001ae6895cb96mr1340plg.5.1689698730965; Tue, 18 Jul 2023 09:45:30 -0700 (PDT) Date: Tue, 18 Jul 2023 16:45:18 +0000 In-Reply-To: <20230718164522.3498236-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230718164522.3498236-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230718164522.3498236-3-jingzhangos@google.com> Subject: [PATCH v6 2/6] KVM: arm64: Reject attempts to set invalid debug arch version From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Oliver Upton The debug architecture is mandatory in ARMv8, so KVM should not allow userspace to configure a vCPU with less than that. Of course, this isn't handled elegantly by the generic ID register plumbing, as the respective ID register fields have a nonzero starting value. Add an explicit check for debug versions less than v8 of the architecture. Signed-off-by: Oliver Upton Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c1a5ec1a016e..053d8057ff1e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1216,8 +1216,14 @@ static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, /* Some features have different safe value type in KVM than host features */ switch (id) { case SYS_ID_AA64DFR0_EL1: - if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT) + switch (kvm_ftr.shift) { + case ID_AA64DFR0_EL1_PMUVer_SHIFT: kvm_ftr.type = FTR_LOWER_SAFE; + break; + case ID_AA64DFR0_EL1_DebugVer_SHIFT: + kvm_ftr.type = FTR_LOWER_SAFE; + break; + } break; case SYS_ID_DFR0_EL1: if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) @@ -1469,14 +1475,22 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return val; } +#define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ +({ \ + u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ + (val) &= ~reg##_##field##_MASK; \ + (val) |= FIELD_PREP(reg##_##field##_MASK, \ + min(__f_val, (u64)reg##_##field##_##limit)); \ + (val); \ +}) + static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); /* Limit debug to ARMv8.0 */ - val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; - val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); /* * Only initialize the PMU version if the vCPU was configured with one. @@ -1496,6 +1510,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { + u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); /* @@ -1515,6 +1530,13 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; + /* + * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a + * nonzero minimum safe value. + */ + if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } @@ -1528,6 +1550,8 @@ static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, if (kvm_vcpu_has_pmu(vcpu)) val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); + return val; } @@ -1536,6 +1560,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, u64 val) { u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); + u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { val &= ~ID_DFR0_EL1_PerfMon_MASK; @@ -1551,6 +1576,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) return -EINVAL; + if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } From patchwork Tue Jul 18 16:45:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13317447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB1DEEB64DD for ; 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Tue, 18 Jul 2023 09:45:32 -0700 (PDT) Date: Tue, 18 Jul 2023 16:45:19 +0000 In-Reply-To: <20230718164522.3498236-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230718164522.3498236-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230718164522.3498236-4-jingzhangos@google.com> Subject: [PATCH v6 3/6] KVM: arm64: Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org All valid fields in ID_AA64DFR0_EL1 and ID_DFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 053d8057ff1e..f33aec83f1b4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2008,7 +2008,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .set_user = set_id_dfr0_el1, .visibility = aa32_id_visibility, .reset = read_sanitised_id_dfr0_el1, - .val = ID_DFR0_EL1_PerfMon_MASK, }, + .val = GENMASK(63, 0), }, ID_HIDDEN(ID_AFR0_EL1), AA32_ID_SANITISED(ID_MMFR0_EL1), AA32_ID_SANITISED(ID_MMFR1_EL1), @@ -2057,7 +2057,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, .reset = read_sanitised_id_aa64dfr0_el1, - .val = ID_AA64DFR0_EL1_PMUVer_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), ID_UNALLOCATED(5,3), From patchwork Tue Jul 18 16:45:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13317448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F493EB64DC for ; Tue, 18 Jul 2023 16:45:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232378AbjGRQpi (ORCPT ); Tue, 18 Jul 2023 12:45:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232301AbjGRQpg (ORCPT ); Tue, 18 Jul 2023 12:45:36 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E130810E5 for ; Tue, 18 Jul 2023 09:45:35 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-57704a25be9so84888037b3.1 for ; Tue, 18 Jul 2023 09:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689698735; x=1692290735; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=xS0acJp+aIDXIQPo5QGK2XMol5RfSj1wMM22zpXYALg=; b=mpfM8/gfGz4eL9WsvWX7/rl2c/XEF+3IZBy6xbn2Nm8YaKYfYszCxiqcQih3uvFcoZ CCyHfCbfF0C1cDKbjHnJg8h6J23K7kxuUTtJ2YnOHqiLn+Ru+xLOVynTE8kRKkZysCcj rztMqtpEyQoRu+XppWAh2poZ+EGId/gLbWI42NGF0ShR9KzVER18cTOPFLdxV82tVeld 8Tqw3IFOH65ngjlOZQsGQT/K2L1pjDGDLrTuiyN/8eO4MrfQZbV6aa2KTfrWdTE/B9Z6 ADI4mAL/zN61phUNkQRrWLgdAqJ1xeLa98MzOX4ZMdYlz7aeBdZLgI8tkYazrhZVJ459 atQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689698735; x=1692290735; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xS0acJp+aIDXIQPo5QGK2XMol5RfSj1wMM22zpXYALg=; b=QnvJWzl99mFSF4P6Nf/FHA3N1dl0GEx62CFI0awVODAjf9e0UHRuCctk6Xm/tSRtwK 0QjGERubmiTCD6EU94fsWtn6nPEyVO3FWRFN+BykvpaAvKs+qURHR68WEC3u8CJHdD0S GdPFicUN4C3D/0LvZFzcD/LzwOpE/zGzfq26T2rQN7SgKLgl23Mn4WyeVD7OorlBS9Jy xpSxABtBxC8cDePq6dcsFjsHXdth7tWc4UqxV+VWwmMlOogDlU62fKOSodEU3FBk15dd gDQMOU8tTvTgykhpl+oRChs9BxVJDrTrPVW2O+d0Tl0duM4pK34M365BHmq6PgeKpw/A 6QLQ== X-Gm-Message-State: ABy/qLZypSFLOWDGQhHoMpvQOp6StSZqG2Y/j/oiAKj1Ya1TzASy9qBJ BALWwfVInxbj8IF16KWspuQ8N/e0vezjndtJyIima8/+fz9qXMuN0N4KEHa6Y4XMhj4MaHuGkpl uQO7oCccwmgucT3wb92tdN5b6uhx++R8jb6RI5cH2TmZITCGW+hLDztItnYFjlQsMe06Kh2A= X-Google-Smtp-Source: APBJJlEQmDSoHkGi9JQIAr4wuITHz7fAluVasMRt8k18NTKlsRsIsnD0bdJ4EqDubIUM0oQB7DLI1CT99QjPdZDFHQ== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a81:fe09:0:b0:57a:6019:62aa with SMTP id j9-20020a81fe09000000b0057a601962aamr237002ywn.5.1689698734735; Tue, 18 Jul 2023 09:45:34 -0700 (PDT) Date: Tue, 18 Jul 2023 16:45:20 +0000 In-Reply-To: <20230718164522.3498236-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230718164522.3498236-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230718164522.3498236-5-jingzhangos@google.com> Subject: [PATCH v6 4/6] KVM: arm64: Enable writable for ID_AA64PFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org All valid fields in ID_AA64PFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f33aec83f1b4..12b81ab27dbe 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2042,7 +2042,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_reg, .reset = read_sanitised_id_aa64pfr0_el1, - .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), From patchwork Tue Jul 18 16:45:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13317449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F3AFC001DC for ; Tue, 18 Jul 2023 16:45:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232389AbjGRQpj (ORCPT ); Tue, 18 Jul 2023 12:45:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232371AbjGRQpi (ORCPT ); Tue, 18 Jul 2023 12:45:38 -0400 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3228610D2 for ; Tue, 18 Jul 2023 09:45:37 -0700 (PDT) Received: by mail-pg1-x549.google.com with SMTP id 41be03b00d2f7-55c79a55650so4537599a12.0 for ; Tue, 18 Jul 2023 09:45:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689698736; x=1692290736; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=7vkCbr047ltjyeNSod64c+hA+AaA1LNd8Iy2F1bOfBE=; b=yDDdm3Z98ZL51ezeU3dyZisGjIZSm1scHPakb810LlPtbzZdWtSUIYn/IEOov5bS/a HhyaKTMZfG3GGLqUcOZEO3jWAbeBWbTi5j8vYHEICwvgbi8Qv93SV86ZXZ0R9uRIOEfU tfW4QxvXTLOQmrAp6N5uWwOcYGCQ1yrqQNnUXmzNz4YhAyyA4TJE3vbPvZe52JEjQ19o rSCyDjo7l5I7KgLtNETHDoB9SexVb9joZl0xIE+DtxXUBwwJrN0HrgEesHZL1dS3a3f9 1WXahQMOWqNCdfgQgckue6kJBtPxpTLLOYavVWjQIXyOfD4f5EYp3T1flDKM9NrTNHJg ca5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689698736; x=1692290736; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7vkCbr047ltjyeNSod64c+hA+AaA1LNd8Iy2F1bOfBE=; b=C/JYacIE+dcSg6NtGxzMu5XoEbd2vgQoK1NAHVMDPveSj0GpespHYw/H7q3X4p7a9S DJ3P6J/7WbpanUvlgk/soygkA7VexdEja6U6/PA9yEppCoR1OqqSJYTbK463UuFwfhJt OurzSK+EwVG9pLfcHAl9MdTFDxfR2sa0hvdng/Z72oZPCEVpHQI6qwVwEG8+khK4J06K hDTe+nYzjlXDz0KMeUPFXJQRtvzI+QxTu/BtlQdG2IMkJ6OZ74T1zN6jjhY5WzF1z8pi mRFatYU5GmNe17ANXGBR/dipKLc8NtwGQQzMopBwTIc9ZOK9Mf/sWYgMwf2AyHtv6P9V B6Vw== X-Gm-Message-State: ABy/qLalGZaJUIu+vy2FpnNbsWVN8KAH01n6ACx1kcgZYZq6yvK7vqmc Ky7jwZAfAofyKxV/ykHeCfVor+idT9jN14XO2zZN35G+GVlA890YyEznYAS757OfzOrPTzrIDan pOOxHpDHM/HWttb+I+n2kGiTPoS6dyaD64lvh/MCUZEU0BDKSzQelOZG+zUrNquYux6ouFd0= X-Google-Smtp-Source: APBJJlHDDu+HxPs3scZlNF4+YoM4eumiXMxf7JemKCB4eK0aLPYXrlzf6mMhZxkgAMPgiQBQLnY7YjFAQ4oSoy0Zbw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a05:6a00:158e:b0:677:c9da:14b6 with SMTP id u14-20020a056a00158e00b00677c9da14b6mr159486pfk.4.1689698736287; Tue, 18 Jul 2023 09:45:36 -0700 (PDT) Date: Tue, 18 Jul 2023 16:45:21 +0000 In-Reply-To: <20230718164522.3498236-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230718164522.3498236-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230718164522.3498236-6-jingzhangos@google.com> Subject: [PATCH v6 5/6] KVM: arm64: Enable writable for ID_AA64MMFR{0, 1, 2, 3}_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Enable writable from userspace for ID_AA64MMFR{0, 1, 2, 3}_EL1. Added a macro for defining general writable idregs. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 12b81ab27dbe..d560fc178a76 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1346,9 +1346,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS); break; - case SYS_ID_AA64MMFR2_EL1: - val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; - break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -1582,6 +1579,18 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, return set_id_reg(vcpu, rd, val); } +static u64 read_sanitised_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + u64 val; + u32 id = reg_to_encoding(rd); + + val = read_sanitised_ftr_reg(id); + val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; + + return val; +} + /* * cpufeature ID register user accessors * @@ -1856,6 +1865,16 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, .val = 0, \ } +#define ID_SANITISED_WRITABLE(name) { \ + SYS_DESC(SYS_##name), \ + .access = access_id_reg, \ + .get_user = get_id_reg, \ + .set_user = set_id_reg, \ + .visibility = id_visibility, \ + .reset = kvm_read_sanitised_id_reg, \ + .val = GENMASK(63, 0), \ +} + /* sys_reg_desc initialiser for known cpufeature ID registers */ #define AA32_ID_SANITISED(name) { \ SYS_DESC(SYS_##name), \ @@ -2077,10 +2096,15 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(6,7), /* CRm=7 */ - ID_SANITISED(ID_AA64MMFR0_EL1), - ID_SANITISED(ID_AA64MMFR1_EL1), - ID_SANITISED(ID_AA64MMFR2_EL1), - ID_SANITISED(ID_AA64MMFR3_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR0_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR1_EL1), + { SYS_DESC(SYS_ID_AA64MMFR2_EL1), + .access = access_id_reg, + .get_user = get_id_reg, + .set_user = set_id_reg, + .reset = read_sanitised_id_aa64mmfr2_el1, + .val = GENMASK(63, 0), }, + ID_SANITISED_WRITABLE(ID_AA64MMFR3_EL1), ID_UNALLOCATED(7,4), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6), From patchwork Tue Jul 18 16:45:22 2023 Content-Type: text/plain; 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Tue, 18 Jul 2023 09:45:38 -0700 (PDT) Date: Tue, 18 Jul 2023 16:45:22 +0000 In-Reply-To: <20230718164522.3498236-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230718164522.3498236-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230718164522.3498236-7-jingzhangos@google.com> Subject: [PATCH v6 6/6] KVM: arm64: selftests: Test for setting ID register from usersapce From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a test to verify setting ID registers from userapce is handled correctly by KVM. Signed-off-by: Jing Zhang --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/aarch64/set_id_regs.c | 163 ++++++++++++++++++ 2 files changed, 164 insertions(+) create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index c692cc86e7da..87ceadc1292a 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -144,6 +144,7 @@ TEST_GEN_PROGS_aarch64 += aarch64/get-reg-list TEST_GEN_PROGS_aarch64 += aarch64/hypercalls TEST_GEN_PROGS_aarch64 += aarch64/page_fault_test TEST_GEN_PROGS_aarch64 += aarch64/psci_test +TEST_GEN_PROGS_aarch64 += aarch64/set_id_regs TEST_GEN_PROGS_aarch64 += aarch64/smccc_filter TEST_GEN_PROGS_aarch64 += aarch64/vcpu_width_config TEST_GEN_PROGS_aarch64 += aarch64/vgic_init diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c new file mode 100644 index 000000000000..e2242ef36bab --- /dev/null +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * set_id_regs - Test for setting ID register from usersapce. + * + * Copyright (c) 2023 Google LLC. + * + * + * Test that KVM supports setting ID registers from userspace and handles the + * feature set correctly. + */ + +#include +#include "kvm_util.h" +#include "processor.h" +#include "test_util.h" +#include + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +struct reg_feature { + uint64_t reg; + uint64_t ftr_mask; +}; + +static void guest_code(void) +{ + for (;;) + GUEST_SYNC(0); +} + +static struct reg_feature lower_safe_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS) }, + { KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1), ARM64_FEATURE_MASK(ID_DFR0_COPDBG) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), ARM64_FEATURE_MASK(ID_AA64PFR0_EL3) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN4) }, +}; + +static void test_user_set_lower_safe(struct kvm_vcpu *vcpu) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lower_safe_reg_ftrs); i++) { + struct reg_feature *reg_ftr = lower_safe_reg_ftrs + i; + uint64_t val, new_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + + /* Set a safe value for the feature */ + if (ftr > 0) + ftr--; + + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + + vcpu_set_reg(vcpu, reg_ftr->reg, val); + vcpu_get_reg(vcpu, reg_ftr->reg, &new_val); + ASSERT_EQ(new_val, val); + } +} + +static struct reg_feature exact_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER) }, +}; + +static void test_user_set_exact(struct kvm_vcpu *vcpu) +{ + int i, r; + + for (i = 0; i < ARRAY_SIZE(exact_reg_ftrs); i++) { + struct reg_feature *reg_ftr = exact_reg_ftrs + i; + uint64_t val, old_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + old_val = val; + + /* Exact match */ + vcpu_set_reg(vcpu, reg_ftr->reg, val); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + + /* Smaller value */ + if (ftr > 0) + ftr--; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + + /* Bigger value */ + ftr += 2; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + } +} + +static struct reg_feature fail_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS) }, + { KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1), ARM64_FEATURE_MASK(ID_DFR0_MPROFDBG) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), ARM64_FEATURE_MASK(ID_AA64PFR0_EL2) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN64) }, +}; + +static void test_user_set_fail(struct kvm_vcpu *vcpu) +{ + int i, r; + + for (i = 0; i < ARRAY_SIZE(fail_reg_ftrs); i++) { + struct reg_feature *reg_ftr = fail_reg_ftrs + i; + uint64_t val, old_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + + /* Set a invalid value (too big) for the feature */ + ftr++; + + old_val = val; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + } +} + +int main(void) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + + ksft_print_header(); + ksft_set_plan(3); + + test_user_set_lower_safe(vcpu); + ksft_test_result_pass("test_user_set_lower_safe\n"); + + test_user_set_exact(vcpu); + ksft_test_result_pass("test_user_set_exact\n"); + + test_user_set_fail(vcpu); + ksft_test_result_pass("test_user_set_fail\n"); + + kvm_vm_free(vm); + + ksft_finished(); +}