From patchwork Fri Jul 21 01:29:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Ying" X-Patchwork-Id: 13321225 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC379363 for ; Fri, 21 Jul 2023 01:45:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689903909; x=1721439909; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oyCI5HLzYg6B8dSBk9eHwDqLZtZfH++WogxlpW3EVlc=; b=hYrzwCZc++J66V74kF1EeCIuDYRMacBixXqxGr++AKCnk+uUxvuIKrw7 7Y1Vz+YpKO4fJM9lTMxdNgaPl1AM4+t4uM7/C/SGJn5IoU4NzWyYXPIGp OdFq1+bvE4EAzYMPk4QC3FfB+sfxsmtp9D2Y28Aj/jHnfhMAWl+IwbiMG 5q++hKwhMOjUqjitfRbeIfuk3Q7uhLzOvpbG0Illl706u8Op7cFSkcI6r pR1ZOJb4aMu6a1iOygZnsEIYS5ZPipZsOYsFZARU9hrjHaS7vBDipXFFG dWuxJ45Ck6pw0EtriOFJD8wgVtu3qLzvVgo5jOEUYp+JeG9MsAcp8JVhx Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="347214147" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="347214147" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 18:45:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="724670918" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="724670918" Received: from yanfeng1-mobl.ccr.corp.intel.com (HELO yhuang6-mobl2.ccr.corp.intel.com) ([10.255.29.24]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 18:45:04 -0700 From: Huang Ying To: Andrew Morton Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev, linux-acpi@vger.kernel.org, Huang Ying , "Aneesh Kumar K . V" , Wei Xu , Alistair Popple , Dan Williams , Dave Hansen , Davidlohr Bueso , Johannes Weiner , Jonathan Cameron , Michal Hocko , Yang Shi , Rafael J Wysocki Subject: [PATCH RESEND 1/4] memory tiering: add abstract distance calculation algorithms management Date: Fri, 21 Jul 2023 09:29:29 +0800 Message-Id: <20230721012932.190742-2-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230721012932.190742-1-ying.huang@intel.com> References: <20230721012932.190742-1-ying.huang@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The abstract distance may be calculated by various drivers, such as ACPI HMAT, CXL CDAT, etc. While it may be used by various code which hot-add memory node, such as dax/kmem etc. To decouple the algorithm users and the providers, the abstract distance calculation algorithms management mechanism is implemented in this patch. It provides interface for the providers to register the implementation, and interface for the users. Multiple algorithm implementations can cooperate via calculating abstract distance for different memory nodes. The preference of algorithm implementations can be specified via priority (notifier_block.priority). Signed-off-by: "Huang, Ying" Cc: Aneesh Kumar K.V Cc: Wei Xu Cc: Alistair Popple Cc: Dan Williams Cc: Dave Hansen Cc: Davidlohr Bueso Cc: Johannes Weiner Cc: Jonathan Cameron Cc: Michal Hocko Cc: Yang Shi Cc: Rafael J Wysocki --- include/linux/memory-tiers.h | 19 ++++++++++++ mm/memory-tiers.c | 59 ++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h index fc9647b1b4f9..c6429e624244 100644 --- a/include/linux/memory-tiers.h +++ b/include/linux/memory-tiers.h @@ -6,6 +6,7 @@ #include #include #include +#include /* * Each tier cover a abstrace distance chunk size of 128 */ @@ -36,6 +37,9 @@ struct memory_dev_type *alloc_memory_type(int adistance); void destroy_memory_type(struct memory_dev_type *memtype); void init_node_memory_type(int node, struct memory_dev_type *default_type); void clear_node_memory_type(int node, struct memory_dev_type *memtype); +int register_mt_adistance_algorithm(struct notifier_block *nb); +int unregister_mt_adistance_algorithm(struct notifier_block *nb); +int mt_calc_adistance(int node, int *adist); #ifdef CONFIG_MIGRATION int next_demotion_node(int node); void node_get_allowed_targets(pg_data_t *pgdat, nodemask_t *targets); @@ -97,5 +101,20 @@ static inline bool node_is_toptier(int node) { return true; } + +static inline int register_mt_adistance_algorithm(struct notifier_block *nb) +{ + return 0; +} + +static inline int unregister_mt_adistance_algorithm(struct notifier_block *nb) +{ + return 0; +} + +static inline int mt_calc_adistance(int node, int *adist) +{ + return NOTIFY_DONE; +} #endif /* CONFIG_NUMA */ #endif /* _LINUX_MEMORY_TIERS_H */ diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c index a516e303e304..1e55fbe2ad51 100644 --- a/mm/memory-tiers.c +++ b/mm/memory-tiers.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "internal.h" @@ -105,6 +106,8 @@ static int top_tier_adistance; static struct demotion_nodes *node_demotion __read_mostly; #endif /* CONFIG_MIGRATION */ +static BLOCKING_NOTIFIER_HEAD(mt_adistance_algorithms); + static inline struct memory_tier *to_memory_tier(struct device *device) { return container_of(device, struct memory_tier, dev); @@ -592,6 +595,62 @@ void clear_node_memory_type(int node, struct memory_dev_type *memtype) } EXPORT_SYMBOL_GPL(clear_node_memory_type); +/** + * register_mt_adistance_algorithm() - Register memory tiering abstract distance algorithm + * @nb: The notifier block which describe the algorithm + * + * Return: 0 on success, errno on error. + * + * Every memory tiering abstract distance algorithm provider needs to + * register the algorithm with register_mt_adistance_algorithm(). To + * calculate the abstract distance for a specified memory node, the + * notifier function will be called unless some high priority + * algorithm has provided result. The prototype of the notifier + * function is as follows, + * + * int (*algorithm_notifier)(struct notifier_block *nb, + * unsigned long nid, void *data); + * + * Where "nid" specifies the memory node, "data" is the pointer to the + * returned abstract distance (that is, "int *adist"). If the + * algorithm provides the result, NOTIFY_STOP should be returned. + * Otherwise, return_value & %NOTIFY_STOP_MASK == 0 to allow the next + * algorithm in the chain to provide the result. + */ +int register_mt_adistance_algorithm(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&mt_adistance_algorithms, nb); +} +EXPORT_SYMBOL_GPL(register_mt_adistance_algorithm); + +/** + * unregister_mt_adistance_algorithm() - Unregister memory tiering abstract distance algorithm + * @nb: the notifier block which describe the algorithm + * + * Return: 0 on success, errno on error. + */ +int unregister_mt_adistance_algorithm(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&mt_adistance_algorithms, nb); +} +EXPORT_SYMBOL_GPL(unregister_mt_adistance_algorithm); + +/** + * mt_calc_adistance() - Calculate abstract distance with registered algorithms + * @node: the node to calculate abstract distance for + * @adist: the returned abstract distance + * + * Return: if return_value & %NOTIFY_STOP_MASK != 0, then some + * abstract distance algorithm provides the result, and return it via + * @adist. Otherwise, no algorithm can provide the result and @adist + * will be kept as it is. + */ +int mt_calc_adistance(int node, int *adist) +{ + return blocking_notifier_call_chain(&mt_adistance_algorithms, node, adist); +} +EXPORT_SYMBOL_GPL(mt_calc_adistance); + static int __meminit memtier_hotplug_callback(struct notifier_block *self, unsigned long action, void *_arg) { From patchwork Fri Jul 21 01:29:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Ying" X-Patchwork-Id: 13321226 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACD87363 for ; Fri, 21 Jul 2023 01:45:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689903914; x=1721439914; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3Hn5VMwJGt0IXFlVjJsaiQl5L2c0xHT5vclGupSQt0Q=; b=TQXd1ZqZDLzUQXPw3TZu3qOkP1u37gaqktw9UvEIaB22WKgfJeucQnrN NWoaNlo/WnrZbmfwXCsUuAj+H015gxX7grLAK+92Il1fUkeA3PFWx5FKl n8+4v4iSOd2F3z9j7MUXLsj99ShCyJ9Bn9YmfnBfNXL9CXMqJECUTWwW8 Y10NxcspUBDSqvsFZHdBg/Ggq2pjpcLVmoESEEZ9amtY/aps8qN+IPUJM ZXx3vtuxPpXmC11ovOc5HgXE9V2prKQIH+5mHcwVrY2WEDj8sMTAzUSGl sp6wreSPIFLyowdz5lY0ua1Ok86k+UOtkKwl2FWRxP2+klbGEEVYWX0US g==; X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="347214171" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="347214171" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 18:45:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="724671020" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="724671020" Received: from yanfeng1-mobl.ccr.corp.intel.com (HELO yhuang6-mobl2.ccr.corp.intel.com) ([10.255.29.24]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 18:45:09 -0700 From: Huang Ying To: Andrew Morton Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev, linux-acpi@vger.kernel.org, Huang Ying , "Aneesh Kumar K . V" , Wei Xu , Alistair Popple , Dan Williams , Dave Hansen , Davidlohr Bueso , Johannes Weiner , Jonathan Cameron , Michal Hocko , Yang Shi , Rafael J Wysocki Subject: [PATCH RESEND 2/4] acpi, hmat: refactor hmat_register_target_initiators() Date: Fri, 21 Jul 2023 09:29:30 +0800 Message-Id: <20230721012932.190742-3-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230721012932.190742-1-ying.huang@intel.com> References: <20230721012932.190742-1-ying.huang@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Previously, in hmat_register_target_initiators(), the performance attributes are calculated and the corresponding sysfs links and files are created too. Which is called during memory onlining. But now, to calculate the abstract distance of a memory target before memory onlining, we need to calculate the performance attributes for a memory target without creating sysfs links and files. To do that, hmat_register_target_initiators() is refactored to make it possible to calculate performance attributes separately. Signed-off-by: "Huang, Ying" Cc: Aneesh Kumar K.V Cc: Wei Xu Cc: Alistair Popple Cc: Dan Williams Cc: Dave Hansen Cc: Davidlohr Bueso Cc: Johannes Weiner Cc: Jonathan Cameron Cc: Michal Hocko Cc: Yang Shi Cc: Rafael J Wysocki Reviewed-by: Alistair Popple Tested-by: Alistair Popple --- drivers/acpi/numa/hmat.c | 81 +++++++++++++++------------------------- 1 file changed, 30 insertions(+), 51 deletions(-) diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index bba268ecd802..2dee0098f1a9 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -582,28 +582,25 @@ static int initiators_to_nodemask(unsigned long *p_nodes) return 0; } -static void hmat_register_target_initiators(struct memory_target *target) +static void hmat_update_target_attrs(struct memory_target *target, + unsigned long *p_nodes, int access) { - static DECLARE_BITMAP(p_nodes, MAX_NUMNODES); struct memory_initiator *initiator; - unsigned int mem_nid, cpu_nid; + unsigned int cpu_nid; struct memory_locality *loc = NULL; u32 best = 0; - bool access0done = false; int i; - mem_nid = pxm_to_node(target->memory_pxm); + bitmap_zero(p_nodes, MAX_NUMNODES); /* - * If the Address Range Structure provides a local processor pxm, link + * If the Address Range Structure provides a local processor pxm, set * only that one. Otherwise, find the best performance attributes and - * register all initiators that match. + * collect all initiators that match. */ if (target->processor_pxm != PXM_INVAL) { cpu_nid = pxm_to_node(target->processor_pxm); - register_memory_node_under_compute_node(mem_nid, cpu_nid, 0); - access0done = true; - if (node_state(cpu_nid, N_CPU)) { - register_memory_node_under_compute_node(mem_nid, cpu_nid, 1); + if (access == 0 || node_state(cpu_nid, N_CPU)) { + set_bit(target->processor_pxm, p_nodes); return; } } @@ -617,47 +614,10 @@ static void hmat_register_target_initiators(struct memory_target *target) * We'll also use the sorting to prime the candidate nodes with known * initiators. */ - bitmap_zero(p_nodes, MAX_NUMNODES); list_sort(NULL, &initiators, initiator_cmp); if (initiators_to_nodemask(p_nodes) < 0) return; - if (!access0done) { - for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) { - loc = localities_types[i]; - if (!loc) - continue; - - best = 0; - list_for_each_entry(initiator, &initiators, node) { - u32 value; - - if (!test_bit(initiator->processor_pxm, p_nodes)) - continue; - - value = hmat_initiator_perf(target, initiator, - loc->hmat_loc); - if (hmat_update_best(loc->hmat_loc->data_type, value, &best)) - bitmap_clear(p_nodes, 0, initiator->processor_pxm); - if (value != best) - clear_bit(initiator->processor_pxm, p_nodes); - } - if (best) - hmat_update_target_access(target, loc->hmat_loc->data_type, - best, 0); - } - - for_each_set_bit(i, p_nodes, MAX_NUMNODES) { - cpu_nid = pxm_to_node(i); - register_memory_node_under_compute_node(mem_nid, cpu_nid, 0); - } - } - - /* Access 1 ignores Generic Initiators */ - bitmap_zero(p_nodes, MAX_NUMNODES); - if (initiators_to_nodemask(p_nodes) < 0) - return; - for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) { loc = localities_types[i]; if (!loc) @@ -667,7 +627,7 @@ static void hmat_register_target_initiators(struct memory_target *target) list_for_each_entry(initiator, &initiators, node) { u32 value; - if (!initiator->has_cpu) { + if (access == 1 && !initiator->has_cpu) { clear_bit(initiator->processor_pxm, p_nodes); continue; } @@ -681,14 +641,33 @@ static void hmat_register_target_initiators(struct memory_target *target) clear_bit(initiator->processor_pxm, p_nodes); } if (best) - hmat_update_target_access(target, loc->hmat_loc->data_type, best, 1); + hmat_update_target_access(target, loc->hmat_loc->data_type, best, access); } +} + +static void __hmat_register_target_initiators(struct memory_target *target, + unsigned long *p_nodes, + int access) +{ + unsigned int mem_nid, cpu_nid; + int i; + + mem_nid = pxm_to_node(target->memory_pxm); + hmat_update_target_attrs(target, p_nodes, access); for_each_set_bit(i, p_nodes, MAX_NUMNODES) { cpu_nid = pxm_to_node(i); - register_memory_node_under_compute_node(mem_nid, cpu_nid, 1); + register_memory_node_under_compute_node(mem_nid, cpu_nid, access); } } +static void hmat_register_target_initiators(struct memory_target *target) +{ + static DECLARE_BITMAP(p_nodes, MAX_NUMNODES); + + __hmat_register_target_initiators(target, p_nodes, 0); + __hmat_register_target_initiators(target, p_nodes, 1); +} + static void hmat_register_target_cache(struct memory_target *target) { unsigned mem_nid = pxm_to_node(target->memory_pxm); From patchwork Fri Jul 21 01:29:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Ying" X-Patchwork-Id: 13321227 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF463363 for ; Fri, 21 Jul 2023 01:45:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689903921; x=1721439921; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fvluWJnQxPJxRNFSQvnsXlILnnh9VajCo65nakKALGw=; b=BkoIgn06qYdFbabVQEbcj9ozXAlMpp3TO7hNZD/DqbCIWLsStD7144Sp PAb86j7xqCUFSEgVW9uvWmZF2HTVoCsl2r2bZDGB1lyGOjd+WEWOzJUMl YSAuQsAnrhxhgeGt2WpcVxE/29MwRwmDoss3VzFLaa4sVcpQEUwdm1n7V 5yoifHmxV1eI9/FtFHfCpPj5TRl9CV9zCWgNUWDy927Hxh3aCpRapmfoe KG3RY3hEaB9j1KJC4ArZttKLKwM/1L/duOf0YJcS0/4wwDznwmscu+fvR YPmy3xkJUI700bSpKb6j1vEq3tY9uo9FcPpAjzsoRXBiSfRFVmmwxq04Y Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="347214195" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="347214195" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 18:45:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="724671128" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="724671128" Received: from yanfeng1-mobl.ccr.corp.intel.com (HELO yhuang6-mobl2.ccr.corp.intel.com) ([10.255.29.24]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 18:45:14 -0700 From: Huang Ying To: Andrew Morton Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev, linux-acpi@vger.kernel.org, Huang Ying , "Aneesh Kumar K . V" , Wei Xu , Alistair Popple , Dan Williams , Dave Hansen , Davidlohr Bueso , Johannes Weiner , Jonathan Cameron , Michal Hocko , Yang Shi , Rafael J Wysocki Subject: [PATCH RESEND 3/4] acpi, hmat: calculate abstract distance with HMAT Date: Fri, 21 Jul 2023 09:29:31 +0800 Message-Id: <20230721012932.190742-4-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230721012932.190742-1-ying.huang@intel.com> References: <20230721012932.190742-1-ying.huang@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A memory tiering abstract distance calculation algorithm based on ACPI HMAT is implemented. The basic idea is as follows. The performance attributes of system default DRAM nodes are recorded as the base line. Whose abstract distance is MEMTIER_ADISTANCE_DRAM. Then, the ratio of the abstract distance of a memory node (target) to MEMTIER_ADISTANCE_DRAM is scaled based on the ratio of the performance attributes of the node to that of the default DRAM nodes. Signed-off-by: "Huang, Ying" Cc: Aneesh Kumar K.V Cc: Wei Xu Cc: Alistair Popple Cc: Dan Williams Cc: Dave Hansen Cc: Davidlohr Bueso Cc: Johannes Weiner Cc: Jonathan Cameron Cc: Michal Hocko Cc: Yang Shi Cc: Rafael J Wysocki --- drivers/acpi/numa/hmat.c | 138 ++++++++++++++++++++++++++++++++++- include/linux/memory-tiers.h | 2 + mm/memory-tiers.c | 2 +- 3 files changed, 140 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index 2dee0098f1a9..306a912090f0 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -24,6 +24,7 @@ #include #include #include +#include static u8 hmat_revision; static int hmat_disable __initdata; @@ -759,6 +760,137 @@ static int hmat_callback(struct notifier_block *self, return NOTIFY_OK; } +static int hmat_adistance_disabled; +static struct node_hmem_attrs default_dram_attrs; + +static void dump_hmem_attrs(struct node_hmem_attrs *attrs) +{ + pr_cont("read_latency: %u, write_latency: %u, read_bandwidth: %u, write_bandwidth: %u\n", + attrs->read_latency, attrs->write_latency, + attrs->read_bandwidth, attrs->write_bandwidth); +} + +static void disable_hmat_adistance_algorithm(void) +{ + hmat_adistance_disabled = true; +} + +static int hmat_init_default_dram_attrs(void) +{ + struct memory_target *target; + struct node_hmem_attrs *attrs; + int nid, pxm; + int nid_dram = NUMA_NO_NODE; + + if (default_dram_attrs.read_latency + + default_dram_attrs.write_latency != 0) + return 0; + + if (!default_dram_type) + return -EIO; + + for_each_node_mask(nid, default_dram_type->nodes) { + pxm = node_to_pxm(nid); + target = find_mem_target(pxm); + if (!target) + continue; + attrs = &target->hmem_attrs[1]; + if (nid_dram == NUMA_NO_NODE) { + if (attrs->read_latency + attrs->write_latency == 0 || + attrs->read_bandwidth + attrs->write_bandwidth == 0) { + pr_info("hmat: invalid hmem attrs for default DRAM node: %d,\n", + nid); + pr_info(" "); + dump_hmem_attrs(attrs); + pr_info(" disable hmat based abstract distance algorithm.\n"); + disable_hmat_adistance_algorithm(); + return -EIO; + } + nid_dram = nid; + default_dram_attrs = *attrs; + continue; + } + + /* + * The performance of all default DRAM nodes is expected + * to be same (that is, the variation is less than 10%). + * And it will be used as base to calculate the abstract + * distance of other memory nodes. + */ + if (abs(attrs->read_latency - default_dram_attrs.read_latency) * 10 > + default_dram_attrs.read_latency || + abs(attrs->write_latency - default_dram_attrs.write_latency) * 10 > + default_dram_attrs.write_latency || + abs(attrs->read_bandwidth - default_dram_attrs.read_bandwidth) * 10 > + default_dram_attrs.read_bandwidth) { + pr_info("hmat: hmem attrs for DRAM nodes mismatch.\n"); + pr_info(" node %d:", nid_dram); + dump_hmem_attrs(&default_dram_attrs); + pr_info(" node %d:", nid); + dump_hmem_attrs(attrs); + pr_info(" disable hmat based abstract distance algorithm.\n"); + disable_hmat_adistance_algorithm(); + return -EIO; + } + } + + return 0; +} + +static int hmat_calculate_adistance(struct notifier_block *self, + unsigned long nid, void *data) +{ + static DECLARE_BITMAP(p_nodes, MAX_NUMNODES); + struct memory_target *target; + struct node_hmem_attrs *attrs; + int *adist = data; + int pxm; + + if (hmat_adistance_disabled) + return NOTIFY_OK; + + pxm = node_to_pxm(nid); + target = find_mem_target(pxm); + if (!target) + return NOTIFY_OK; + + if (hmat_init_default_dram_attrs()) + return NOTIFY_OK; + + mutex_lock(&target_lock); + hmat_update_target_attrs(target, p_nodes, 1); + mutex_unlock(&target_lock); + + attrs = &target->hmem_attrs[1]; + + if (attrs->read_latency + attrs->write_latency == 0 || + attrs->read_bandwidth + attrs->write_bandwidth == 0) + return NOTIFY_OK; + + /* + * The abstract distance of a memory node is in direct + * proportion to its memory latency (read + write) and + * inversely proportional to its memory bandwidth (read + + * write). The abstract distance, memory latency, and memory + * bandwidth of the default DRAM nodes are used as the base. + */ + *adist = MEMTIER_ADISTANCE_DRAM * + (attrs->read_latency + attrs->write_latency) / + (default_dram_attrs.read_latency + + default_dram_attrs.write_latency) * + (default_dram_attrs.read_bandwidth + + default_dram_attrs.write_bandwidth) / + (attrs->read_bandwidth + attrs->write_bandwidth); + + return NOTIFY_STOP; +} + +static __meminitdata struct notifier_block hmat_adist_nb = +{ + .notifier_call = hmat_calculate_adistance, + .priority = 100, +}; + static __init void hmat_free_structures(void) { struct memory_target *target, *tnext; @@ -801,6 +933,7 @@ static __init int hmat_init(void) struct acpi_table_header *tbl; enum acpi_hmat_type i; acpi_status status; + int usage; if (srat_disabled() || hmat_disable) return 0; @@ -841,8 +974,11 @@ static __init int hmat_init(void) hmat_register_targets(); /* Keep the table and structures if the notifier may use them */ - if (!hotplug_memory_notifier(hmat_callback, HMAT_CALLBACK_PRI)) + usage = !hotplug_memory_notifier(hmat_callback, HMAT_CALLBACK_PRI); + usage += !register_mt_adistance_algorithm(&hmat_adist_nb); + if (usage) return 0; + out_put: hmat_free_structures(); acpi_put_table(tbl); diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h index c6429e624244..9377239c8d34 100644 --- a/include/linux/memory-tiers.h +++ b/include/linux/memory-tiers.h @@ -33,6 +33,7 @@ struct memory_dev_type { #ifdef CONFIG_NUMA extern bool numa_demotion_enabled; +extern struct memory_dev_type *default_dram_type; struct memory_dev_type *alloc_memory_type(int adistance); void destroy_memory_type(struct memory_dev_type *memtype); void init_node_memory_type(int node, struct memory_dev_type *default_type); @@ -64,6 +65,7 @@ static inline bool node_is_toptier(int node) #else #define numa_demotion_enabled false +#define default_dram_type NULL /* * CONFIG_NUMA implementation returns non NULL error. */ diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c index 1e55fbe2ad51..9a734ef2edfb 100644 --- a/mm/memory-tiers.c +++ b/mm/memory-tiers.c @@ -37,7 +37,7 @@ struct node_memory_type_map { static DEFINE_MUTEX(memory_tier_lock); static LIST_HEAD(memory_tiers); static struct node_memory_type_map node_memory_types[MAX_NUMNODES]; -static struct memory_dev_type *default_dram_type; +struct memory_dev_type *default_dram_type; static struct bus_type memory_tier_subsys = { .name = "memory_tiering", From patchwork Fri Jul 21 01:29:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Ying" X-Patchwork-Id: 13321228 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB11E363 for ; Fri, 21 Jul 2023 01:45:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689903925; x=1721439925; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WgH5xLOkBW2Y/oZqJhHhP4ppJv8kSHk1fii5X3wpokk=; b=WNVErJpj3YN0pcLnn6tk2EyAdJbLs9Kys8Py9kBCXQBS5TGcd7EHoFHv 1Y2E4vp6qjbs8c29Z4nnroDnVpnbPyqdG77I719TmKdgeTrdD30S4vQZp 0OC29zarG8fTP0DLPBAfsXVcX4Mt70kMEoMLA1iJvIt5b4RnmkkRM7KAA 4P6e5NCUJI4pPmjXh10DWtiXL+7IRSWXrCYHrlD+3Ys52d8FzhVZWd+oU Ldve3DJHZkNC90sLOU0QZsjN6MpLw6S4f1QzEhhAXvdnPcbC0OYISgUuE xvCYMDFGmmOKH45kMaU1NNakuhWv9TFN1c05V8byWhf3t9WpS4zlsRtU3 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="347214213" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="347214213" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 18:45:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="724671167" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="724671167" Received: from yanfeng1-mobl.ccr.corp.intel.com (HELO yhuang6-mobl2.ccr.corp.intel.com) ([10.255.29.24]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 18:45:20 -0700 From: Huang Ying To: Andrew Morton Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev, linux-acpi@vger.kernel.org, Huang Ying , "Aneesh Kumar K . V" , Wei Xu , Alistair Popple , Dan Williams , Dave Hansen , Davidlohr Bueso , Johannes Weiner , Jonathan Cameron , Michal Hocko , Yang Shi , Rafael J Wysocki Subject: [PATCH RESEND 4/4] dax, kmem: calculate abstract distance with general interface Date: Fri, 21 Jul 2023 09:29:32 +0800 Message-Id: <20230721012932.190742-5-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230721012932.190742-1-ying.huang@intel.com> References: <20230721012932.190742-1-ying.huang@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Previously, a fixed abstract distance MEMTIER_DEFAULT_DAX_ADISTANCE is used for slow memory type in kmem driver. This limits the usage of kmem driver, for example, it cannot be used for HBM (high bandwidth memory). So, we use the general abstract distance calculation mechanism in kmem drivers to get more accurate abstract distance on systems with proper support. The original MEMTIER_DEFAULT_DAX_ADISTANCE is used as fallback only. Now, multiple memory types may be managed by kmem. These memory types are put into the "kmem_memory_types" list and protected by kmem_memory_type_lock. Signed-off-by: "Huang, Ying" Cc: Aneesh Kumar K.V Cc: Wei Xu Cc: Alistair Popple Cc: Dan Williams Cc: Dave Hansen Cc: Davidlohr Bueso Cc: Johannes Weiner Cc: Jonathan Cameron Cc: Michal Hocko Cc: Yang Shi Cc: Rafael J Wysocki --- drivers/dax/kmem.c | 54 +++++++++++++++++++++++++++--------- include/linux/memory-tiers.h | 2 ++ mm/memory-tiers.c | 2 +- 3 files changed, 44 insertions(+), 14 deletions(-) diff --git a/drivers/dax/kmem.c b/drivers/dax/kmem.c index 898ca9505754..837165037231 100644 --- a/drivers/dax/kmem.c +++ b/drivers/dax/kmem.c @@ -49,14 +49,40 @@ struct dax_kmem_data { struct resource *res[]; }; -static struct memory_dev_type *dax_slowmem_type; +static DEFINE_MUTEX(kmem_memory_type_lock); +static LIST_HEAD(kmem_memory_types); + +static struct memory_dev_type *kmem_find_alloc_memorty_type(int adist) +{ + bool found = false; + struct memory_dev_type *mtype; + + mutex_lock(&kmem_memory_type_lock); + list_for_each_entry(mtype, &kmem_memory_types, list) { + if (mtype->adistance == adist) { + found = true; + break; + } + } + if (!found) { + mtype = alloc_memory_type(adist); + if (!IS_ERR(mtype)) + list_add(&mtype->list, &kmem_memory_types); + } + mutex_unlock(&kmem_memory_type_lock); + + return mtype; +} + static int dev_dax_kmem_probe(struct dev_dax *dev_dax) { struct device *dev = &dev_dax->dev; unsigned long total_len = 0; struct dax_kmem_data *data; + struct memory_dev_type *mtype; int i, rc, mapped = 0; int numa_node; + int adist = MEMTIER_DEFAULT_DAX_ADISTANCE; /* * Ensure good NUMA information for the persistent memory. @@ -71,6 +97,11 @@ static int dev_dax_kmem_probe(struct dev_dax *dev_dax) return -EINVAL; } + mt_calc_adistance(numa_node, &adist); + mtype = kmem_find_alloc_memorty_type(adist); + if (IS_ERR(mtype)) + return PTR_ERR(mtype); + for (i = 0; i < dev_dax->nr_range; i++) { struct range range; @@ -88,7 +119,7 @@ static int dev_dax_kmem_probe(struct dev_dax *dev_dax) return -EINVAL; } - init_node_memory_type(numa_node, dax_slowmem_type); + init_node_memory_type(numa_node, mtype); rc = -ENOMEM; data = kzalloc(struct_size(data, res, dev_dax->nr_range), GFP_KERNEL); @@ -167,7 +198,7 @@ static int dev_dax_kmem_probe(struct dev_dax *dev_dax) err_res_name: kfree(data); err_dax_kmem_data: - clear_node_memory_type(numa_node, dax_slowmem_type); + clear_node_memory_type(numa_node, mtype); return rc; } @@ -219,7 +250,7 @@ static void dev_dax_kmem_remove(struct dev_dax *dev_dax) * for that. This implies this reference will be around * till next reboot. */ - clear_node_memory_type(node, dax_slowmem_type); + clear_node_memory_type(node, NULL); } } #else @@ -251,12 +282,6 @@ static int __init dax_kmem_init(void) if (!kmem_name) return -ENOMEM; - dax_slowmem_type = alloc_memory_type(MEMTIER_DEFAULT_DAX_ADISTANCE); - if (IS_ERR(dax_slowmem_type)) { - rc = PTR_ERR(dax_slowmem_type); - goto err_dax_slowmem_type; - } - rc = dax_driver_register(&device_dax_kmem_driver); if (rc) goto error_dax_driver; @@ -264,18 +289,21 @@ static int __init dax_kmem_init(void) return rc; error_dax_driver: - destroy_memory_type(dax_slowmem_type); -err_dax_slowmem_type: kfree_const(kmem_name); return rc; } static void __exit dax_kmem_exit(void) { + struct memory_dev_type *mtype, *mtn; + dax_driver_unregister(&device_dax_kmem_driver); if (!any_hotremove_failed) kfree_const(kmem_name); - destroy_memory_type(dax_slowmem_type); + list_for_each_entry_safe(mtype, mtn, &kmem_memory_types, list) { + list_del(&mtype->list); + destroy_memory_type(mtype); + } } MODULE_AUTHOR("Intel Corporation"); diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h index 9377239c8d34..aca22220cb5c 100644 --- a/include/linux/memory-tiers.h +++ b/include/linux/memory-tiers.h @@ -24,6 +24,8 @@ struct memory_tier; struct memory_dev_type { /* list of memory types that are part of same tier as this type */ struct list_head tier_sibiling; + /* list of memory types that are managed by one driver */ + struct list_head list; /* abstract distance for this specific memory type */ int adistance; /* Nodes of same abstract distance */ diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c index 9a734ef2edfb..38005c60fa2d 100644 --- a/mm/memory-tiers.c +++ b/mm/memory-tiers.c @@ -581,7 +581,7 @@ EXPORT_SYMBOL_GPL(init_node_memory_type); void clear_node_memory_type(int node, struct memory_dev_type *memtype) { mutex_lock(&memory_tier_lock); - if (node_memory_types[node].memtype == memtype) + if (node_memory_types[node].memtype == memtype || !memtype) node_memory_types[node].map_count--; /* * If we umapped all the attached devices to this node,