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[2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id n2-20020aa7c782000000b00521953ce6e0sm2074329eds.93.2023.07.21.06.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:13:22 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Michael Turquette , Stephen Boyd , Jon Hunter , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: clock: tegra124-dfll: Convert to json-schema Date: Fri, 21 Jul 2023 15:13:21 +0200 Message-ID: <20230721131322.2991364-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Thierry Reding Convert the Tegra124 (and later) DFLL bindings from the free-form text format to json-schema. Signed-off-by: Thierry Reding --- Changes in v2: - should now validate properly because pinmux bindings have been merged .../bindings/clock/nvidia,tegra124-dfll.txt | 155 ---------- .../bindings/clock/nvidia,tegra124-dfll.yaml | 277 ++++++++++++++++++ 2 files changed, 277 insertions(+), 155 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt deleted file mode 100644 index f7d347385b57..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ /dev/null @@ -1,155 +0,0 @@ -NVIDIA Tegra124 DFLL FCPU clocksource - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The DFLL IP block on Tegra is a root clocksource designed for clocking -the fast CPU cluster. It consists of a free-running voltage controlled -oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop -control module that will automatically adjust the VDD_CPU voltage by -communicating with an off-chip PMIC either via an I2C bus or via PWM signals. - -Required properties: -- compatible : should be one of: - - "nvidia,tegra124-dfll": for Tegra124 - - "nvidia,tegra210-dfll": for Tegra210 -- reg : Defines the following set of registers, in the order listed: - - registers for the DFLL control logic. - - registers for the I2C output logic. - - registers for the integrated I2C master controller. - - look-up table RAM for voltage register values. -- interrupts: Should contain the DFLL block interrupt. -- clocks: Must contain an entry for each entry in clock-names. - See clock-bindings.txt for details. -- clock-names: Must include the following entries: - - soc: Clock source for the DFLL control logic. - - ref: The closed loop reference clock - - i2c: Clock source for the integrated I2C master. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - dvco: Reset control for the DFLL DVCO. -- #clock-cells: Must be 0. -- clock-output-names: Name of the clock output. -- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL - hardware will start controlling. The regulator will be queried for - the I2C register, control values and supported voltages. - -Required properties for the control loop parameters: -- nvidia,sample-rate: Sample rate of the DFLL control loop. -- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM. -- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM. -- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM. -- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM. -- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM. - -Optional properties for the control loop parameters: -- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM. - -Optional properties for mode selection: -- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C. - -Required properties for I2C mode: -- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode. - -Required properties for PWM mode: -- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds. -- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM - control is disabled and the PWM output is tristated. Note that this voltage is - configured in hardware, typically via a resistor divider. -- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control - is enabled and PWM output is low. Hence, this is the minimum output voltage - that the regulator supports when PWM control is enabled. -- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts - corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th - duty cycle would be: nvidia,pwm-min-microvolts + - nvidia,pwm-voltage-step-microvolts * 2. -- pinctrl-0: I/O pad configuration when PWM control is enabled. -- pinctrl-1: I/O pad configuration when PWM control is disabled. -- pinctrl-names: must include the following entries: - - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled. - - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled. - -Example for I2C: - -clock@70110000 { - compatible = "nvidia,tegra124-dfll"; - reg = <0 0x70110000 0 0x100>, /* DFLL control */ - <0 0x70110000 0 0x100>, /* I2C output control */ - <0 0x70110100 0 0x100>, /* Integrated I2C controller */ - <0 0x70110200 0 0x100>; /* Look-up table RAM */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, - <&tegra_car TEGRA124_CLK_DFLL_REF>, - <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; - reset-names = "dvco"; - #clock-cells = <0>; - clock-output-names = "dfllCPU_out"; - vdd-cpu-supply = <&vdd_cpu>; - - nvidia,sample-rate = <12500>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,cf = <10>; - nvidia,ci = <0>; - nvidia,cg = <2>; - - nvidia,i2c-fs-rate = <400000>; -}; - -Example for PWM: - -clock@70110000 { - compatible = "nvidia,tegra124-dfll"; - reg = <0 0x70110000 0 0x100>, /* DFLL control */ - <0 0x70110000 0 0x100>, /* I2C output control */ - <0 0x70110100 0 0x100>, /* Integrated I2C controller */ - <0 0x70110200 0 0x100>; /* Look-up table RAM */ - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, - <&tegra_car TEGRA210_CLK_DFLL_REF>, - <&tegra_car TEGRA124_CLK_I2C5>;; - clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; - reset-names = "dvco"; - #clock-cells = <0>; - clock-output-names = "dfllCPU_out"; - - nvidia,sample-rate = <25000>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,cf = <6>; - nvidia,ci = <0>; - nvidia,cg = <2>; - - nvidia,pwm-min-microvolts = <708000>; /* 708mV */ - nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ - nvidia,pwm-to-pmic; - nvidia,pwm-tristate-microvolts = <1000000>; - nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */ - - pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; - pinctrl-0 = <&dvfs_pwm_active_state>; - pinctrl-1 = <&dvfs_pwm_inactive_state>; -}; - -/* pinmux nodes added for completeness. Binding doc can be found in: - * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml - */ - -pinmux: pinmux@700008d4 { - dvfs_pwm_active_state: dvfs_pwm_active { - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,tristate = ; - }; - }; - dvfs_pwm_inactive_state: dvfs_pwm_inactive { - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,tristate = ; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml new file mode 100644 index 000000000000..4a9a48613ec6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml @@ -0,0 +1,277 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra124-dfll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra124 (and later) DFLL FCPU clocksource + +maintainers: + - Thierry Reding + - Jon Hunter + +description: + The DFLL IP block on Tegra is a root clocksource designed for clocking + the fast CPU cluster. It consists of a free-running voltage controlled + oscillator connected to the CPU voltage rail (VDD_CPU), and a closed + loop control module that will automatically adjust the VDD_CPU voltage + by communicating with an off-chip PMIC either via an I2C bus or via + PWM signals. + +properties: + compatible: + enum: + - nvidia,tegra124-dfll + - nvidia,tegra210-dfll + + reg: + items: + - description: DFLL control logic + - description: I2C output logic + - description: integrated I2C controller + - description: look-up table RAM for voltage register values + + interrupts: + maxItems: 1 + + clocks: + items: + - description: clock source for the DFLL control logic + - description: closed loop reference clock + - description: clock source for the integrated I2C controller + + clock-names: + items: + - const: soc + - const: ref + - const: i2c + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + + "#clock-cells": + const: 0 + + clock-output-names: + description: name of the clock output + + vdd-cpu-supply: + description: Regulator for the CPU voltage rail that the DFLL + hardware will start controlling. The regulator will be queried for + the I2C register, control values and supported voltages. + + nvidia,sample-rate: + description: Sample rate of the DFLL control loop. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,droop-ctrl: + description: See the register CL_DVFS_DROOP_CTRL in the TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,force-mode: + description: See the field DFLL_PARAMS_FORCE_MODE in the TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,cf: + description: Numeric value, see the field DFLL_PARAMS_CF_PARAM in + the TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,ci: + description: Numeric value, see the field DFLL_PARAMS_CI_PARAM in + the TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,cg: + description: Numeric value, see the field DFLL_PARAMS_CG_PARAM in + the TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + + # optional properties + nvidia,cg-scale: + description: Boolean value, see the field DFLL_PARAMS_CG_SCALE in + the TRM. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,pwm-to-pmic: + description: Use PWM to control regulator rather then I2C. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,i2c-fs-rate: + description: I2C transfer rate, if using full speed mode. + $ref: /schemas/types.yaml#/definitions/uint32 + + # required properties for PWM mode + nvidia,pwm-period-nanoseconds: + description: period of PWM square wave in nanoseconds. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,pwm-tristate-microvolts: + description: Regulator voltage in micro volts when PWM control is + disabled and the PWM output is tristated. Note that this voltage + is configured in hardware, typically via a resistor divider. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,pwm-min-microvolts: + description: Regulator voltage in micro volts when PWM control is + enabled and PWM output is low. Hence, this is the minimum output + voltage that the regulator supports when PWM control is enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,pwm-voltage-step-microvolts: + description: | + Voltage increase in micro volts corresponding to a 1/33th increase + in duty cycle. Eg the voltage for 2/33th duty cycle would be: + + nvidia,pwm-min-microvolts + nvidia,pwm-voltage-step-microvolts * 2 + $ref: /schemas/types.yaml#/definitions/uint32 + + pinctrl-names: + items: + # I/O pad configuration when PWM control is enabled + - const: dvfs_pwm_enable + # I/O pad configuration when PWM control is disabled + - const: dvfs_pwm_disable + + pinctrl-0: true + pinctrl-1: true + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra124-dfll + then: + properties: + resets: + items: + - description: DFLL DVCO reset + + reset-names: + items: + - const: dvco + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-dfll + then: + properties: + resets: + items: + - description: DFLL DVCO reset + - description: DFLL reset + + reset-names: + items: + - const: dvco + - const: dfll + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + clock@70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0x70110000 0x100>, /* DFLL control */ + <0x70110000 0x100>, /* I2C output control */ + <0x70110100 0x100>, /* Integrated I2C controller */ + <0x70110200 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, + <&tegra_car TEGRA124_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + vdd-cpu-supply = <&vdd_cpu>; + + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + + nvidia,i2c-fs-rate = <400000>; + }; + + - | + #include + #include + #include + #include + + clock@70110000 { + compatible = "nvidia,tegra210-dfll"; + reg = <0x70110000 0x100>, /* DFLL control */ + <0x70110000 0x100>, /* I2C output control */ + <0x70110100 0x100>, /* Integrated I2C controller */ + <0x70110200 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA210_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, + <&tegra_car 155>; + reset-names = "dvco", "dfll"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + + nvidia,sample-rate = <25000>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + + nvidia,pwm-min-microvolts = <708000>; /* 708mV */ + nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts = <1000000>; + nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */ + + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; + }; + + /* + * pinmux nodes added for completeness. Binding doc can be found in: + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml + */ + + pinmux: pinmux@700008d4 { + compatible = "nvidia,tegra210-pinmux"; + reg = <0x700008d4 0x29c>, /* Pad control registers */ + <0x70003000 0x294>; /* Mux registers */ + + dvfs_pwm_active_state: pinmux-dvfs-pwm-active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + + dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + }; From patchwork Fri Jul 21 13:13:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 13321972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2963EEB64DD for ; Fri, 21 Jul 2023 13:13:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229656AbjGUNNd (ORCPT ); Fri, 21 Jul 2023 09:13:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230226AbjGUNNb (ORCPT ); Fri, 21 Jul 2023 09:13:31 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29F9F30DB; Fri, 21 Jul 2023 06:13:26 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-993a37b79e2so302938366b.1; Fri, 21 Jul 2023 06:13:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689945204; x=1690550004; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y1ygg2Jn0dhD6FjKNZtwLf4GFouySs0VxaChZ+hIHFI=; b=A8ce8Wv1hqz+dhMozEqVKU3Q5gbwjy3MoJ9HNcCltj8vUbqCuhdM5PHBhei1FNfqzF 6dudhjS0CtKUD4n+OmMkNndQlnrKniYVtKIVZEIAehPshPyseLsGlEu7RLScnesKSxqA OXx+WMw4iglP6u14nArJgOI9NP3N/cJROWV1C/u73O1g3mN4Swn3fRG8g3zSEh/HDgcg EBQlwWR5KMRQwTH/viVJeu4dSpg0cunXegVwbT3JN9gBqayaxk0glSSGgPeOJAJ076ek 8veNfICJ0etF/vaIzhVGVGt8s/2SBDDOJY2anx/WRxuJFyFaU47fvV/8+xKNKjtZRh4B IYFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689945204; x=1690550004; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y1ygg2Jn0dhD6FjKNZtwLf4GFouySs0VxaChZ+hIHFI=; b=Y36RKXbORC18H3s6qyaIMTYL9nx27ahsRzQBlWYlvywwW7DbiDQ1BSVXOwgOLsHgLq UUb5DTYwtHAXNfwAZvcndlP7gu7AuYO6TEW1KuYsLSmXnTllITSX33zCQ0hPNVYc+vNQ iN3TdA3tXuBihb+1hWuxfTk6q+jRqUH7sMNbGp5qG5HRgRoS7g+BivXzEC1a2l2hM440 JpYVFdMeUAcEIs4U2SWdbI6Mw/zyWe/sS9QhS38T5zk+PoeoYZ6RYW83HUu7EqG5lIsU Oj1cBUTmw9xCr2QLPzSMZbic2sGWsMTN0qX9iyCt8O5xrb4u4xj9+Y0VWdXcxrhu3QeZ YhTA== X-Gm-Message-State: ABy/qLYanVAfnThrk97vAwT3FuTKMqOlzcpllj+7KJEzkYfSIINcWDK4 q5di0vzlWcu8NOEchKotA78= X-Google-Smtp-Source: APBJJlHAtsOTOWgZFH3Pd4W1FZW8zutVblaO2WWAjSmBrQKyzTvNO4p3eMK3Hoxgutnv80gvTh6L/g== X-Received: by 2002:a17:906:7386:b0:99a:8053:158 with SMTP id f6-20020a170906738600b0099a80530158mr1691434ejl.68.1689945204493; Fri, 21 Jul 2023 06:13:24 -0700 (PDT) Received: from localhost (p200300e41f1bd600f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id jx16-20020a170906ca5000b00993664a9987sm2167822ejb.103.2023.07.21.06.13.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 06:13:23 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Michael Turquette , Stephen Boyd , Jon Hunter , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 2/2] dt-bindings: clock: tegra: Document Tegra132 compatible Date: Fri, 21 Jul 2023 15:13:22 +0200 Message-ID: <20230721131322.2991364-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721131322.2991364-1-thierry.reding@gmail.com> References: <20230721131322.2991364-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Thierry Reding The Tegra132 clock and reset controller is largely compatible with the version found on Tegra124 but it does have slight differences in what clocks it exposes, so a separate compatible string is needed. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- .../devicetree/bindings/clock/nvidia,tegra124-car.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml index 0fc55f441ac3..2d7736a10178 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml @@ -27,7 +27,9 @@ description: | properties: compatible: - const: nvidia,tegra124-car + enum: + - nvidia,tegra124-car + - nvidia,tegra132-car reg: maxItems: 1