From patchwork Wed Jul 26 00:31:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13327335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECFA1EB64DD for ; Wed, 26 Jul 2023 00:34:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qOST1-0001U8-AX; Tue, 25 Jul 2023 20:33:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOSSz-0001Sw-CC for qemu-devel@nongnu.org; Tue, 25 Jul 2023 20:33:25 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOSSx-00035m-S8 for qemu-devel@nongnu.org; Tue, 25 Jul 2023 20:33:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1690331603; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UfyYlAXPEO6rGCDdsc7We1YnnIDJV5ZWMB2m4Bc86dg=; b=aPRLirJ+dUgRw+dYFbmo9s1Roac1dhqQS7zMgYwx95uVN6/Kqwc7aHLGbYt3EkXvxeL0UO JAUcJXzSpCe33pIX4O+cJE9b+eUJT4lnVzPk4KH1Mf3rrSIu3mTEQ2nAbmg49M8uXkVByA U8omKwTm5J/ozuzR2t355AYpMH/6Ymg= Received: from mimecast-mx02.redhat.com (66.187.233.73 [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-662-IObcQVRKOoOWnJXGLt_pnQ-1; Tue, 25 Jul 2023 20:33:19 -0400 X-MC-Unique: IObcQVRKOoOWnJXGLt_pnQ-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 1FFD41C09A4A; Wed, 26 Jul 2023 00:33:18 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.80]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7CC13492C13; Wed, 26 Jul 2023 00:33:09 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, imammedo@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v2 1/8] machine: Use error handling when CPU type is checked Date: Wed, 26 Jul 2023 10:31:58 +1000 Message-ID: <20230726003205.1599788-2-gshan@redhat.com> In-Reply-To: <20230726003205.1599788-1-gshan@redhat.com> References: <20230726003205.1599788-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org QEMU will be terminated if the specified CPU type isn't supported in machine_run_board_init(). The list of supported CPU type is maintained in mc->valid_cpu_types. The error handling can be used to propagate error messages, to be consistent how the errors are handled for other situations in the same function. No functional change intended. Suggested-by: Igor Mammedov Signed-off-by: Gavin Shan --- hw/core/machine.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index f0d35c6401..d7e7f8f120 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1355,6 +1355,7 @@ void machine_run_board_init(MachineState *machine, const char *mem_path, Error * MachineClass *machine_class = MACHINE_GET_CLASS(machine); ObjectClass *oc = object_class_by_name(machine->cpu_type); CPUClass *cc; + Error *local_err = NULL; /* This checkpoint is required by replay to separate prior clock reading from the other reads, because timer polling functions query @@ -1423,15 +1424,16 @@ void machine_run_board_init(MachineState *machine, const char *mem_path, Error * if (!machine_class->valid_cpu_types[i]) { /* The user specified CPU is not valid */ - error_report("Invalid CPU type: %s", machine->cpu_type); - error_printf("The valid types are: %s", - machine_class->valid_cpu_types[0]); + error_setg(&local_err, "Invalid CPU type: %s", machine->cpu_type); + error_append_hint(&local_err, "The valid types are: %s", + machine_class->valid_cpu_types[0]); for (i = 1; machine_class->valid_cpu_types[i]; i++) { - error_printf(", %s", machine_class->valid_cpu_types[i]); + error_append_hint(&local_err, ", %s", + machine_class->valid_cpu_types[i]); } - error_printf("\n"); + error_append_hint(&local_err, "\n"); - exit(1); + error_propagate(errp, local_err); } } From patchwork Wed Jul 26 00:31:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13327334 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08A07C41513 for ; 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bh=jF1mIBor31mE5IynmL+MzqSZLA280LeTAIhQhMoDghU=; b=Mvlr/18Rm3u22iQIDcIpQjA304bi/MuuQIiBoaU2w9QdGdrCpJL/mSezbsH/wYKJSPkNfC 3wvfSc9cxpYrWdt6+suUFvlZ5mEv7T3dxUySwWGpV10YA3UcX2inU2GJzxsV38ca5js4bl Mlh/lifUqd2gaaqIKYMfqGifjRl3H24= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-56-pLPoaZ-2OQKUXNAp_TA4cw-1; Tue, 25 Jul 2023 20:33:29 -0400 X-MC-Unique: pLPoaZ-2OQKUXNAp_TA4cw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id EBBE4858290; Wed, 26 Jul 2023 00:33:27 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.80]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 96BA946A3AA; Wed, 26 Jul 2023 00:33:18 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, imammedo@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v2 2/8] machine: Introduce helper is_cpu_type_supported() Date: Wed, 26 Jul 2023 10:31:59 +1000 Message-ID: <20230726003205.1599788-3-gshan@redhat.com> In-Reply-To: <20230726003205.1599788-1-gshan@redhat.com> References: <20230726003205.1599788-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The logic of checking if the specified CPU type is supported in machine_run_board_init() is independent enough. Factor it out into helper is_cpu_type_supported(). With this, machine_run_board_init() looks a bit clean. Since we're here, @machine_class is renamed to @mc to avoid multiple line spanning of code. The comments are tweaked a bit either. No functional change intended. Signed-off-by: Gavin Shan --- hw/core/machine.c | 82 +++++++++++++++++++++++++---------------------- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index d7e7f8f120..fe110e9b0a 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1349,12 +1349,50 @@ out: return r; } +static void is_cpu_type_supported(MachineState *machine, Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(machine); + ObjectClass *oc = object_class_by_name(machine->cpu_type); + CPUClass *cc; + int i; + + /* + * Check if the user specified CPU type is supported when the valid + * CPU types have been determined. Note that the user specified CPU + * type is provided through '-cpu' option. + */ + if (mc->valid_cpu_types && machine->cpu_type) { + for (i = 0; mc->valid_cpu_types[i]; i++) { + if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) { + break; + } + } + + /* The user specified CPU type isn't valid */ + if (!mc->valid_cpu_types[i]) { + error_setg(errp, "Invalid CPU type: %s", machine->cpu_type); + error_append_hint(errp, "The valid types are: %s", + mc->valid_cpu_types[0]); + for (i = 1; mc->valid_cpu_types[i]; i++) { + error_append_hint(errp, ", %s", mc->valid_cpu_types[i]); + } + error_append_hint(errp, "\n"); + + return; + } + } + + /* Check if CPU type is deprecated and warn if so */ + cc = CPU_CLASS(oc); + if (cc && cc->deprecation_note) { + warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, + cc->deprecation_note); + } +} void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) { MachineClass *machine_class = MACHINE_GET_CLASS(machine); - ObjectClass *oc = object_class_by_name(machine->cpu_type); - CPUClass *cc; Error *local_err = NULL; /* This checkpoint is required by replay to separate prior clock @@ -1406,42 +1444,10 @@ void machine_run_board_init(MachineState *machine, const char *mem_path, Error * machine->ram = machine_consume_memdev(machine, machine->memdev); } - /* If the machine supports the valid_cpu_types check and the user - * specified a CPU with -cpu check here that the user CPU is supported. - */ - if (machine_class->valid_cpu_types && machine->cpu_type) { - int i; - - for (i = 0; machine_class->valid_cpu_types[i]; i++) { - if (object_class_dynamic_cast(oc, - machine_class->valid_cpu_types[i])) { - /* The user specificed CPU is in the valid field, we are - * good to go. - */ - break; - } - } - - if (!machine_class->valid_cpu_types[i]) { - /* The user specified CPU is not valid */ - error_setg(&local_err, "Invalid CPU type: %s", machine->cpu_type); - error_append_hint(&local_err, "The valid types are: %s", - machine_class->valid_cpu_types[0]); - for (i = 1; machine_class->valid_cpu_types[i]; i++) { - error_append_hint(&local_err, ", %s", - machine_class->valid_cpu_types[i]); - } - error_append_hint(&local_err, "\n"); - - error_propagate(errp, local_err); - } - } - - /* Check if CPU type is deprecated and warn if so */ - cc = CPU_CLASS(oc); - if (cc && cc->deprecation_note) { - warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, - cc->deprecation_note); + /* Check if the CPU type is supported */ + is_cpu_type_supported(machine, &local_err); + if (local_err) { + error_propagate(errp, local_err); } if (machine->cgs) { From patchwork Wed Jul 26 00:32:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13327339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1DC61C001DF for ; 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bh=VNlHIxY/3NIS52D7SMkw4PFmgOcF6RXD+YEI+jhYGDc=; b=ZlZvznOFjeAIRs+S0DZCyOiuSu1iOjOAJZSO3YXRHDF2YDuCKfg/80jh9i2eyNISIMOYke WUlSMn8Yxw74b6o9M7kjYIoApO6YxclLH8q3XuoOg07yKOioZoTZn/h/ADs192mCEFRDzu gfDG1hiLF7Sh9/ewvEcCZkVP6Nl1I18= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-615-FMms2AvTM8WlT8kLmb7IAw-1; Tue, 25 Jul 2023 20:33:39 -0400 X-MC-Unique: FMms2AvTM8WlT8kLmb7IAw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id B1C698002BF; Wed, 26 Jul 2023 00:33:37 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.80]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8806F46A3A9; Wed, 26 Jul 2023 00:33:28 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, imammedo@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v2 3/8] machine: Print supported CPU models instead of typenames Date: Wed, 26 Jul 2023 10:32:00 +1000 Message-ID: <20230726003205.1599788-4-gshan@redhat.com> In-Reply-To: <20230726003205.1599788-1-gshan@redhat.com> References: <20230726003205.1599788-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The supported CPU models instead of typenames should be printed when the user specified CPU type isn't supported in is_cpu_type_supported(), to be consistent with the CPU model specified by user through '-cpu ' option. Correct the error messages to print CPU models, maintained in the newly added mc->valid_cpu_models because there is no fixed pattern for the conversion between CPU model and typename. Besides, mc->valid_cpu_types and mc->valid_cpu_models are further constified since we're here. Signed-off-by: Gavin Shan --- hw/core/machine.c | 10 ++++++---- hw/m68k/q800.c | 8 +++++++- include/hw/boards.h | 3 ++- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index fe110e9b0a..858f8ede89 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1362,6 +1362,8 @@ static void is_cpu_type_supported(MachineState *machine, Error **errp) * type is provided through '-cpu' option. */ if (mc->valid_cpu_types && machine->cpu_type) { + assert(mc->valid_cpu_models && mc->valid_cpu_models[0]); + for (i = 0; mc->valid_cpu_types[i]; i++) { if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) { break; @@ -1371,10 +1373,10 @@ static void is_cpu_type_supported(MachineState *machine, Error **errp) /* The user specified CPU type isn't valid */ if (!mc->valid_cpu_types[i]) { error_setg(errp, "Invalid CPU type: %s", machine->cpu_type); - error_append_hint(errp, "The valid types are: %s", - mc->valid_cpu_types[0]); - for (i = 1; mc->valid_cpu_types[i]; i++) { - error_append_hint(errp, ", %s", mc->valid_cpu_types[i]); + error_append_hint(errp, "The valid models are: %s", + mc->valid_cpu_models[0]); + for (i = 1; mc->valid_cpu_models[i]; i++) { + error_append_hint(errp, ", %s", mc->valid_cpu_models[i]); } error_append_hint(errp, "\n"); diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index b770b71d54..1e360674a7 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -596,11 +596,16 @@ static GlobalProperty hw_compat_q800[] = { }; static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800); -static const char *q800_machine_valid_cpu_types[] = { +static const char * const q800_machine_valid_cpu_types[] = { M68K_CPU_TYPE_NAME("m68040"), NULL }; +static const char * const q800_machine_valid_cpu_models[] = { + "m68040", + NULL +}; + static void q800_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -609,6 +614,7 @@ static void q800_machine_class_init(ObjectClass *oc, void *data) mc->init = q800_machine_init; mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); mc->valid_cpu_types = q800_machine_valid_cpu_types; + mc->valid_cpu_models = q800_machine_valid_cpu_models; mc->max_cpus = 1; mc->block_default_type = IF_SCSI; mc->default_ram_id = "m68k_mac.ram"; diff --git a/include/hw/boards.h b/include/hw/boards.h index ed83360198..81747b0788 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -268,7 +268,8 @@ struct MachineClass { bool has_hotpluggable_cpus; bool ignore_memory_transaction_failures; int numa_mem_align_shift; - const char **valid_cpu_types; + const char * const *valid_cpu_types; + const char * const *valid_cpu_models; strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; From patchwork Wed Jul 26 00:32:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13327340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45565C0015E for ; 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bh=cK/u9hBezZjv5U8uB342B7vDcqbotvyMZ2sIvXNJXuw=; b=I5qOfScqUFlnJ7GV1ug8RMKLiXpZ9mEhSRiHYi4ZWjEImytu8WDDJfX/2bNXzWnx77/lDQ 3oaRWhCLOdonwPu1sgHXXH7WvMgNSwROVckKSNGWh9XhofGqFGUBjuYBXZebAh2Y49p9MK fA7S6dcMzkPpZVVHkIUAH8KdL//H/5Q= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-5-J2x1c4w3PviT9B5_7O8dmg-1; Tue, 25 Jul 2023 20:33:48 -0400 X-MC-Unique: J2x1c4w3PviT9B5_7O8dmg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C410885A58A; Wed, 26 Jul 2023 00:33:46 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.80]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 32EB0492C13; Wed, 26 Jul 2023 00:33:37 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, imammedo@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v2 4/8] hw/arm/virt: Check CPU type in machine_run_board_init() Date: Wed, 26 Jul 2023 10:32:01 +1000 Message-ID: <20230726003205.1599788-5-gshan@redhat.com> In-Reply-To: <20230726003205.1599788-1-gshan@redhat.com> References: <20230726003205.1599788-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set mc->valid_cpu_{types, models} so that the specified CPU type can be checked in machine_run_board_init(). We needn't to do the check by ourselves. Signed-off-by: Gavin Shan --- hw/arm/virt.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7d9dbc2663..debd85614e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -203,7 +203,7 @@ static const int a15irqmap[] = { [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ }; -static const char *valid_cpus[] = { +static const char * const valid_cpu_types[] = { #ifdef CONFIG_TCG ARM_CPU_TYPE_NAME("cortex-a7"), ARM_CPU_TYPE_NAME("cortex-a15"), @@ -219,19 +219,27 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), + NULL }; -static bool cpu_type_valid(const char *cpu) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { - if (strcmp(cpu, valid_cpus[i]) == 0) { - return true; - } - } - return false; -} +static const char * const valid_cpu_models[] = { +#ifdef CONFIG_TCG + "cortex-a7", + "cortex-a15", + "cortex-a35", + "cortex-a55", + "cortex-a72", + "cortex-a76", + "a64fx", + "neoverse-n1", + "neoverse-v1", +#endif + "cortex-a53", + "cortex-a57", + "host", + "max", + NULL +}; static void create_randomness(MachineState *ms, const char *node) { @@ -2030,11 +2038,6 @@ static void machvirt_init(MachineState *machine) unsigned int smp_cpus = machine->smp.cpus; unsigned int max_cpus = machine->smp.max_cpus; - if (!cpu_type_valid(machine->cpu_type)) { - error_report("mach-virt: CPU type %s not supported", machine->cpu_type); - exit(1); - } - possible_cpus = mc->possible_cpu_arch_ids(machine); /* @@ -2953,6 +2956,8 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) #else mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); #endif + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type; assert(!mc->get_hotplug_handler); From patchwork Wed Jul 26 00:32:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13327341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7D3AEB64DD for ; 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bh=J8S0eAWzN6EGtNTjC2qFLYW++XUaEL4oEsl8iKKMElY=; b=IY5WVeiceHRIVmRaQJuVo+oNvQ8BtsBECERaudajt+AmsiqVSCpMVugENnca/ncUP0PhGp ODq8rrqAqOb5EAk7q0iqhQ2T9f+4+Crq+VT1fEfPdT6bPSBs2ab6Q8Q6ElXzA0JtA65MdY ZSeI+PlefBf/5+Loy331y8O2Z3m7S50= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-573-05eIoiskP4W0CGpOtJpIhA-1; Tue, 25 Jul 2023 20:33:57 -0400 X-MC-Unique: 05eIoiskP4W0CGpOtJpIhA-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E09FF8030AC; Wed, 26 Jul 2023 00:33:55 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.80]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6621F4A9004; Wed, 26 Jul 2023 00:33:47 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, imammedo@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v2 5/8] hw/arm/virt: Unsupported host CPU model on TCG Date: Wed, 26 Jul 2023 10:32:02 +1000 Message-ID: <20230726003205.1599788-6-gshan@redhat.com> In-Reply-To: <20230726003205.1599788-1-gshan@redhat.com> References: <20230726003205.1599788-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The 'host' CPU model isn't supported until KVM or HVF is enabled. For example, the following error messages are seen when the guest is started with option '-cpu cortex-a8'. qemu-system-aarch64: Invalid CPU type: cortex-a8-arm-cpu The valid models are: cortex-a7, cortex-a15, cortex-a35, cortex-a55, cortex-a72, cortex-a76, a64fx, neoverse-n1, neoverse-v1, cortex-a53, cortex-a57, host, max Hide 'host' CPU model until KVM or HVF is enabled. Signed-off-by: Gavin Shan --- hw/arm/virt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index debd85614e..2562ca0c1e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -217,7 +217,9 @@ static const char * const valid_cpu_types[] = { #endif ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) ARM_CPU_TYPE_NAME("host"), +#endif ARM_CPU_TYPE_NAME("max"), NULL }; @@ -236,7 +238,9 @@ static const char * const valid_cpu_models[] = { #endif "cortex-a53", "cortex-a57", +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) "host", +#endif "max", NULL }; From patchwork Wed Jul 26 00:32:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13327342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81110EB64DD for ; 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bh=26N7Vh+u0KOHFAhb0L1Q0yfOwGybUwteYTG075B8U+o=; b=eM2egqYNWFsqOW4OzY8fAe2nuyDsZYAAhhbpPPmRBfzv74qwY0g4LkkLMxS2Bl061BXSbm 3yD4QUymCxTHt0twzXxVCbziYTcVxfkWJpjj4ng4/bUwTel3dtKQMVVIwPAHKCxCsP00wf n3EMTof6NBKk8ap2/IJoekBeEDzkyIw= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-633-B4_NLybtPG2_zUm-kxJImQ-1; Tue, 25 Jul 2023 20:34:06 -0400 X-MC-Unique: B4_NLybtPG2_zUm-kxJImQ-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 3528A800B35; Wed, 26 Jul 2023 00:34:05 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.80]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 708C1492C13; Wed, 26 Jul 2023 00:33:56 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, imammedo@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v2 6/8] hw/arm/sbsa-ref: Check CPU type in machine_run_board_init() Date: Wed, 26 Jul 2023 10:32:03 +1000 Message-ID: <20230726003205.1599788-7-gshan@redhat.com> In-Reply-To: <20230726003205.1599788-1-gshan@redhat.com> References: <20230726003205.1599788-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set mc->valid_cpu_{types, models} so that the specified CPU type can be checked in machine_run_board_init(). We needn't to do the check by ourselves. Signed-off-by: Gavin Shan --- hw/arm/sbsa-ref.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index bc89eb4806..66d171b745 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -149,25 +149,23 @@ static const int sbsa_ref_irqmap[] = { [SBSA_GWDT_WS0] = 16, }; -static const char * const valid_cpus[] = { +static const char * const valid_cpu_types[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), ARM_CPU_TYPE_NAME("max"), + NULL, }; -static bool cpu_type_valid(const char *cpu) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { - if (strcmp(cpu, valid_cpus[i]) == 0) { - return true; - } - } - return false; -} +static const char * const valid_cpu_models[] = { + "cortex-a57", + "cortex-a72", + "neoverse-n1", + "neoverse-v1", + "max", + NULL, +}; static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) { @@ -730,11 +728,6 @@ static void sbsa_ref_init(MachineState *machine) const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; - if (!cpu_type_valid(machine->cpu_type)) { - error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type); - exit(1); - } - if (kvm_enabled()) { error_report("sbsa-ref: KVM is not supported for this machine"); exit(1); @@ -899,6 +892,8 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) mc->init = sbsa_ref_init; mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mc->max_cpus = 512; mc->pci_allow_0_address = true; mc->minimum_page_bits = 12; From patchwork Wed Jul 26 00:32:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13327336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 145D2C0015E for ; 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bh=lfmBrdlAtxGFUhBLkxZNIajxS58lzkN4jrK08DaO3l0=; b=aWqrOo0fCCxD//UIrbJoQHZYZoFqD7AM9pDOJxHw35JTCBMVoWbRNVZtgKHr4FggWbup9y qqMEV7VkBcXqxFS3nOuZdf6ZCdvH0ho3HNzrkQJO58YLBiaV5jHzkUKiszB+MjWb90ezTS 9crsdF6DP15kGxeIuiMMG5Nya6gUSrg= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-48-8A2SSzyRPpK7hoBInbo8Sg-1; Tue, 25 Jul 2023 20:34:15 -0400 X-MC-Unique: 8A2SSzyRPpK7hoBInbo8Sg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id DC9AA1006A71; Wed, 26 Jul 2023 00:34:13 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.80]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AB43F492C13; Wed, 26 Jul 2023 00:34:05 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, imammedo@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v2 7/8] hw/arm: Check CPU type in machine_run_board_init() Date: Wed, 26 Jul 2023 10:32:04 +1000 Message-ID: <20230726003205.1599788-8-gshan@redhat.com> In-Reply-To: <20230726003205.1599788-1-gshan@redhat.com> References: <20230726003205.1599788-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set mc->valid_cpu_{types, models} so that the specified CPU type can be checked in machine_run_board_init(). We needn't to do the check by ourselves. Signed-off-by: Gavin Shan --- hw/arm/bananapi_m2u.c | 18 +++++++++++------ hw/arm/cubieboard.c | 18 +++++++++++------ hw/arm/mps2-tz.c | 34 +++++++++++++++++++++++++------ hw/arm/mps2.c | 44 +++++++++++++++++++++++++++++++++++------ hw/arm/msf2-som.c | 18 +++++++++++------ hw/arm/musca.c | 19 +++++++++++------- hw/arm/npcm7xx_boards.c | 19 +++++++++++------- hw/arm/orangepi.c | 18 +++++++++++------ 8 files changed, 138 insertions(+), 50 deletions(-) diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 74121d8966..d6c9b90370 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -29,6 +29,16 @@ static struct arm_boot_info bpim2u_binfo; +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "cortex-a7", + NULL +}; + /* * R40 can boot from mmc0 and mmc2, and bpim2u has two mmc interface, one is * connected to sdcard and another mount an emmc media. @@ -70,12 +80,6 @@ static void bpim2u_init(MachineState *machine) exit(1); } - /* Only allow Cortex-A7 for this board */ - if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { - error_report("This board can only be used with cortex-a7 CPU"); - exit(1); - } - r40 = AW_R40(object_new(TYPE_AW_R40)); object_property_add_child(OBJECT(machine), "soc", OBJECT(r40)); object_unref(OBJECT(r40)); @@ -138,6 +142,8 @@ static void bpim2u_machine_init(MachineClass *mc) mc->max_cpus = AW_R40_NUM_CPUS; mc->default_cpus = AW_R40_NUM_CPUS; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mc->default_ram_size = 1 * GiB; mc->default_ram_id = "bpim2u.ram"; } diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 8c7fa91529..4a66a781a4 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -28,6 +28,16 @@ static struct arm_boot_info cubieboard_binfo = { .board_id = 0x1008, }; +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a8"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "cortex-a8", + NULL +}; + static void cubieboard_init(MachineState *machine) { AwA10State *a10; @@ -51,12 +61,6 @@ static void cubieboard_init(MachineState *machine) exit(1); } - /* Only allow Cortex-A8 for this board */ - if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a8")) != 0) { - error_report("This board can only be used with cortex-a8 CPU"); - exit(1); - } - a10 = AW_A10(object_new(TYPE_AW_A10)); object_property_add_child(OBJECT(machine), "soc", OBJECT(a10)); object_unref(OBJECT(a10)); @@ -115,6 +119,8 @@ static void cubieboard_machine_init(MachineClass *mc) { mc->desc = "cubietech cubieboard (Cortex-A8)"; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mc->default_ram_size = 1 * GiB; mc->init = cubieboard_init; mc->block_default_type = IF_IDE; diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 5873107302..7eba212659 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -183,6 +183,26 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) #define MPS3_DDR_SIZE (2 * GiB) #endif +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m33"), + NULL +}; + +static const char * const mps3tz_an547_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m55"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "cortex-m33", + NULL +}; + +static const char * const mps3tz_an547_valid_cpu_models[] = { + "cortex-m55", + NULL +}; + static const uint32_t an505_oscclk[] = { 40000000, 24580000, @@ -802,12 +822,6 @@ static void mps2tz_common_init(MachineState *machine) int num_ppcs; int i; - if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); error_report("Invalid RAM size, should be %s", sz); @@ -1293,6 +1307,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mc->max_cpus = mc->default_cpus; mmc->fpga_type = FPGA_AN505; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mmc->scc_id = 0x41045050; mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->apb_periph_frq = mmc->sysclk_frq; @@ -1322,6 +1338,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mc->max_cpus = mc->default_cpus; mmc->fpga_type = FPGA_AN521; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mmc->scc_id = 0x41045210; mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->apb_periph_frq = mmc->sysclk_frq; @@ -1351,6 +1369,8 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) mc->max_cpus = mc->default_cpus; mmc->fpga_type = FPGA_AN524; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mmc->scc_id = 0x41045240; mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ mmc->apb_periph_frq = mmc->sysclk_frq; @@ -1385,6 +1405,8 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) mc->max_cpus = mc->default_cpus; mmc->fpga_type = FPGA_AN547; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"); + mc->valid_cpu_types = mps3tz_an547_valid_cpu_types; + mc->valid_cpu_models = mps3tz_an547_valid_cpu_models; mmc->scc_id = 0x41055470; mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index d92fd60684..b833029088 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -110,6 +110,36 @@ OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE) */ #define REFCLK_FRQ (1 * 1000 * 1000) +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL +}; + +static const char * const mps2_an386_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL +}; + +static const char * const mps2_an500_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m7"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "cortex-m3", + NULL +}; + +static const char * const mps2_an386_valid_cpu_models[] = { + "cortex-m4", + NULL +}; + +static const char * const mps2_an500_valid_cpu_models[] = { + "cortex-m7", + NULL +}; + /* Initialize the auxiliary RAM region @mr and map it into * the memory map at @base. */ @@ -140,12 +170,6 @@ static void mps2_common_init(MachineState *machine) DeviceState *armv7m, *sccdev; int i; - if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); error_report("Invalid RAM size, should be %s", sz); @@ -484,6 +508,8 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data) mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; mmc->fpga_type = FPGA_AN385; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mmc->scc_id = 0x41043850; mmc->psram_base = 0x21000000; mmc->ethernet_base = 0x40200000; @@ -498,6 +524,8 @@ static void mps2_an386_class_init(ObjectClass *oc, void *data) mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4"; mmc->fpga_type = FPGA_AN386; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); + mc->valid_cpu_types = mps2_an386_valid_cpu_types; + mc->valid_cpu_models = mps2_an386_valid_cpu_models; mmc->scc_id = 0x41043860; mmc->psram_base = 0x21000000; mmc->ethernet_base = 0x40200000; @@ -512,6 +540,8 @@ static void mps2_an500_class_init(ObjectClass *oc, void *data) mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7"; mmc->fpga_type = FPGA_AN500; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7"); + mc->valid_cpu_types = mps2_an500_valid_cpu_types; + mc->valid_cpu_models = mps2_an500_valid_cpu_models; mmc->scc_id = 0x41045000; mmc->psram_base = 0x60000000; mmc->ethernet_base = 0xa0000000; @@ -526,6 +556,8 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data) mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; mmc->fpga_type = FPGA_AN511; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mmc->scc_id = 0x41045110; mmc->psram_base = 0x21000000; mmc->ethernet_base = 0x40200000; diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 7b3106c790..725309514b 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -42,6 +42,16 @@ #define M2S010_ENVM_SIZE (256 * KiB) #define M2S010_ESRAM_SIZE (64 * KiB) +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "cortex-m3", + NULL +}; + static void emcraft_sf2_s2s010_init(MachineState *machine) { DeviceState *dev; @@ -55,12 +65,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) MemoryRegion *ddr = g_new(MemoryRegion, 1); Clock *m3clk; - if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, &error_fatal); memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); @@ -109,6 +113,8 @@ static void emcraft_sf2_machine_init(MachineClass *mc) mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)"; mc->init = emcraft_sf2_s2s010_init; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; } DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 6eeee57c9d..69d6735f27 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -102,6 +102,16 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE) /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m33"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "cortex-m33", + NULL +}; + static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ @@ -355,7 +365,6 @@ static void musca_init(MachineState *machine) { MuscaMachineState *mms = MUSCA_MACHINE(machine); MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms); - MachineClass *mc = MACHINE_GET_CLASS(machine); MemoryRegion *system_memory = get_system_memory(); DeviceState *ssedev; DeviceState *dev_splitter; @@ -366,12 +375,6 @@ static void musca_init(MachineState *machine) assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX); assert(mmc->num_mpcs <= MUSCA_MPC_MAX); - if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(mms->sysclk, SYSCLK_FRQ); mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); @@ -609,6 +612,8 @@ static void musca_class_init(ObjectClass *oc, void *data) mc->min_cpus = mc->default_cpus; mc->max_cpus = mc->default_cpus; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mc->init = musca_init; } diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 2aef579aac..23b5ab0ccc 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -55,6 +55,16 @@ static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "cortex-a9", + NULL +}; + static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc) { const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom; @@ -121,15 +131,8 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, uint32_t hw_straps) { NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); - MachineClass *mc = MACHINE_CLASS(nmc); Object *obj; - if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { - error_report("This board can only be used with %s", - mc->default_cpu_type); - exit(1); - } - obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", &error_abort, NULL); object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort); @@ -469,6 +472,8 @@ static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) mc->no_parallel = 1; mc->default_ram_id = "ram"; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; } /* diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 10653361ed..d13987deed 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -28,6 +28,16 @@ static struct arm_boot_info orangepi_binfo; +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "cortex-a7", + NULL +}; + static void orangepi_init(MachineState *machine) { AwH3State *h3; @@ -48,12 +58,6 @@ static void orangepi_init(MachineState *machine) exit(1); } - /* Only allow Cortex-A7 for this board */ - if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) { - error_report("This board can only be used with cortex-a7 CPU"); - exit(1); - } - h3 = AW_H3(object_new(TYPE_AW_H3)); object_property_add_child(OBJECT(machine), "soc", OBJECT(h3)); object_unref(OBJECT(h3)); @@ -118,6 +122,8 @@ static void orangepi_machine_init(MachineClass *mc) mc->max_cpus = AW_H3_NUM_CPUS; mc->default_cpus = AW_H3_NUM_CPUS; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mc->default_ram_size = 1 * GiB; mc->default_ram_id = "orangepi.ram"; } From patchwork Wed Jul 26 00:32:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 13327338 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 397ECEB64DD for ; Wed, 26 Jul 2023 00:35:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qOSUC-0002hb-Ld; Tue, 25 Jul 2023 20:34:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOSU4-0002NH-Ie for qemu-devel@nongnu.org; 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Tue, 25 Jul 2023 20:34:24 -0400 X-MC-Unique: L4uT3TutNh2ip98KgVrFtQ-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C6C668008A4; Wed, 26 Jul 2023 00:34:22 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.80]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5EEE54A9004; Wed, 26 Jul 2023 00:34:14 +0000 (UTC) From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, imammedo@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, pbonzini@redhat.com, shan.gavin@gmail.com Subject: [PATCH v2 8/8] hw/riscv/shakti_c: Check CPU type in machine_run_board_init() Date: Wed, 26 Jul 2023 10:32:05 +1000 Message-ID: <20230726003205.1599788-9-gshan@redhat.com> In-Reply-To: <20230726003205.1599788-1-gshan@redhat.com> References: <20230726003205.1599788-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set mc->valid_cpu_{types, models} so that the specified CPU type can be checked in machine_run_board_init(). We needn't to do the check by ourselves. Signed-off-by: Gavin Shan --- hw/riscv/shakti_c.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 12ea74b032..0bd59d47cd 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -28,6 +28,15 @@ #include "exec/address-spaces.h" #include "hw/riscv/boot.h" +static const char * const valid_cpu_types[] = { + RISCV_CPU_TYPE_NAME("shakti-c"), + NULL +}; + +static const char * const valid_cpu_models[] = { + "shakti-c", + NULL +}; static const struct MemmapEntry { hwaddr base; @@ -47,12 +56,6 @@ static void shakti_c_machine_state_init(MachineState *mstate) ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate); MemoryRegion *system_memory = get_system_memory(); - /* Allow only Shakti C CPU for this platform */ - if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) { - error_report("This board can only be used with Shakti C CPU"); - exit(1); - } - /* Initialize SoC */ object_initialize_child(OBJECT(mstate), "soc", &sms->soc, TYPE_RISCV_SHAKTI_SOC); @@ -85,6 +88,8 @@ static void shakti_c_machine_class_init(ObjectClass *klass, void *data) mc->desc = "RISC-V Board compatible with Shakti SDK"; mc->init = shakti_c_machine_state_init; mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C; + mc->valid_cpu_types = valid_cpu_types; + mc->valid_cpu_models = valid_cpu_models; mc->default_ram_id = "riscv.shakti.c.ram"; }