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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id z15-20020a05600c114f00b003fbb5506e54sm2443379wmz.29.2023.07.27.11.57.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 11:57:02 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v2 1/4] riscv: Improve flush_tlb() Date: Thu, 27 Jul 2023 20:55:50 +0200 Message-Id: <20230727185553.980262-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727185553.980262-1-alexghiti@rivosinc.com> References: <20230727185553.980262-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: D6B88A000C X-Rspam-User: X-Rspamd-Server: rspam04 X-Stat-Signature: iw66r44o9doo7i1bo816c3zoiozrkmon X-HE-Tag: 1690484223-397324 X-HE-Meta: U2FsdGVkX199wbqr/XSDItVeWOovP3hEyby25LKDkiKjeUznwOsg4JlUWnJOH0UZtngY+tusyKD8ocPC+x2QCmCXXE5CjSo99PMRzv0uIusYwoW1VHqntCKCID/KaI36sd2EP/LN5g2tZNzReN8+zXwyskCpDN1+o4Uetno2V2NkE7M+2Rqj4QII0y3Qo1xS75dxeqnvlOf7RNaYGCoFE9Y2uQ0du5An6e1bn0SozK2HIeTKWd3/Bd0t+GgadFROTUhws6SFDPFW1NajjZab7RinbM+jxaK6q3nUxLsGbZ5y+hBuhuqLwk3TmhgdiRgjz/crHnZtWf0/saNDL1eXYT8z9Q6M1pfn+thm1S3QRr11T/BAlQCK1KnIOxlVpY0BZBN87gLwMo7Mpdo8GMmpf8TBtsT287s08af24jnffKsRPz62EvNi1m3G7NQbaz3dlCouVBF8fIlP3kWDzfbvbidbkFznPhx4KWqE/nJAgpT4/cAXeFv+UM5FJbfHCARQwqGnMOHXvWw91YAnGZbd/lsO5pTl/ddjgRF2Vg4RQSbusnIs2ZBux36UdRmrig1gWiVHMRqU/JuX5tLeEKkN/C0cKu/BWcUDd0ppXEfK7ItRZ6jsrV3/W9P6AarCYuOPdlqwz7fwkQW6XD6XJuS6CpKeMnHqeLq2VVY7zazhtHRGYVBFM4LAtUVJrAkvEZDTNH4Z1HdRsmX4k1710excoSPljYUiF/gMfL8jofG8xymBfpqsARCL++t/sRzxS7ay0rZSJftTbdzscE+DqvZcDDPlaTSB1YOLr2tBBIy1jkVHHhVCielxIWE4m8lSborHjXG/0hU+6Bm+QsIUUMS1lhi8lw031L+SxzeLwHcJEQ6QNQQKkdLPBRw/JB3edzi0fQ5hBxFwMSzpjboDSdbeqC8ZYgSfn2ygZj1Ub0cVNRxfv7LrCrFKeNoetDpES9HMR7KxQec8SzYLRaT8gyA wZJM76Tc xIFAnpcx91G+badQKXBmcrvAc/58QdD71DgJjok9xL1jGUKmN4RImKAc76Bv9GBbe+c2fPhksS3cAiBj9MUpDBqYZL0tMipNgS7GDwPzTcwDjZXGow/5kR18dpfLRG3A3P7Azit2oGbmfmsfp1HBDWCkqNEFWCA0ZkWJNsWXq+/b1l7VJm+ju5WA2FhZf1i0L8vz51DxXOyJqJ9JNbFtb5fsQLlwHWocEUDy/Gw1Ddi3lw12l8rAthtK0t6Tq3+SpH5yf1Q+BM227dNX8ONFnVit0oyheDOUw48aO7JeUvYQ1vxHRZn1pn6cqEnuJfOfJQQkJd4HTbrXe3QVUAt8cWMb0jqqzZXn7XQzGJxHVGJyXqJpPZ6mXii75AO3CtsWYMDeX7TNKgc146yowALST8J1+lIuLCpy5kARPcoUUZyuZGcc1UwDpRaF6RC6YAXY+lOgbgpODh5fzqiZwdu7NsSV5YO+vNaOHDw1Hdcl/UQjvuhcl/YRebX6YxQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: For now, flush_tlb() simply calls flush_tlb_mm() which results in a flush of the whole TLB. So let's use mmu_gather fields to provide a more fine-grained flush of the TLB. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- arch/riscv/include/asm/tlb.h | 8 +++++++- arch/riscv/include/asm/tlbflush.h | 3 +++ arch/riscv/mm/tlbflush.c | 7 +++++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.h index 120bcf2ed8a8..1eb5682b2af6 100644 --- a/arch/riscv/include/asm/tlb.h +++ b/arch/riscv/include/asm/tlb.h @@ -15,7 +15,13 @@ static void tlb_flush(struct mmu_gather *tlb); static inline void tlb_flush(struct mmu_gather *tlb) { - flush_tlb_mm(tlb->mm); +#ifdef CONFIG_MMU + if (tlb->fullmm || tlb->need_flush_all) + flush_tlb_mm(tlb->mm); + else + flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end, + tlb_get_unmap_size(tlb)); +#endif } #endif /* _ASM_RISCV_TLB_H */ diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index a09196f8de68..f5c4fb0ae642 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -32,6 +32,8 @@ static inline void local_flush_tlb_page(unsigned long addr) #if defined(CONFIG_SMP) && defined(CONFIG_MMU) void flush_tlb_all(void); void flush_tlb_mm(struct mm_struct *mm); +void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, + unsigned long end, unsigned int page_size); void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); @@ -52,6 +54,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, } #define flush_tlb_mm(mm) flush_tlb_all() +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() #endif /* !CONFIG_SMP || !CONFIG_MMU */ /* Flush a range of kernel pages */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 77be59aadc73..fa03289853d8 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -132,6 +132,13 @@ void flush_tlb_mm(struct mm_struct *mm) __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } +void flush_tlb_mm_range(struct mm_struct *mm, + unsigned long start, unsigned long end, + unsigned int page_size) +{ + __flush_tlb_range(mm, start, end - start, page_size); +} + void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); From patchwork Thu Jul 27 18:55:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13330587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FDEDC001DC for ; Thu, 27 Jul 2023 18:58:07 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 26C196B0072; Thu, 27 Jul 2023 14:58:07 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 1F5BF6B0074; Thu, 27 Jul 2023 14:58:07 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 0BDFE6B0075; Thu, 27 Jul 2023 14:58:07 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id EF3D86B0072 for ; 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id a1-20020a056000050100b003141f96ed36sm2840938wrf.0.2023.07.27.11.58.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 11:58:03 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v2 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Date: Thu, 27 Jul 2023 20:55:51 +0200 Message-Id: <20230727185553.980262-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727185553.980262-1-alexghiti@rivosinc.com> References: <20230727185553.980262-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: CE21B20005 X-Rspam-User: X-Stat-Signature: e63iocgeny4bwmypydajt5y8amhpaqx3 X-Rspamd-Server: rspam03 X-HE-Tag: 1690484284-811590 X-HE-Meta: U2FsdGVkX19HaklObAFCV48bCCZMTDCzGhyuOs80qo9fGc6K4m/m9o4W5fY0XarLhQGBLJjXGRULjPFmLJa3+uZZ0hPPJxmtW+UrCgyTfJN9ujY1YpDpBrz9Gui7Ehxi6afRMHI+PLm/CrEiS8SsB8nJdifaduWDhAF7sTttDCq8C2aIr0IKhh2aE65GsYk+HVU6t6JgGW4ooQYnqrBixK+Q7jCD/kfLmafcBUd6/VDCrxLUnWt2TOc9h0Ip68BEmGcHawyiczgj2rXzuL7E2bRJ/QgZFiVpos5tGsxlZ6YWMP1wuzpL8EL3qTL7qo9Keu6+bc9j49Nn203Dq9DWSQ4oCfwl34ZKAZtzS8XQARv+/+0sCrrGXqsifp2y0WO0ZKbSuCw89a7lx0diYfz+dNLa8HiogSQzzBAsxk2Q2/zIDa5LJsCp5UCt0CE1r912QmocXvaQ7tGSx75geR+kTdfNm2wNQKPlsxtGUixzgKPxx/EgThyVmRrRxzSLdqcTZ3uH5oE3FXlCDD26LuI16W1xvSYnFrsinu0onAY1669V+kDqZs72hB9YeUOHOaF+zFPMoGJiIVGNmsuSgj9VapEAsxCI2+vksEcvNabTUPhpeo8ubaaEM1us3KlmICvx+bhhNu43mNAaPGjUf+byzuiX1oSq5pnlPHMEdJxuZuxefjY3YVOJzsz+zALIFnteBxA9Gyc2D9aYmBGMEVxOBwUGinWc7SJA4Xjno8sEy0mbNsIbHlhluDP5Q79ttcqwHdLLJhntQoYi7+jjNP/O4/PZqvrAwY4+guxg9DOapbhiQ2RmCyAOclZnD9A2siD3yRtFxyjA3QWAXcKjOr1FWvbc0owCsheAmoy3+5zIN7f2oZRKOd3UJxXZ2YTRnvtlpSPE/Lwkq36JpvK7e3K+QKcpCxKZMRaWio0IOddXaWr/hp9DMMPFVkZl2/bm0qZuMeIyVzIwhMBKcpmN2xO o9H7Mhgg QFqk5zXHpfkQn+YZyuKvDjfvmOkzdViO8Txelnpao/kO+ka9gsG6jUkMwa396PydBQwGOe4GgGyRjz1s5tdxyqhbGDfON2IYoMmhYKC/uiRJ3m2MoGHOL+ZAKiKRu14AUNltKUyWMLU0spmDJJj70ntJuW3pL0vfKIS+/TghPMfZVvy7WXmZQYzWbIPKfFs7eSLi56LFmvYJbyPCQo+wS+xs9msmRE7j6tvcwq1yB5Axm47WPKW+4ueFXNZH8SNsEjDgQmy1YHhhUFmBKveKb0rasYolaEfbwXZipeBaHt3JchbFNgWPhUGks9eWOj+0mAHlbGZm01hP76deXwQjKY51pPzhFJkmmlPbuiOt9Qz+gKUxDVKdJqMvopzUchSaZWdA4x5BBSy2MbBD9sn39eXnQoEBpdFSTvnFXtvu8zGZg+S+aPZvx2yLeX6QNLxRpV7i4KZswRzgQ3/QE9Zo2gXUZg+azpXUkWEIUgwIpsN6Y4/aJ4Yr0dajnPQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: flush_tlb_range() uses a fixed stride of PAGE_SIZE and in its current form, when a hugetlb mapping needs to be flushed, flush_tlb_range() flushes the whole tlb: so set a stride of the size of the hugetlb mapping in order to only flush the hugetlb mapping. Note that THPs are directly handled by flush_pmd_tlb_range(). Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- arch/riscv/mm/tlbflush.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index fa03289853d8..3e4acef1f6bc 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -147,7 +148,14 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); + unsigned long stride_shift; + + stride_shift = is_vm_hugetlb_page(vma) ? + huge_page_shift(hstate_vma(vma)) : + PAGE_SHIFT; + + __flush_tlb_range(vma->vm_mm, + start, end - start, 1 << stride_shift); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, From patchwork Thu Jul 27 18:55:52 2023 Content-Type: text/plain; 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id 2-20020a05600c22c200b003fa96620b23sm5376517wmg.12.2023.07.27.11.59.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 11:59:04 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Date: Thu, 27 Jul 2023 20:55:52 +0200 Message-Id: <20230727185553.980262-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727185553.980262-1-alexghiti@rivosinc.com> References: <20230727185553.980262-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspam-User: X-Stat-Signature: omaaeqiaqta6opdfknab4kmi1pjm4brb X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: C4003C001A X-HE-Tag: 1690484345-694663 X-HE-Meta: U2FsdGVkX19789QCtrwLn36cYJIFAFu/23YFE1Hvkv1izOtXdltir/U6K70G2dbFTMnyEwTinCRzZAgHCA7sW29ymtjUWZd6ElQ8cSAOsN7nSKDHLNTcVefVnTF8STD4QCDHu4MIkYSnF4JTpklhe3507jD7XBhBV1sotb3PLVMwnWE/8k5LxVGzAyBBo7joItodJwuFpwRlM0oGQal1r/eAMMz7Aug++e9Go73l2kWXJiybo9aoHGJWXUb/cW/HOi6oUVHShtUqVSvLNwWYBBEmhO35K+176FRtdYu14ZNUL0jcbs3s7Di9D6F9e1+DWTY/vM+toqJ3gz0pkZykfJez9zBFUFet5qF7JzyTvktPzW3G6wQUI5Yh5lRztgoLHkjFlvYD7cdmZmovJYkBsT1HKQzXTXwUM+91NTAAfe1uZqBp49EIPB3dxwudDN564yWPua+X+/uVnqM99tIeDHCB/BSeR0cUXj5AgTIyMLPVvamgSqd4L9EB5WICXjBX64LIDsifIjc0VsABkkMF7AUbgAihFdyxGdb4eIsw8xxVDZyqKfTm5gKDrh5EAt3Kl8IRCWQjlQwOyTOZQGzWM9ugkoLpnP9JBPLsqoWPtC/Q9WCRdmF3+ryB4uBaTh/bz5uQ8ewctWLcYu65q6i/rS98wrZGLIvKtXrMH7ym0z2PKfw6nxCSTG6pbLL8exH9JQTf63h+4wpvqnA1Kz6Bu8IoaFa/j0WQ0wEE65Iv34UBj/Spz7IPxFrvfMBuFWSEu7qkTY1u7FiWmVzU/TEVcBHCezwq4PufuG+e5mWfEeLrb6JLTeNtrcLSm5Zcc5PEjCdJPvTlE8jd3mJJLRHYvzRfBMVvqSQjlRyV3N0smkP50TQGfQxQzHKkvtD8dEvqdmzQ9mFiYQJSN54/RjrxEWhHXMcxjD/hpKfbDctLTls93YktMsu+HP6w0kFdwMpmk/Oco/nvmQd80ZH9xWe h5lplMik LHFaKK6x+O5AOHfO/iKj+Zvc2VtZB/u+SJbfthyQcVNZHvLgdeM/OX2V1KoktMLUpagHpTyAxpgGrS9t31++aoc7Cqn4mM0hGCFI04a7sLPxlsHYyAK5vFL98Q4Tz5iraMw1bUq4U6KC0f1gQLUt4kru8MeLga8n9jihqh2NdJcOj9uyObbfJDPuKKzKdPiNzA+a18eOKcCa4kQL4IxiamQCIfwEdRsEAUDPM0Qj4MN4M4ev8kGi3WkjeQDcLruNrQIev7YXX5JVJM4e70A4+bqxSjkYhO9bOjegqlb0agc3erdxEtsW7IlDOMLiz780NS6Gl7ilb6133clNmkelVYhk8S5X7JXLrkpBExw9RAGG4IqygYkv6pvDWeDpICv0WxhdG3G7A8lM/qTf79FfyeTHAcGp8pz6mD4Ep/ANYrpOiCAZD4Qaay8VJIDQdZU/6nt8kFOLkUJkfvPRwLnctSDFSL5FPADDMq+y5QaR5zpNABROmTcpJ4OI/L873nWe0RHOOeawuCBnTGoSgwfHRRCAvnTvyL8iQtR+sJcANTr9/8uc= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Currently, when the range to flush covers more than one page (a 4K page or a hugepage), __flush_tlb_range() flushes the whole tlb. Flushing the whole tlb comes with a greater cost than flushing a single entry so we should flush single entries up to a certain threshold so that: threshold * cost of flushing a single entry < cost of flushing the whole tlb. This threshold is microarchitecture dependent and can/should be overwritten by vendors. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- arch/riscv/mm/tlbflush.c | 41 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 3e4acef1f6bc..8017d2130e27 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -24,13 +24,48 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, : "memory"); } +/* + * Flush entire TLB if number of entries to be flushed is greater + * than the threshold below. Platforms may override the threshold + * value based on marchid, mvendorid, and mimpid. + */ +static unsigned long tlb_flush_all_threshold __read_mostly = 64; + +static void local_flush_tlb_range_threshold_asid(unsigned long start, + unsigned long size, + unsigned long stride, + unsigned long asid) +{ + u16 nr_ptes_in_range = DIV_ROUND_UP(size, stride); + int i; + + if (nr_ptes_in_range > tlb_flush_all_threshold) { + if (asid != -1) + local_flush_tlb_all_asid(asid); + else + local_flush_tlb_all(); + return; + } + + for (i = 0; i < nr_ptes_in_range; ++i) { + if (asid != -1) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_page(start); + start += stride; + } +} + static inline void local_flush_tlb_range(unsigned long start, unsigned long size, unsigned long stride) { if (size <= stride) local_flush_tlb_page(start); - else + else if (size == (unsigned long)-1) local_flush_tlb_all(); + else + local_flush_tlb_range_threshold_asid(start, size, stride, -1); + } static inline void local_flush_tlb_range_asid(unsigned long start, @@ -38,8 +73,10 @@ static inline void local_flush_tlb_range_asid(unsigned long start, { if (size <= stride) local_flush_tlb_page_asid(start, asid); - else + else if (size == (unsigned long)-1) local_flush_tlb_all_asid(asid); + else + local_flush_tlb_range_threshold_asid(start, size, stride, asid); } static void __ipi_flush_tlb_all(void *info) From patchwork Thu Jul 27 18:55:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13330589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B01C001DC for ; Thu, 27 Jul 2023 19:00:10 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 94DAB6B0072; Thu, 27 Jul 2023 15:00:09 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 8FDC36B0074; Thu, 27 Jul 2023 15:00:09 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 7C6286B0075; Thu, 27 Jul 2023 15:00:09 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0014.hostedemail.com [216.40.44.14]) by kanga.kvack.org (Postfix) with ESMTP id 6CC7A6B0072 for ; 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id p1-20020a7bcc81000000b003fa96fe2bebsm2470792wma.41.2023.07.27.12.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 12:00:05 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v2 4/4] riscv: Improve flush_tlb_kernel_range() Date: Thu, 27 Jul 2023 20:55:53 +0200 Message-Id: <20230727185553.980262-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727185553.980262-1-alexghiti@rivosinc.com> References: <20230727185553.980262-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 41E3A14002F X-Stat-Signature: formk93dmfjie867xem3fga4pigonk1b X-HE-Tag: 1690484406-927216 X-HE-Meta: U2FsdGVkX19ML8UclaId2vxTRBeyYc/F61dcAMj+EXH8UKPlL7fGa5cCfWngKicHIN9fErI2YLzULkegjqrRmYwaFs/XdK5U1wGOinCeXJLB9JFvJJSi39MsidyZ0BN2WgrNu9rAYH6Cg6zoBMMHoPIg3dsWJOTQhWDzIWJGBjiiACLoSW/jrMsWjamnGUPB5WgemKSvz/j1i9XYmawJ4llYGiec5SD9rlVROX9xfJ3ALgarurHBmM1rWAaPupmoiDxF2Dty7HkqqrNladSabxpb8MjUuf744mnyYW5HSJunRyATCUfECn0+rZQ0j2NOMBwxFZK1nRGmMhw8YoZsiFMs3TPJZ56KfCq56KJ4zOOWAN8mSW8koC1LXw7K/IfcCSwyuPxlVTqz485BHaBIaU7IrBaF6rUiAYY9Tw6Vj3bxGQ4pvAr1wAdWgscSsFbOvay9R+6dtF3pVMIfh8roaBo+Yq6G/8vblYYlxSj9nl++OGpMejw06GnFHjCqmsIxHO+aPQgFsGhVwQJLD79FT6fCrbUrxeTxjSRPqYC5V/wNiwufPfoMZ2aHtWPSQKzlyyvvwNuh2Q3PmqIWFCxOBJtxVjiW28yplQUnhGfTN7SgcxfUFqThFYU/kfkAQ85li4W63Tho/GgS9Gv+EDPaoZMcq+AtgufQggf+jxnSRH7LOt7G9FbmUzhgRxi+gzFDFJUdsHJQmVcepPfhoba/jcTwBbg6HvohlV1uD+cLYxZ8U3HHPyIJzXZpZzUmUTCtVJ75PctvG0ifKLm6SeM7naaNhqzHb05uScG/6jTiLsHYuJfJGuCYn7+I5eLG5C1LsDzPnEkq1sHVWjTeC3bNUdlGJmj9AkLoZ2t6jiSCp1ej7Z1TxYlLERXhd1/DlUJZZjE+p3CLTkoRQGPxvte07MDVHHffvlpXX/KorJ0XIQj63k4/hjOVPhxSJy4DccmgTZ5v25phFER3qY6a/Iw niRoiYjS SaBMT//uPOcbsk1x/ySEsHgdY6BJhI2N9TrkdAkWK8ENZiSSIIvE1wofB4Vj42/vWnQbwrK/CkYNdN9kCEZSCGrONNasGZAgt48KMpr0DA8LmMYkz50eoy0aSd0hs5KReuZupBeV9NiZvrZq6TyEctPCxNaCF9ThuElQ8V1pqVYdsAllYXT3bsGd8wzW+gFstMvtWzXnSGiypSZi2qrOP9HL679PWMxNxXi2sDKqPJrrM69TIBFshqHtPszGlXUvRRHPVXCmHMisxinWoaKIMPK1ASmstM6B79SnCP3SmC3c7lGW/j0vh2abKS3HqK4bWlFb4lwvvbFv4lHGb/NtK65QP/hsTR60TXacqIDszahfzvdcxqFGS4hRicGEu4wOLJpQd9mdmTt/vZKdjg19D5In0YKz6PTARCFGig9XcSYajGq19dLwY5ZeAFwp6NjWQz+QiyiOAe3qKAhgFA75w31Ac6kLTGLSPVxH667bJ2A/2x8puRb6J2Ta4Yg== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: This function used to simply flush the whole tlb of all harts, be more subtile and try to only flush the range. The problem is that we can only use PAGE_SIZE as stride since we don't know the size of the underlying mapping and then this function will be improved only if the size of the region to flush is < threshold * PAGE_SIZE. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- arch/riscv/include/asm/tlbflush.h | 11 +++++----- arch/riscv/mm/tlbflush.c | 35 +++++++++++++++++++++++-------- 2 files changed, 32 insertions(+), 14 deletions(-) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index f5c4fb0ae642..7426fdcd8ec5 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -37,6 +37,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); +void flush_tlb_kernel_range(unsigned long start, unsigned long end); #ifdef CONFIG_TRANSPARENT_HUGEPAGE #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, @@ -53,15 +54,15 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, local_flush_tlb_all(); } -#define flush_tlb_mm(mm) flush_tlb_all() -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() -#endif /* !CONFIG_SMP || !CONFIG_MMU */ - /* Flush a range of kernel pages */ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - flush_tlb_all(); + local_flush_tlb_all(); } +#define flush_tlb_mm(mm) flush_tlb_all() +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() +#endif /* !CONFIG_SMP || !CONFIG_MMU */ + #endif /* _ASM_RISCV_TLBFLUSH_H */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 8017d2130e27..96aeacb269d5 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -117,18 +117,27 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long size, unsigned long stride) { struct flush_tlb_range_data ftd; - struct cpumask *cmask = mm_cpumask(mm); - unsigned int cpuid; + struct cpumask *cmask, full_cmask; bool broadcast; - if (cpumask_empty(cmask)) - return; + if (mm) { + unsigned int cpuid; + + cmask = mm_cpumask(mm); + if (cpumask_empty(cmask)) + return; + + cpuid = get_cpu(); + /* check if the tlbflush needs to be sent to other CPUs */ + broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; + } else { + cpumask_setall(&full_cmask); + cmask = &full_cmask; + broadcast = true; + } - cpuid = get_cpu(); - /* check if the tlbflush needs to be sent to other CPUs */ - broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; if (static_branch_unlikely(&use_asid_allocator)) { - unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask; + unsigned long asid = mm ? atomic_long_read(&mm->context.id) & asid_mask : 0; if (broadcast) { if (riscv_use_ipi_for_rfence()) { @@ -162,7 +171,8 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, } } - put_cpu(); + if (mm) + put_cpu(); } void flush_tlb_mm(struct mm_struct *mm) @@ -194,6 +204,13 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, __flush_tlb_range(vma->vm_mm, start, end - start, 1 << stride_shift); } + +void flush_tlb_kernel_range(unsigned long start, + unsigned long end) +{ + __flush_tlb_range(NULL, start, end, PAGE_SIZE); +} + #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)