From patchwork Thu Jul 27 21:20:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82D67EB64DD for ; Thu, 27 Jul 2023 21:22:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229448AbjG0VWp (ORCPT ); Thu, 27 Jul 2023 17:22:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230349AbjG0VWn (ORCPT ); Thu, 27 Jul 2023 17:22:43 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32A4A10CB; Thu, 27 Jul 2023 14:22:42 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-55b5a3915f5so827286a12.0; Thu, 27 Jul 2023 14:22:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690492961; x=1691097761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UewGh9LKW89TdE00XXwcTXeHiWhdfYrkJoWhpa0ZANk=; b=O0IcYaTPHkNnvM0fnvbUxovzWJvd2W+AnTWNs8NMJ6BExBcWRCPEbU62NUSYwuJnGg 9JOerHCklKo0agB/xZ9uSCQgjj65P1SjyvM32c45TVjmpWw78PCb0PHWx4rI/ItqzEj2 xPHt/9bl9ExfTwVdIdqqZzRMXwHn5Qook1Oaj8bg58B4v/8czeH7PKwq8iBXPFiyZbRF ku4SVEhBqqaanIE5/HvDwTr3iBvg5VBs80DPqq8ZCMZBUmnntChsqmXPgRGnq8CQA3cG yHX0Hb/9MCxJ63Mb77z7qmHwFsFlZmLNKflhB+uTaMZCXo4cZ+Ou0T8WLtR5S7cr/Wub 5DZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690492961; x=1691097761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UewGh9LKW89TdE00XXwcTXeHiWhdfYrkJoWhpa0ZANk=; b=horrgKjEoof2vHyGSWCflIPosEwIjR1Sq1n9hkVFX/l0C96jVSreJdrkesQdPMsr9p cXrSuLZXxAyrMJZCm7JT3D1tzvXTniOVjKsaEH/63UaILh9I7e32wIEPBndcYgYeaqZ5 Ar7srXqrd3BeXmLyhZ4tS8vzsxzSRz7GtQETPq1KFiw59fzcb+jvtIPbAcheOPgn49UU RWMQJUsrlzR3vtTdDjna0BuBkKo69BZRjiYP+XHSG340dclCG7t9AcygoA4fFq+TK8DL RvBPehW1K9xftcJsRS89mYOIudsTds+13cZLyrGUlpU4hCX1751kPyB9Pf0RxSzyJbvg iAFg== X-Gm-Message-State: ABy/qLYVq+js9T+WEUbPA/BhzkzBK8jEgFhr7CgZbnAM+ocr7X43LTmW OstGo39e9rIhw9EMPUQk2og= X-Google-Smtp-Source: APBJJlG0OstN/eWueCdI0VCXlM2r2ClQvzKOo4ZoisA5yFjYrklqM2mNPJ9btiQQJxzR+bw9X9hMSA== X-Received: by 2002:a17:903:181:b0:1b8:7625:3042 with SMTP id z1-20020a170903018100b001b876253042mr627355plg.10.1690492961518; Thu, 27 Jul 2023 14:22:41 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:69d1:d8aa:25be:a2b6]) by smtp.gmail.com with ESMTPSA id p16-20020a170902e75000b0019ee045a2b3sm2064466plf.308.2023.07.27.14.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 14:22:40 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Johan Hovold , Bjorn Andersson , Rob Herring , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 01/13] drm/msm/adreno: Remove GPU name Date: Thu, 27 Jul 2023 14:20:06 -0700 Message-ID: <20230727212208.102501-2-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark No real need to have marketing names in the kernel. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 25 ---------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++++------ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 3 files changed, 5 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index ce8d0b2475bf..326912284a95 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -24,7 +24,6 @@ static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), .revn = 200, - .name = "A200", .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", [ADRENO_FW_PFP] = "yamato_pfp.fw", @@ -35,7 +34,6 @@ static const struct adreno_info gpulist[] = { }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), .revn = 201, - .name = "A200", .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", [ADRENO_FW_PFP] = "yamato_pfp.fw", @@ -46,7 +44,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), .revn = 220, - .name = "A220", .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw", [ADRENO_FW_PFP] = "leia_pfp_470.fw", @@ -57,7 +54,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), .revn = 305, - .name = "A305", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -68,7 +64,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 0, 6, 0), .revn = 307, /* because a305c is revn==306 */ - .name = "A306", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -79,7 +74,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), .revn = 320, - .name = "A320", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -90,7 +84,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), .revn = 330, - .name = "A330", .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw", [ADRENO_FW_PFP] = "a330_pfp.fw", @@ -101,7 +94,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), .revn = 405, - .name = "A405", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -112,7 +104,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), .revn = 420, - .name = "A420", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -123,7 +114,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), .revn = 430, - .name = "A430", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -134,7 +124,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), .revn = 506, - .name = "A506", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -152,7 +141,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), .revn = 508, - .name = "A508", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -169,7 +157,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), .revn = 509, - .name = "A509", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -187,7 +174,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), .revn = 510, - .name = "A510", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -202,7 +188,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), .revn = 512, - .name = "A512", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -219,7 +204,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 3, 0, 2), .revn = 530, - .name = "A530", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -238,7 +222,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), .revn = 540, - .name = "A540", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -256,7 +239,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), .revn = 610, - .name = "A610", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", }, @@ -268,7 +250,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, - .name = "A618", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin", @@ -279,7 +260,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, - .name = "A619", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a619_gmu.bin", @@ -292,7 +272,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, - .name = "A630", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin", @@ -305,7 +284,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), .revn = 640, - .name = "A640", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a640_gmu.bin", @@ -318,7 +296,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), .revn = 650, - .name = "A650", .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw", [ADRENO_FW_GMU] = "a650_gmu.bin", @@ -332,7 +309,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), .revn = 660, - .name = "A660", .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin", @@ -357,7 +333,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), .revn = 680, - .name = "A680", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a640_gmu.bin", diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 5c5901d65950..e3cd9ff6ff1d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1105,14 +1105,11 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); - gpu_name = adreno_gpu->info->name; - if (!gpu_name) { - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", - rev->core, rev->major, rev->minor, - rev->patchid); - if (!gpu_name) - return -ENOMEM; - } + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", + rev->core, rev->major, rev->minor, + rev->patchid); + if (!gpu_name) + return -ENOMEM; adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index cf45007400c8..6830c3776c2d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -61,7 +61,6 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; struct adreno_info { struct adreno_rev rev; uint32_t revn; - const char *name; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; u64 quirks; From patchwork Thu Jul 27 21:20:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10505EB64DD for ; Thu, 27 Jul 2023 21:23:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229870AbjG0VXE (ORCPT ); Thu, 27 Jul 2023 17:23:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229683AbjG0VWt (ORCPT ); Thu, 27 Jul 2023 17:22:49 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FE791B8; Thu, 27 Jul 2023 14:22:48 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-68706b39c4cso503411b3a.2; Thu, 27 Jul 2023 14:22:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690492968; x=1691097768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=axIy3Rca2QfM0C9hEzlec+etM4W6UePiA7KJJTh2OkA=; b=LgIjozM1Uyg2bT4r5wPkfUE6W+GvPKS/w9BVSZJVUmPPRwq6LO6nm6l9MbgfhoMMuC DP2Q3ea/KkswMfOTfJ78wtL77CqYIrqxNqKZUBIi9L2HP93xarqpOl41BayQoFQJaNar DxUzhRiaPtcO1aCzU0XCav0VgkiY5BMNoXioNq4OTkHC8qsCXRMYQT12V4/oKVni/S6q 0p3MDSLO3VlINWJGRHT/5XjIJ0eEu1hAYyJLCu2nbE463gdHDqFIrIACjWo1Y4mlD1/m KNNsOSzerLgiI6n5ubzrkzGKQiB8zJJ4TkXFy6tlGSF6y8iVlVgvTyHnIFH3THqK6W9F mADQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690492968; x=1691097768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=axIy3Rca2QfM0C9hEzlec+etM4W6UePiA7KJJTh2OkA=; b=CR5qk75k67SkkJViFruyAAUvuqUjnRXfOJj6X3PXtMK9ksv2+TC7NWPYIWEWtAwOHE p5MEI37Kb8cccuSG0igmgdC1cOHQ4LrgHt1hY4QsX8oa1M9GGYWENeIEIWvlnquhx2UM DhnnaxaifVUl8swPl24ACod5YE3HPAID9pAG69aOMfX6PUj+Vho6QrNuhOKyh6Fxd6gu Q/bauIUKm6v5uJd0pWP7OLcllLaR/FSHkGYuI40WrSEE30anI6To4vPKNXsz6IgtXvZS +QZZsKhpeWW+AJSQjPxk+RuEfmIX0lsFDYnYQiVAXZXkia80ZNO95WSKDEDGKemObhaZ TsCA== X-Gm-Message-State: ABy/qLaswsGs+uQyBHRyP447sDJ/njk456OpG/4fV+T2mEwk/eNZFfio VOy0j8TIiGDXlikm90BGsQ8= X-Google-Smtp-Source: APBJJlH7YiZYm/Vwmtw3rcot9NbVZnPbQjFgltrXRgf4FeAr4TtCZ+MFouwajIK8cLS4/MzDV+jOfQ== X-Received: by 2002:a05:6a20:3d87:b0:126:a5e3:3927 with SMTP id s7-20020a056a203d8700b00126a5e33927mr317087pzi.8.1690492967798; Thu, 27 Jul 2023 14:22:47 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:69d1:d8aa:25be:a2b6]) by smtp.gmail.com with ESMTPSA id c29-20020a63725d000000b005348af1b84csm1973987pgn.74.2023.07.27.14.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 14:22:47 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Mukesh Ojha , Elliot Berman , Adam Skladowski , Douglas Anderson , Bjorn Andersson , Jernej Skrabec , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 02/13] drm/msm/adreno: Remove redundant gmem size param Date: Thu, 27 Jul 2023 14:20:07 -0700 Message-ID: <20230727212208.102501-3-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Even in the ocmem case, the allocated ocmem buffer size should match the requested size. v2: Move stray hunk to previous patch, make OCMEM size mismatch an error condition. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index c67089a7ebc1..50ee03bc94b4 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu) A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT); for (i = 3; i <= 5; i++) - if ((SZ_16K << i) == adreno_gpu->gmem) + if ((SZ_16K << i) == adreno_gpu->info->gmem) break; gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index a99310b68793..f0803e94ebe5 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, - 0x00100000 + adreno_gpu->gmem - 1); + 0x00100000 + adreno_gpu->info->gmem - 1); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) || diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b3ada1e7b598..edbade75020f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000); gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, - 0x00100000 + adreno_gpu->gmem - 1); + 0x00100000 + adreno_gpu->info->gmem - 1); } gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index e3cd9ff6ff1d..ef98d51d237f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = adreno_gpu->info->revn; return 0; case MSM_PARAM_GMEM_SIZE: - *value = adreno_gpu->gmem; + *value = adreno_gpu->info->gmem; return 0; case MSM_PARAM_GMEM_BASE: *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; @@ -1041,14 +1041,16 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, return PTR_ERR(ocmem); } - ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem); + ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem); if (IS_ERR(ocmem_hdl)) return PTR_ERR(ocmem_hdl); adreno_ocmem->ocmem = ocmem; adreno_ocmem->base = ocmem_hdl->addr; adreno_ocmem->hdl = ocmem_hdl; - adreno_gpu->gmem = ocmem_hdl->len; + + if (WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem)) + return -ENOMEM; return 0; } @@ -1097,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->gmem = adreno_gpu->info->gmem; adreno_gpu->revn = adreno_gpu->info->revn; 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Thu, 27 Jul 2023 14:22:51 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Douglas Anderson , Bjorn Andersson , Jernej Skrabec , Elliot Berman , Rob Herring , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 03/13] drm/msm/adreno: Remove redundant revn param Date: Thu, 27 Jul 2023 14:20:08 -0700 Message-ID: <20230727212208.102501-4-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark This just duplicates what is in adreno_info, and can cause confusion if used before it is set. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 -- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 +++++++++------------- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index edbade75020f..5ba8b5aca502 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2484,8 +2484,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(-EINVAL); /* Assign these early so that we can use the is_aXYZ helpers */ - /* Numeric revision IDs (e.g. 630) */ - adreno_gpu->revn = info->revn; /* New-style ADRENO_REV()-only */ adreno_gpu->rev = info->rev; /* Quirk data */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ef98d51d237f..f4d45534dd7f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1099,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev; if (adreno_read_speedbin(dev, &speedbin) || !speedbin) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index aaf09c642dc6..d31e2d37c61b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -77,7 +77,6 @@ struct adreno_gpu { struct msm_gpu base; struct adreno_rev rev; const struct adreno_info *info; - uint32_t revn; /* numeric revision name */ uint16_t speedbin; const struct adreno_gpu_funcs *funcs; @@ -147,10 +146,9 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return gpu->revn == revn; + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->revn == revn; } static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) @@ -160,18 +158,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return (gpu->revn < 300); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return (gpu->info->revn < 300); } static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return (gpu->revn < 210); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return (gpu->info->revn < 210); } static inline bool adreno_is_a225(const struct adreno_gpu *gpu) From patchwork Thu Jul 27 21:20:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7DD7C00528 for ; Thu, 27 Jul 2023 21:23:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231339AbjG0VXF (ORCPT ); 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Thu, 27 Jul 2023 14:22:56 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Douglas Anderson , Bjorn Andersson , Johan Hovold , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 04/13] drm/msm/adreno: Use quirk identify hw_apriv Date: Thu, 27 Jul 2023 14:20:09 -0700 Message-ID: <20230727212208.102501-5-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Rather than just open coding a list of gpu-id matches. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +-- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5ba8b5aca502..6f8c4381fa4a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2489,8 +2489,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* Quirk data */ adreno_gpu->info = info; - if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) - adreno_gpu->base.hw_apriv = true; + adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); a6xx_llc_slices_init(pdev, a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 326912284a95..f469f951a907 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -302,6 +302,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, @@ -315,6 +316,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg, @@ -327,6 +329,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, @@ -350,6 +353,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index d31e2d37c61b..a7c4a2c536e3 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -32,6 +32,7 @@ enum { #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) +#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) struct adreno_rev { uint8_t core; From patchwork Thu Jul 27 21:20:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 782E3C04A94 for ; Thu, 27 Jul 2023 21:23:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230102AbjG0VXK (ORCPT ); Thu, 27 Jul 2023 17:23:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231829AbjG0VXI (ORCPT ); Thu, 27 Jul 2023 17:23:08 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9393830E2; Thu, 27 Jul 2023 14:23:01 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6862842a028so1122423b3a.0; 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With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index f469f951a907..3c531da417b9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, @@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .hwcg = a630_hwcg, @@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, @@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, @@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg, @@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, @@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, @@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, @@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - if (config.rev.core >= 6) - if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) - priv->has_cached_coherent = true; + priv->has_cached_coherent = + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && + !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index a7c4a2c536e3..e08d41337169 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -33,6 +33,7 @@ enum { #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) struct adreno_rev { uint8_t core; From patchwork Thu Jul 27 21:20:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14BDAEB64DD for ; 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Thu, 27 Jul 2023 14:23:04 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:69d1:d8aa:25be:a2b6]) by smtp.gmail.com with ESMTPSA id g26-20020a62e31a000000b00666b3706be6sm1892596pfh.107.2023.07.27.14.23.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 14:23:04 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Johan Hovold , Bjorn Andersson , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 06/13] drm/msm/adreno: Allow SoC specific gpu device table entries Date: Thu, 27 Jul 2023 14:20:11 -0700 Message-ID: <20230727212208.102501-7-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 3c531da417b9..e62bc895a31f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + }, { + .machine = "qcom,sm4350", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + }, { + .machine = "qcom,sm6375", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev) /* identify gpu: */ for (i = 0; i < ARRAY_SIZE(gpulist); i++) { const struct adreno_info *info = &gpulist[i]; + if (info->machine && !of_machine_is_compatible(info->machine)) + continue; if (adreno_cmp_rev(info->rev, rev)) return info; } @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core == 2; + priv->has_cached_coherent = + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); gpu = info->init(drm); if (IS_ERR(gpu)) { @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - priv->has_cached_coherent = - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); - return 0; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e08d41337169..d5335b99c64c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; struct adreno_info { + const char *machine; struct adreno_rev rev; uint32_t revn; const char *fw[ADRENO_FW_MAX]; From patchwork Thu Jul 27 21:20:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78EA5C41513 for ; Thu, 27 Jul 2023 21:23:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232037AbjG0VX2 (ORCPT ); Thu, 27 Jul 2023 17:23:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231781AbjG0VXS (ORCPT ); Thu, 27 Jul 2023 17:23:18 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BEC11FC4; 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Thu, 27 Jul 2023 14:23:09 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Douglas Anderson , Bjorn Andersson , Johan Hovold , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 07/13] drm/msm/adreno: Move speedbin mapping to device table Date: Thu, 27 Jul 2023 14:20:12 -0700 Message-ID: <20230727212208.102501-8-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark This simplifies the code. v2: Use a table of structs instead of flat uint32_t[] Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++------------------- drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++++ 3 files changed, 97 insertions(+), 155 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 6f8c4381fa4a..a81a6459c656 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2204,159 +2204,19 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } -static u32 a610_get_speed_bin(u32 fuse) +static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) { - /* - * There are (at least) three SoCs implementing A610: SM6125 (trinket), - * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, - * as only a single SKU exists and we don't support khaje upstream yet. - * Hence, this matching table is only valid for bengal and can be easily - * expanded if need be. - */ - - if (fuse == 0) - return 0; - else if (fuse == 206) - return 1; - else if (fuse == 200) - return 2; - else if (fuse == 157) - return 3; - else if (fuse == 127) - return 4; - - return UINT_MAX; -} - -static u32 a618_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 169) - return 1; - else if (fuse == 174) - return 2; - - return UINT_MAX; -} - -static u32 a619_holi_get_speed_bin(u32 fuse) -{ - /* - * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) - * and SM6375 (blair). Limit the fuse matching to the corresponding - * SoC to prevent bogus frequency setting (as improbable as it may be, - * given unexpected fuse values are.. unexpected! But still possible.) - */ - - if (fuse == 0) - return 0; - - if (of_machine_is_compatible("qcom,sm4350")) { - if (fuse == 138) - return 1; - else if (fuse == 92) - return 2; - } else if (of_machine_is_compatible("qcom,sm6375")) { - if (fuse == 190) - return 1; - else if (fuse == 177) - return 2; - } else - pr_warn("Unknown SoC implementing A619_holi!\n"); - - return UINT_MAX; -} - -static u32 a619_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 120) - return 4; - else if (fuse == 138) - return 3; - else if (fuse == 169) - return 2; - else if (fuse == 180) - return 1; - - return UINT_MAX; -} - -static u32 a640_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 1) - return 1; - - return UINT_MAX; -} - -static u32 a650_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 1) - return 1; - /* Yep, 2 and 3 are swapped! :/ */ - else if (fuse == 2) - return 3; - else if (fuse == 3) - return 2; - - return UINT_MAX; -} + if (!info->speedbins) + return UINT_MAX; -static u32 adreno_7c3_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 117) - return 0; - else if (fuse == 190) - return 1; + for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) + if (info->speedbins[i].fuse == fuse) + return BIT(info->speedbins[i].speedbin); return UINT_MAX; } -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) -{ - u32 val = UINT_MAX; - - if (adreno_is_a610(adreno_gpu)) - val = a610_get_speed_bin(fuse); - - if (adreno_is_a618(adreno_gpu)) - val = a618_get_speed_bin(fuse); - - else if (adreno_is_a619_holi(adreno_gpu)) - val = a619_holi_get_speed_bin(fuse); - - else if (adreno_is_a619(adreno_gpu)) - val = a619_get_speed_bin(fuse); - - else if (adreno_is_7c3(adreno_gpu)) - val = adreno_7c3_get_speed_bin(fuse); - - else if (adreno_is_a640(adreno_gpu)) - val = a640_get_speed_bin(fuse); - - else if (adreno_is_a650(adreno_gpu)) - val = a650_get_speed_bin(fuse); - - if (val == UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", - fuse); - return UINT_MAX; - } - - return (1 << val); -} - -static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) +static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) { u32 supp_hw; u32 speedbin; @@ -2375,7 +2235,14 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_g return ret; } - supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); + supp_hw = fuse_to_supp_hw(info, speedbin); + + if (supp_hw == UINT_MAX) { + DRM_DEV_ERROR(dev, + "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", + speedbin); + return UINT_MAX; + } ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2483,17 +2350,11 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (!info) return ERR_PTR(-EINVAL); - /* Assign these early so that we can use the is_aXYZ helpers */ - /* New-style ADRENO_REV()-only */ - adreno_gpu->rev = info->rev; - /* Quirk data */ - adreno_gpu->info = info; - adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); + ret = a6xx_set_supported_hw(&pdev->dev, info); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e62bc895a31f..325b25dc8bfd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -247,6 +247,20 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a610_zap.mdt", .hwcg = a612_hwcg, + /* + * There are (at least) three SoCs implementing A610: SM6125 + * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does + * not have speedbinning, as only a single SKU exists and we + * don't support khaje upstream yet. Hence, this matching + * table is only valid for bengal. + */ + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 206, 1 }, + { 200, 2 }, + { 157, 3 }, + { 127, 4 }, + ), }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, @@ -258,6 +272,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 169, 1 }, + { 174, 2 }, + ), }, { .machine = "qcom,sm4350", .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -271,6 +290,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 138, 1 }, + { 92, 2 }, + ), }, { .machine = "qcom,sm6375", .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -284,6 +308,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 190, 1 }, + { 177, 2 }, + ), }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, @@ -297,6 +326,13 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 120, 4 }, + { 138, 3 }, + { 169, 2 }, + { 180, 1 }, + ), }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, @@ -323,6 +359,10 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + ), }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), .revn = 650, @@ -338,6 +378,12 @@ static const struct adreno_info gpulist[] = { .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ + { 3, 2 }, + ), }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), .revn = 660, @@ -366,6 +412,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 117, 0 }, + { 190, 1 }, + ), }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), .revn = 680, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index d5335b99c64c..aa64bad25a63 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -60,6 +60,11 @@ struct adreno_reglist { extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; +struct adreno_speedbin { + uint16_t fuse; + uint16_t speedbin; +}; + struct adreno_info { const char *machine; struct adreno_rev rev; @@ -72,8 +77,33 @@ struct adreno_info { u32 inactive_period; const struct adreno_reglist *hwcg; u64 address_space_size; + /** + * @speedbins: Optional table of fuse to speedbin mappings + * + * Consists of pairs of fuse, index mappings, terminated with + * {SHRT_MAX, 0} sentinal. + */ + struct adreno_speedbin *speedbins; }; +/* + * Helper to build a speedbin table, ie. the table: + * fuse | speedbin + * -----+--------- + * 0 | 0 + * 169 | 1 + * 174 | 2 + * + * would be declared as: + * + * .speedbins = ADRENO_SPEEDBINS( + * { 0, 0 }, + * { 169, 1 }, + * { 174, 2 }, + * ), + */ +#define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } + const struct adreno_info *adreno_info(struct adreno_rev rev); struct adreno_gpu { From patchwork Thu Jul 27 21:20:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46D41EB64DD for ; Thu, 27 Jul 2023 21:23:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230013AbjG0VX3 (ORCPT ); Thu, 27 Jul 2023 17:23:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230468AbjG0VXW (ORCPT ); Thu, 27 Jul 2023 17:23:22 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FBBC35AB; Thu, 27 Jul 2023 14:23:14 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-666e97fcc60so1127306b3a.3; Thu, 27 Jul 2023 14:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690492993; x=1691097793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M8B5Rk6QSQZWTWxcPiEa1LmusCrb40W7NxArO+Wdwlc=; b=FETijaWQcPoKuijdvy6VGH9gCIvpbHjIzX+8VQu0pH4QYeUT/XqTeuHahLKce5xQfA Buu+wxAtZJm6shHXbX1IJaE6X5OlFleB9tNqVI+7HF6ouedBPnk4FofE5mE5KGT2QOdg +YgsFvWjmKEPPXc/6d9/vVJyhyrKJU8iViWhoLcgEdwxoodh3ZL7YoIyGcJ6XwJNiLof vaapWyQcyFTldy8ACvCqTff/G9Hyhrj5JT6YSYHf9vEwYmI5KUsXJOY/60nikd4vsTNm fdKmh8DjyFS1esT+W1IVj1AmItG3NjlqsG9qr7478OuAs63kxj1sAR73WDeeAwWdYXkg I/4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690492993; x=1691097793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M8B5Rk6QSQZWTWxcPiEa1LmusCrb40W7NxArO+Wdwlc=; b=UmIYsEBhjX7P1HNxQhxYk7sbfOcdZRAKAVyKvozTmLk6P0FjXqwtIlKnb9X5CsORxi CUdmpVfNwYycgTMiPWHJnAAcjhJcdTTX4fNcTIOdgZMTlTJRBU1bhPYANdji9Va7Ir6j AHwNTK/skXfpac58sUvoFyVQcxwFB1H2X/Zf+ZcQweAGz86vrqWfMgxr6NElETmqZOX3 H+adVRYtdxJxpnrgy82gUHTzPDgzB1PypdN5FgXtjwi0r1PUGA6nEcNHpiKDdIanD7rT BFikqSoToTTMW6mpe7phjWaDeQTrUtA9piVLa94chpljmjVDX+HY1V+4GJQvdnfn9DnO GNRQ== X-Gm-Message-State: ABy/qLb/pdCOtZGlsdkyJwT/EF0j2ac9W7kYuPUfqdvOUAPoa0Tlt4hm lUuqPzV8dDu+KZVi6lVfx68= X-Google-Smtp-Source: APBJJlFGPAfj6SAzSLVI+8Pw5OBMxu5rUIc/sE2/Tg1vP16GnF3CRyxe7oq7crLI45hd0fsTEmVh0A== X-Received: by 2002:a05:6a21:35c4:b0:136:ea2d:6d6a with SMTP id ba4-20020a056a2135c400b00136ea2d6d6amr240137pzc.17.1690492993504; Thu, 27 Jul 2023 14:23:13 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:69d1:d8aa:25be:a2b6]) by smtp.gmail.com with ESMTPSA id m14-20020a638c0e000000b0055fedbf1938sm2000967pgd.31.2023.07.27.14.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 14:23:12 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Ulf Hansson , Douglas Anderson , Bjorn Andersson , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 08/13] drm/msm/adreno: Bring the a630 family together Date: Thu, 27 Jul 2023 14:20:13 -0700 Message-ID: <20230727212208.102501-9-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark All of these are derivatives of a630. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 5deb79924897..f1bb20574018 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1617,7 +1617,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) SZ_256K - SZ_16K, 0x44000, "dcache"); if (ret) goto err_memory; - } else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) { + } else if (adreno_is_a630_family(adreno_gpu)) { /* HFI v1, has sptprac */ gmu->legacy = true; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index aa64bad25a63..fe7afac5b059 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -340,10 +340,11 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) /* The order of args is important here to handle ANY_ID correctly */ return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev); }; -/* check for a615, a616, a618, a619 or any derivatives */ -static inline int adreno_is_a615_family(const struct adreno_gpu *gpu) +/* check for a615, a616, a618, a619 or any a630 derivatives */ +static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 615) || + return adreno_is_revn(gpu, 630) || + adreno_is_revn(gpu, 615) || adreno_is_revn(gpu, 616) || adreno_is_revn(gpu, 618) || adreno_is_revn(gpu, 619); From patchwork Thu Jul 27 21:20:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0526CEB64DD for ; Thu, 27 Jul 2023 21:23:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230033AbjG0VXp (ORCPT ); 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Thu, 27 Jul 2023 14:23:17 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Johan Hovold , Bjorn Andersson , Elliot Berman , Rob Herring , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 09/13] drm/msm/adreno: Add adreno family Date: Thu, 27 Jul 2023 14:20:14 -0700 Message-ID: <20230727212208.102501-10-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id. v2: Fix is_a2xx() typo Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 31 ++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 ++++++++++++++++------ 3 files changed, 70 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 325b25dc8bfd..e014d85a60cc 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -23,6 +23,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), + .family = ADRENO_2XX_GEN1, .revn = 200, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", @@ -33,6 +34,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), + .family = ADRENO_2XX_GEN1, .revn = 201, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", @@ -43,6 +45,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), + .family = ADRENO_2XX_GEN2, .revn = 220, .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw", @@ -53,6 +56,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), + .family = ADRENO_3XX, .revn = 305, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -63,6 +67,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 6, 0), + .family = ADRENO_3XX, .revn = 307, /* because a305c is revn==306 */ .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -73,6 +78,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), + .family = ADRENO_3XX, .revn = 320, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -83,6 +89,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), + .family = ADRENO_3XX, .revn = 330, .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw", @@ -93,6 +100,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .family = ADRENO_4XX, .revn = 405, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -103,6 +111,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 420, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -113,6 +122,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 430, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -123,6 +133,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), + .family = ADRENO_5XX, .revn = 506, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -140,6 +151,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a506_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .family = ADRENO_5XX, .revn = 508, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a508_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .family = ADRENO_5XX, .revn = 509, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 510, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -187,6 +201,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .family = ADRENO_5XX, .revn = 512, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -203,6 +218,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 3, 0, 2), + .family = ADRENO_5XX, .revn = 530, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -221,6 +237,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a530_zap.mdt", }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 540, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -238,6 +255,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a540_zap.mdt", }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 610, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -263,6 +281,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 618, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -280,6 +299,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm4350", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -298,6 +318,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm6375", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -315,6 +336,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -335,6 +357,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 630, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -348,6 +371,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a630_hwcg, }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 640, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -365,6 +389,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), + .family = ADRENO_6XX_GEN3, .revn = 650, .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw", @@ -386,6 +411,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .revn = 660, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -401,6 +427,7 @@ static const struct adreno_info gpulist[] = { .address_space_size = SZ_16G, }, { .rev = ADRENO_REV(6, 3, 5, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin", @@ -419,6 +446,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 680, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -432,6 +460,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a640_hwcg, }, { .rev = ADRENO_REV(6, 9, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a690_gmu.bin", @@ -641,7 +670,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, config.rev.minor, config.rev.patchid); - priv->is_a2xx = config.rev.core == 2; + priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index f4d45534dd7f..1951036b2308 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1080,8 +1080,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, u32 speedbin; int ret; + adreno_gpu->funcs = funcs; + adreno_gpu->info = adreno_info(config->rev); + adreno_gpu->rev = *rev; + /* Only handle the core clock when GMU is not in use (or is absent). */ - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) { + if (adreno_has_gmu_wrapper(adreno_gpu) || + adreno_gpu->info->family < ADRENO_6XX_GEN1) { /* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON() @@ -1097,10 +1102,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - adreno_gpu->funcs = funcs; - adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->rev = *rev; - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index fe7afac5b059..14af16080bd0 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -29,6 +29,25 @@ enum { ADRENO_FW_MAX, }; +/** + * @enum adreno_family: identify generation and possibly sub-generation + * + * In some cases there are distinct sub-generations within a major revision + * so it helps to be able to group the GPU devices by generation and if + * necessary sub-generation. + */ +enum adreno_family { + ADRENO_2XX_GEN1, /* a20x */ + ADRENO_2XX_GEN2, /* a22x */ + ADRENO_3XX, + ADRENO_4XX, + ADRENO_5XX, + ADRENO_6XX_GEN1, /* a630 family */ + ADRENO_6XX_GEN2, /* a640 family */ + ADRENO_6XX_GEN3, /* a650 family */ + ADRENO_6XX_GEN4, /* a660 family */ +}; + #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) @@ -68,6 +87,7 @@ struct adreno_speedbin { struct adreno_info { const char *machine; struct adreno_rev rev; + enum adreno_family family; uint32_t revn; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; @@ -193,14 +213,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return (gpu->info->revn < 300); + return gpu->info->family <= ADRENO_2XX_GEN2; } static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return (gpu->info->revn < 210); + return gpu->info->family == ADRENO_2XX_GEN1; } static inline bool adreno_is_a225(const struct adreno_gpu *gpu) @@ -343,29 +363,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 630) || - adreno_is_revn(gpu, 615) || - adreno_is_revn(gpu, 616) || - adreno_is_revn(gpu, 618) || - adreno_is_revn(gpu, 619); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN1; } static inline int adreno_is_a660_family(const struct adreno_gpu *gpu) { - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN4; } /* check for a650, a660, or any derivatives */ static inline int adreno_is_a650_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 650) || - adreno_is_revn(gpu, 620) || - adreno_is_a660_family(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family >= ADRENO_6XX_GEN3; } static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) { - return adreno_is_a640(gpu) || adreno_is_a680(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN2; } u64 adreno_private_address_space_size(struct msm_gpu *gpu); From patchwork Thu Jul 27 21:20:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A521CC04A94 for ; Thu, 27 Jul 2023 21:23:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231421AbjG0VXp (ORCPT ); Thu, 27 Jul 2023 17:23:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47434 "EHLO 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2023 14:20:15 -0700 Message-ID: <20230727212208.102501-11-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++----- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++----------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++ 3 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e014d85a60cc..7448f299b77c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -661,14 +661,12 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) info = adreno_info(config.rev); if (!info) { - dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", - config.rev.core, config.rev.major, - config.rev.minor, config.rev.patchid); + dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", + ADRENO_CHIPID_ARGS(config.rev)); return -ENXIO; } - DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, - config.rev.minor, config.rev.patchid); + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev)); priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1951036b2308..a775b4d82735 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -847,10 +847,9 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, if (IS_ERR_OR_NULL(state)) return; - drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", - adreno_gpu->info->revn, adreno_gpu->rev.core, - adreno_gpu->rev.major, adreno_gpu->rev.minor, - adreno_gpu->rev.patchid); + drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n", + adreno_gpu->info->revn, + ADRENO_CHIPID_ARGS(adreno_gpu->rev)); /* * If this is state collected due to iova fault, so fault related info * @@ -921,10 +920,9 @@ void adreno_dump_info(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int i; - printk("revision: %d (%d.%d.%d.%d)\n", - adreno_gpu->info->revn, adreno_gpu->rev.core, - adreno_gpu->rev.major, adreno_gpu->rev.minor, - adreno_gpu->rev.patchid); + printk("revision: %u (%"ADRENO_CHIPID_FMT")\n", + adreno_gpu->info->revn, + ADRENO_CHIPID_ARGS(adreno_gpu->rev)); for (i = 0; i < gpu->nr_rings; i++) { struct msm_ringbuffer *ring = gpu->rb[i]; @@ -1106,9 +1104,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", - rev->core, rev->major, rev->minor, - rev->patchid); + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, + ADRENO_CHIPID_ARGS(config->rev)); if (!gpu_name) return -ENOMEM; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 14af16080bd0..c6fd6f9016d3 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -66,6 +66,12 @@ struct adreno_rev { #define ADRENO_REV(core, major, minor, patchid) \ ((struct adreno_rev){ core, major, minor, patchid }) +/* Helper for formating the chip_id in the way that userspace tools like + * crashdec expect. + */ +#define ADRENO_CHIPID_FMT "u.%u.%u.%u" +#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid + struct adreno_gpu_funcs { struct msm_gpu_funcs base; int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); From patchwork Thu Jul 27 21:20:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32F86EB64DD for ; Thu, 27 Jul 2023 21:23:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231147AbjG0VX5 (ORCPT ); Thu, 27 Jul 2023 17:23:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231854AbjG0VXu (ORCPT ); Thu, 27 Jul 2023 17:23:50 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A04323A80; 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Thu, 27 Jul 2023 14:23:28 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Douglas Anderson , Bjorn Andersson , Johan Hovold , Guru Das Srinagesh , Rob Herring , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 11/13] drm/msm/adreno: Move adreno info to config Date: Thu, 27 Jul 2023 14:20:16 -0700 Message-ID: <20230727212208.102501-12-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Let's just stash it in adreno_platform_config rather than looking it up in N different places. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++------------ drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-- 4 files changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a81a6459c656..9be3260c8033 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2316,7 +2316,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct platform_device *pdev = priv->gpu_pdev; struct adreno_platform_config *config = pdev->dev.platform_data; - const struct adreno_info *info; struct device_node *node; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; @@ -2341,20 +2340,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); - /* - * We need to know the platform type before calling into adreno_gpu_init - * so that the hw_apriv flag can be correctly set. Snoop into the info - * and grab the revision number - */ - info = adreno_info(config->rev); - if (!info) - return ERR_PTR(-EINVAL); - - adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); + adreno_gpu->base.hw_apriv = + !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, info); + ret = a6xx_set_supported_hw(&pdev->dev, config->info); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 7448f299b77c..332cb804a45d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -508,7 +508,7 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2) _rev_match(rev1.patchid, rev2.patchid); } -const struct adreno_info *adreno_info(struct adreno_rev rev) +static const struct adreno_info *adreno_info(struct adreno_rev rev) { int i; @@ -659,13 +659,14 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) priv->gpu_pdev = to_platform_device(dev); info = adreno_info(config.rev); - if (!info) { dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", ADRENO_CHIPID_ARGS(config.rev)); return -ENXIO; } + config.info = info; + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev)); priv->is_a2xx = info->family < ADRENO_3XX; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index a775b4d82735..865ff4c1eaf6 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1079,7 +1079,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, int ret; adreno_gpu->funcs = funcs; - adreno_gpu->info = adreno_info(config->rev); + adreno_gpu->info = config->info; adreno_gpu->rev = *rev; /* Only handle the core clock when GMU is not in use (or is absent). */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index c6fd6f9016d3..81a1396e124d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -130,8 +130,6 @@ struct adreno_info { */ #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } -const struct adreno_info *adreno_info(struct adreno_rev rev); - struct adreno_gpu { struct msm_gpu base; struct adreno_rev rev; @@ -185,6 +183,7 @@ struct adreno_ocmem { /* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config { struct adreno_rev rev; + const struct adreno_info *info; }; #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) From patchwork Thu Jul 27 21:20:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13330753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47019C00528 for ; Thu, 27 Jul 2023 21:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230270AbjG0VYB (ORCPT ); Thu, 27 Jul 2023 17:24:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231923AbjG0VX4 (ORCPT ); Thu, 27 Jul 2023 17:23:56 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11E2D4200; Thu, 27 Jul 2023 14:23:31 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1bb2468257fso8691155ad.0; Thu, 27 Jul 2023 14:23:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690493011; x=1691097811; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AQZMOPuU2NT251VkgOhkBFz/GJRkDGlyYehHpTo6xuo=; b=ivYp4VJCrL/8o1Xn4k6WDMaTuMD3bKTU4BJpdp83TNkv1aQzgezYW+SjC5+QLxW8lh 00IQvb2RQ1DY4Yv4R6sEuZN7yYF6qWdSiyr1towRuRVGFEwDSgZhrozK8pxzr4pPdl0S BF2uXXKUtnQ8HbzR/h352BcbpZ9jXcymuiC/O8Nf0j7q8bhifVUBAQg+JBLWBHky4h0+ fqhPJvCO5+sTO9Otyciht4/oaN9qAOIedk8P/ojCImjfWB04JEU7f2cZttDA4xqYn/DR XRtxwQUJC642nI3RwdLqczsIQdwxecFJ00gfPYR5SuUsOiOLjsZPzKFh797GJ4xDacRo PGUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690493011; x=1691097811; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AQZMOPuU2NT251VkgOhkBFz/GJRkDGlyYehHpTo6xuo=; b=cxmbVbwSiTWI6lqm1SADamyWfd99sselIGHFaHyh6XMssk315DwSuNBlRHatfIKudN INDmjYy/ZM2OAIvZzPKxWikISqww2A26gw2uousnQYDVS5ZTnISGH1HYBWUuc1jm3L2K 91/rPPe39udNEjyN3Rdc3dswSy1xd1uv64zd+z8yAtxd5wndtV23vhXgT6mDxONaaEB2 a8DPZTmxcTa+wgoNe+JVu/Z2TnukdtFGOI3Uk5W3pcQovJh50W50vT+zBjRiwSMpFeuV 5gZ6BS0hkkSet5TqpUIxbl36lxioxVL6QEMVNGIBDaBSmhaLbPOXhR3tZIXiHZfmQofa G+pA== X-Gm-Message-State: ABy/qLasYJ3omAxAMFOzt/pcVW4qze4wGIRBBQRArTLDtnscfqu2vOHr 3d2IHSOKxP8j/oKJT74FjWA= X-Google-Smtp-Source: APBJJlG1ww+SPQvtSFuUK3ikZ0jM7AgtQ8N3bRakU4pav3WJNQ0ITBLndKGJDY5IP78SwHRXLOQJWQ== X-Received: by 2002:a17:902:ef87:b0:1b9:e9f1:91e0 with SMTP id iz7-20020a170902ef8700b001b9e9f191e0mr383339plb.41.1690493011002; Thu, 27 Jul 2023 14:23:31 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:69d1:d8aa:25be:a2b6]) by smtp.gmail.com with ESMTPSA id z8-20020a170903018800b001b8a85489a3sm2074529plg.262.2023.07.27.14.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 14:23:30 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Akhil P Oommen , Konrad Dybcio , Rob Clark , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 12/13] dt-bindings: drm/msm/gpu: Extend bindings for chip-id Date: Thu, 27 Jul 2023 14:20:17 -0700 Message-ID: <20230727212208.102501-13-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727212208.102501-1-robdclark@gmail.com> References: <20230727212208.102501-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Upcoming GPUs use an opaque chip-id for identifying the GPU. Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 58ca8912a8c3..56b9b247e8c2 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -13,6 +13,12 @@ maintainers: properties: compatible: oneOf: + - description: | + The driver is parsing the compat string for Adreno to + figure out the chip-id. + items: + - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$' + - const: qcom,adreno - description: | The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. 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This means that we need to explicitly list different patch revisions in the device table. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++- drivers/gpu/drm/msm/adreno/adreno_device.c | 137 +++++++++++---------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 49 ++++---- 7 files changed, 115 insertions(+), 105 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 715436cb3996..8b4cdf95f445 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000); /* Early A430's have a timing issue with SP/TP power collapse; disabling HW clock gating prevents it. */ - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2) + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); else gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index f0803e94ebe5..a98c97977e01 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1770,7 +1770,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) nr_rings = 4; - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev)) + if (config->info->revn == 510) nr_rings = 1; ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index 0e63a1429189..7705f8010484 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu) /* The battery current limiter isn't enabled for A540 */ config = AGC_LM_CONFIG_BCL_DISABLED; - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT; + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT; /* For now disable GPMU side throttling */ config |= AGC_LM_CONFIG_THROTTLE_DISABLE; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index f1bb20574018..bf7f855f4a34 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -790,10 +790,16 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, (1 << 31) | (0xa << 18) | (0xa0)); - chipid = adreno_gpu->rev.core << 24; - chipid |= adreno_gpu->rev.major << 16; - chipid |= adreno_gpu->rev.minor << 12; - chipid |= adreno_gpu->rev.patchid << 8; + /* + * Note that the GMU has a slightly different layout for + * chip_id, for whatever reason, so a bit of massaging + * is needed. The upper 16b are the same, but minor and + * patchid are packed in four bits each with the lower + * 8b unused: + */ + chipid = adreno_gpu->chip_id & 0xffff0000; + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */ + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 332cb804a45d..9cda403ebc7b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); static const struct adreno_info gpulist[] = { { - .rev = ADRENO_REV(2, 0, 0, 0), + .chip_ids = ADRENO_CHIP_IDS(0x02000000), .family = ADRENO_2XX_GEN1, .revn = 200, .fw = { @@ -33,7 +33,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { /* a200 on i.mx51 has only 128kib gmem */ - .rev = ADRENO_REV(2, 0, 0, 1), + .chip_ids = ADRENO_CHIP_IDS(0x02000001), .family = ADRENO_2XX_GEN1, .revn = 201, .fw = { @@ -44,7 +44,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .rev = ADRENO_REV(2, 2, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x02020000), .family = ADRENO_2XX_GEN2, .revn = 220, .fw = { @@ -55,7 +55,10 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .rev = ADRENO_REV(3, 0, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x03000512, + 0x03000520 + ), .family = ADRENO_3XX, .revn = 305, .fw = { @@ -66,7 +69,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 0, 6, 0), + .chip_ids = ADRENO_CHIP_IDS(0x03000600), .family = ADRENO_3XX, .revn = 307, /* because a305c is revn==306 */ .fw = { @@ -77,7 +80,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x03020000, + 0x03020001, + 0x03020002 + ), .family = ADRENO_3XX, .revn = 320, .fw = { @@ -88,7 +95,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x03030000, + 0x03030001, + 0x03030002 + ), .family = ADRENO_3XX, .revn = 330, .fw = { @@ -99,7 +110,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04000500), .family = ADRENO_4XX, .revn = 405, .fw = { @@ -110,7 +121,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04020000), .family = ADRENO_4XX, .revn = 420, .fw = { @@ -121,7 +132,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04030002), .family = ADRENO_4XX, .revn = 430, .fw = { @@ -132,7 +143,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(5, 0, 6, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000600), .family = ADRENO_5XX, .revn = 506, .fw = { @@ -150,7 +161,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a506_zap.mdt", }, { - .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000800), .family = ADRENO_5XX, .revn = 508, .fw = { @@ -167,7 +178,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a508_zap.mdt", }, { - .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000900), .family = ADRENO_5XX, .revn = 509, .fw = { @@ -185,7 +196,7 @@ static const struct adreno_info gpulist[] = { /* Adreno 509 uses the same ZAP as 512 */ .zapfw = "a512_zap.mdt", }, { - .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05010000), .family = ADRENO_5XX, .revn = 510, .fw = { @@ -200,7 +211,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = 250, .init = a5xx_gpu_init, }, { - .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05010200), .family = ADRENO_5XX, .revn = 512, .fw = { @@ -217,7 +228,10 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a512_zap.mdt", }, { - .rev = ADRENO_REV(5, 3, 0, 2), + .chip_ids = ADRENO_CHIP_IDS( + 0x05030002, + 0x05030004 + ), .family = ADRENO_5XX, .revn = 530, .fw = { @@ -236,7 +250,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", }, { - .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05040001), .family = ADRENO_5XX, .revn = 540, .fw = { @@ -254,7 +268,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", }, { - .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010000), .family = ADRENO_6XX_GEN1, .revn = 610, .fw = { @@ -280,7 +294,7 @@ static const struct adreno_info gpulist[] = { { 127, 4 }, ), }, { - .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010800), .family = ADRENO_6XX_GEN1, .revn = 618, .fw = { @@ -298,7 +312,7 @@ static const struct adreno_info gpulist[] = { ), }, { .machine = "qcom,sm4350", - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -317,7 +331,7 @@ static const struct adreno_info gpulist[] = { ), }, { .machine = "qcom,sm6375", - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -335,7 +349,7 @@ static const struct adreno_info gpulist[] = { { 177, 2 }, ), }, { - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -356,7 +370,10 @@ static const struct adreno_info gpulist[] = { { 180, 1 }, ), }, { - .rev = ADRENO_REV(6, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x06030001, + 0x06030002 + ), .family = ADRENO_6XX_GEN1, .revn = 630, .fw = { @@ -370,7 +387,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a630_zap.mdt", .hwcg = a630_hwcg, }, { - .rev = ADRENO_REV(6, 4, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06040001), .family = ADRENO_6XX_GEN2, .revn = 640, .fw = { @@ -388,7 +405,7 @@ static const struct adreno_info gpulist[] = { { 1, 1 }, ), }, { - .rev = ADRENO_REV(6, 5, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06050002), .family = ADRENO_6XX_GEN3, .revn = 650, .fw = { @@ -410,7 +427,7 @@ static const struct adreno_info gpulist[] = { { 3, 2 }, ), }, { - .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06060001), .family = ADRENO_6XX_GEN4, .revn = 660, .fw = { @@ -426,7 +443,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a660_hwcg, .address_space_size = SZ_16G, }, { - .rev = ADRENO_REV(6, 3, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06030500), .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -445,7 +462,7 @@ static const struct adreno_info gpulist[] = { { 190, 1 }, ), }, { - .rev = ADRENO_REV(6, 8, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06080000), .family = ADRENO_6XX_GEN2, .revn = 680, .fw = { @@ -459,7 +476,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, }, { - .rev = ADRENO_REV(6, 9, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06090000), .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -494,31 +511,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw"); MODULE_FIRMWARE("qcom/a630_gmu.bin"); MODULE_FIRMWARE("qcom/a630_zap.mbn"); -static inline bool _rev_match(uint8_t entry, uint8_t id) +static const struct adreno_info *adreno_info(uint32_t chip_id) { - return (entry == ANY_ID) || (entry == id); -} - -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2) -{ - - return _rev_match(rev1.core, rev2.core) && - _rev_match(rev1.major, rev2.major) && - _rev_match(rev1.minor, rev2.minor) && - _rev_match(rev1.patchid, rev2.patchid); -} - -static const struct adreno_info *adreno_info(struct adreno_rev rev) -{ - int i; - /* identify gpu: */ - for (i = 0; i < ARRAY_SIZE(gpulist); i++) { + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) { const struct adreno_info *info = &gpulist[i]; if (info->machine && !of_machine_is_compatible(info->machine)) continue; - if (adreno_cmp_rev(info->rev, rev)) - return info; + for (int j = 0; info->chip_ids[j]; j++) + if (info->chip_ids[j] == chip_id) + return info; } return NULL; @@ -598,12 +600,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) return NULL; } -static int find_chipid(struct device *dev, struct adreno_rev *rev) +static int find_chipid(struct device *dev, uint32_t *chipid) { struct device_node *node = dev->of_node; const char *compat; int ret; - u32 chipid; /* first search the compat strings for qcom,adreno-XYZ.W: */ ret = of_property_read_string_index(node, "compatible", 0, &compat); @@ -612,32 +613,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev) if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { - rev->core = r / 100; + uint32_t core, major, minor; + + core = r / 100; r %= 100; - rev->major = r / 10; + major = r / 10; r %= 10; - rev->minor = r; - rev->patchid = patch; + minor = r; + + *chipid = (core << 24) | + (major << 16) | + (minor << 8) | + patch; return 0; } + + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1) + return 0; } /* and if that fails, fall back to legacy "qcom,chipid" property: */ - ret = of_property_read_u32(node, "qcom,chipid", &chipid); + ret = of_property_read_u32(node, "qcom,chipid", chipid); if (ret) { DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); return ret; } - rev->core = (chipid >> 24) & 0xff; - rev->major = (chipid >> 16) & 0xff; - rev->minor = (chipid >> 8) & 0xff; - rev->patchid = (chipid & 0xff); - dev_warn(dev, "Using legacy qcom,chipid binding!\n"); - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", - rev->core, rev->major, rev->minor, rev->patchid); return 0; } @@ -651,23 +654,23 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) struct msm_gpu *gpu; int ret; - ret = find_chipid(dev, &config.rev); + ret = find_chipid(dev, &config.chip_id); if (ret) return ret; dev->platform_data = &config; priv->gpu_pdev = to_platform_device(dev); - info = adreno_info(config.rev); + info = adreno_info(config.chip_id); if (!info) { dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", - ADRENO_CHIPID_ARGS(config.rev)); + ADRENO_CHIPID_ARGS(config.chip_id)); return -ENXIO; } config.info = info; - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev)); + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id)); priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 865ff4c1eaf6..ba35c2a87021 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; return 0; case MSM_PARAM_CHIP_ID: - *value = (uint64_t)adreno_gpu->rev.patchid | - ((uint64_t)adreno_gpu->rev.minor << 8) | - ((uint64_t)adreno_gpu->rev.major << 16) | - ((uint64_t)adreno_gpu->rev.core << 24); + *value = adreno_gpu->chip_id; if (!adreno_gpu->info->revn) *value |= ((uint64_t) adreno_gpu->speedbin) << 32; return 0; @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n", adreno_gpu->info->revn, - ADRENO_CHIPID_ARGS(adreno_gpu->rev)); + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id)); /* * If this is state collected due to iova fault, so fault related info * @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu) printk("revision: %u (%"ADRENO_CHIPID_FMT")\n", adreno_gpu->info->revn, - ADRENO_CHIPID_ARGS(adreno_gpu->rev)); + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id)); for (i = 0; i < gpu->nr_rings; i++) { struct msm_ringbuffer *ring = gpu->rb[i]; @@ -1073,14 +1070,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_platform_config *config = dev->platform_data; struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; - struct adreno_rev *rev = &config->rev; const char *gpu_name; u32 speedbin; int ret; adreno_gpu->funcs = funcs; adreno_gpu->info = config->info; - adreno_gpu->rev = *rev; + adreno_gpu->chip_id = config->chip_id; /* Only handle the core clock when GMU is not in use (or is absent). */ if (adreno_has_gmu_wrapper(adreno_gpu) || @@ -1105,7 +1101,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, - ADRENO_CHIPID_ARGS(config->rev)); + ADRENO_CHIPID_ARGS(config->chip_id)); if (!gpu_name) return -ENOMEM; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 81a1396e124d..0af43ae82c43 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -54,23 +54,15 @@ enum adreno_family { #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) -struct adreno_rev { - uint8_t core; - uint8_t major; - uint8_t minor; - uint8_t patchid; -}; - -#define ANY_ID 0xff - -#define ADRENO_REV(core, major, minor, patchid) \ - ((struct adreno_rev){ core, major, minor, patchid }) - /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. */ #define ADRENO_CHIPID_FMT "u.%u.%u.%u" -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid +#define ADRENO_CHIPID_ARGS(_c) \ + (((_c) >> 24) & 0xff), \ + (((_c) >> 16) & 0xff), \ + (((_c) >> 8) & 0xff), \ + ((_c) & 0xff) struct adreno_gpu_funcs { struct msm_gpu_funcs base; @@ -92,7 +84,12 @@ struct adreno_speedbin { struct adreno_info { const char *machine; - struct adreno_rev rev; + /** + * @chipids: Table of matching chip-ids + * + * Terminated with 0 sentinal + */ + uint32_t *chip_ids; enum adreno_family family; uint32_t revn; const char *fw[ADRENO_FW_MAX]; @@ -112,6 +109,8 @@ struct adreno_info { struct adreno_speedbin *speedbins; }; +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 } + /* * Helper to build a speedbin table, ie. the table: * fuse | speedbin @@ -132,8 +131,8 @@ struct adreno_info { struct adreno_gpu { struct msm_gpu base; - struct adreno_rev rev; const struct adreno_info *info; + uint32_t chip_id; uint16_t speedbin; const struct adreno_gpu_funcs *funcs; @@ -182,7 +181,7 @@ struct adreno_ocmem { /* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config { - struct adreno_rev rev; + uint32_t chip_id; const struct adreno_info *info; }; @@ -200,7 +199,15 @@ struct adreno_platform_config { __ret; \ }) -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu) +{ + /* It is probably ok to assume legacy "adreno_rev" format + * for all a6xx devices, but probably best to limit this + * to older things. + */ + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1); + return gpu->chip_id & 0xff; +} static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) { @@ -256,7 +263,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu) static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu) { - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0); } static inline int adreno_is_a405(const struct adreno_gpu *gpu) @@ -346,8 +353,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu) static inline int adreno_is_7c3(const struct adreno_gpu *gpu) { - /* The order of args is important here to handle ANY_ID correctly */ - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev); + return gpu->info->chip_ids[0] == 0x06030500; } static inline int adreno_is_a660(const struct adreno_gpu *gpu) @@ -362,8 +368,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu) static inline int adreno_is_a690(const struct adreno_gpu *gpu) { - /* The order of args is important here to handle ANY_ID correctly */ - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev); + return gpu->info->chip_ids[0] == 0x06090000; }; /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)