From patchwork Fri Jul 28 18:19:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13332255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C9ECC0015E for ; Fri, 28 Jul 2023 18:19:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235761AbjG1STh (ORCPT ); Fri, 28 Jul 2023 14:19:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229830AbjG1STg (ORCPT ); Fri, 28 Jul 2023 14:19:36 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 940983C1D for ; Fri, 28 Jul 2023 11:19:35 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-cf4cb742715so2161053276.2 for ; Fri, 28 Jul 2023 11:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690568375; x=1691173175; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=T7cMhi6W1QA72qy6OnVjmEOCding/R2p1klzAYF0ZSc=; b=rF2yKEaY1+qGW4yqr/ZDga1hoWZYiI2p2zc8yQ9kHdT44KsPEvoMVekCxp8AfghkrW rMjKjRvkxs+wiCzBI5lgToksGFROkVlXlN+SkQIjZniH8ytnyaxvtlQRlJn9Cj8kcvI3 KoFNL9T8OSKOnjnssPigziHXCqK1L3kE2iRASoTLF1OnyYkPMah8AsJk05j8hATC3ZZ2 C8bnTiwVpe5/KEZBZIzcExtKteckZN91xceRRLul0/fRz8xcWAGQJvr8FcCUVvOx9LpH CBFXgWSA928eM+Yo7h1fWLEYXg24t9YcsTPZYlS7JEpAAXmcD3X0XI3V5Wi6vT6uSlm2 uZDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690568375; x=1691173175; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=T7cMhi6W1QA72qy6OnVjmEOCding/R2p1klzAYF0ZSc=; b=VDoM1y4HdITTpB/VJV+ltn88rSvdRqY1ilC5rEq6ng55oBeKXbygA1jp785n2qPkCv TUAY2Rnof60p55YBQYs0LGrkY5EuBpEkwwLs9OS9N8VdUtWBshXLDoaKKDdWfK/SNMt3 1slmQ/UmM6YK+X1Zp2EpLqD63txI+aYsP7u0zucoCE8RSAOsjXkgrWNATbtT2Y5vu+rE qhyu6mpd9Kld97ebkBhHqdcPgVryXmTpycklrxWYxci/w9SsyfJDeW21IdX2FsfM8Tuf R34JOJjeVrSmyqzOl1fVmqDgN+uxMO8cHQh5CJKIZDDb/WenCnDg5XbZNIrIdjwxYGU+ 85ow== X-Gm-Message-State: ABy/qLZ8oWzH5ANAZzhJ6240lGpjdAqHCB7qljAix6XZPJnjuu3LvSZi 9znvfO3VFuINyalxBqR+qekljF4y2/A= X-Google-Smtp-Source: APBJJlHHrkbaWwlROgHKR6eB+lXZtSRXwpmBiCRMU364RcnA5ppYwL/doSe0Q2ZdQqFbWDIBBE84vPbLp04= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a05:6902:100f:b0:cf9:3564:33cc with SMTP id w15-20020a056902100f00b00cf9356433ccmr18274ybt.13.1690568374733; Fri, 28 Jul 2023 11:19:34 -0700 (PDT) Date: Fri, 28 Jul 2023 11:19:03 -0700 In-Reply-To: <20230728181907.1759513-1-reijiw@google.com> Mime-Version: 1.0 References: <20230728181907.1759513-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230728181907.1759513-2-reijiw@google.com> Subject: [PATCH v2 1/5] KVM: arm64: PMU: Use of pmuv3_implemented() instead of open-coded version From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Replace the open-coded PMU version check with pmuv3_implemented() to simplify the code. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/pmu-emul.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 560650972478..dee83119e112 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -14,6 +14,7 @@ #include #include #include +#include #define PERF_ATTR_CFG1_COUNTER_64BIT BIT(0) @@ -672,8 +673,7 @@ void kvm_host_pmu_init(struct arm_pmu *pmu) { struct arm_pmu_entry *entry; - if (pmu->pmuver == ID_AA64DFR0_EL1_PMUVer_NI || - pmu->pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) + if (!pmuv3_implemented(pmu->pmuver)) return; mutex_lock(&arm_pmus_lock); From patchwork Fri Jul 28 18:19:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13332256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11A2EC001DF for ; Fri, 28 Jul 2023 18:19:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235786AbjG1STp (ORCPT ); Fri, 28 Jul 2023 14:19:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235772AbjG1STo (ORCPT ); Fri, 28 Jul 2023 14:19:44 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 514093C27 for ; Fri, 28 Jul 2023 11:19:43 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-d052f58b7deso2274717276.2 for ; Fri, 28 Jul 2023 11:19:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690568382; x=1691173182; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=H7xJDFLue/NvwsOlwF0hcWMCcGztcwcVHo0aL0oqpCk=; b=MFangAmRBbh+y81QRDLHlnYWDvQam6hXRtl/9i9dvGTHWjQTWrcGvnSxU9nQj+bhLG KRzv3Uowtaa75RT4RISVnvfwip8juIdbGophEv79/46AnMKYkzKWTLmfmSb9gPbKid6h 8Oini5a6yFzTlXor1VJxSgWUyPvlprvZwBtZPz1MUdZ57CLfM+BtzFhXwkC21T49fiVF A+nu0DCxaly6SaU567uP7eaLYDtse4zpLotilYTpvJ6AKUHYJTxTOuqmNKajw70r18aV 6VN4k0AIJtA32vvNG2KjElxBrD4g+cVb19koF09jjMuPCmV4GVAmWnlzFJUOqw0GW2kw DoLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690568382; x=1691173182; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=H7xJDFLue/NvwsOlwF0hcWMCcGztcwcVHo0aL0oqpCk=; b=WxB37QCA21K3zd3wG5Md9gg6HcaQJ3j3XvI51a0poRp8OZa15AW2DvsH4nTNTYPWDz PeQADjSZTdvwp/sdCjLGpndAr3n9j4wVLpKf/j8ulCJQyr0prlFYUDqwaNvNMnGORbaZ 0RABMz8A5UyLfDmWsRK2YhxnCylJjIalAmIrnO/5PeEK7+wdKajnytemYu9BAazbelOA OisCMQ2xv6xuLA1NK/B7Ll/WDzcsf5ifLcjpZlzO21DIii0xxsfxgMmh1O0JaANxE/Jt z3eOK7VmMFsb0J+titgWyxvFSgIvtlAXiueuTdC5D2nF7z5KisLfcONai343FdHbmbyK tZ2A== X-Gm-Message-State: ABy/qLYkCV1npn0+GqEhdu80fJMrEcj6s1AlOubbyPZ4PkomQf6Ali+Z DYo0AaGjk+cCTsM083pi6o3MaZvgeI8= X-Google-Smtp-Source: APBJJlHLtcHDyqcq9MQ6CU4noYTnxBVY9xSNarpOt7Z38zw5Zg3c+tHSZBL/SzA6OvcKskJwpb9P4Vgnm9I= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a25:ae0c:0:b0:d05:38ba:b616 with SMTP id a12-20020a25ae0c000000b00d0538bab616mr13044ybj.6.1690568382652; Fri, 28 Jul 2023 11:19:42 -0700 (PDT) Date: Fri, 28 Jul 2023 11:19:04 -0700 In-Reply-To: <20230728181907.1759513-1-reijiw@google.com> Mime-Version: 1.0 References: <20230728181907.1759513-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230728181907.1759513-3-reijiw@google.com> Subject: [PATCH v2 2/5] KVM: arm64: PMU: Disallow vPMU on non-uniform PMUVer systems From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Disallow userspace from configuring vPMU for guests on systems where the PMUVer is not uniform across all PEs. KVM has not been advertising PMUv3 to the guests with vPMU on such systems anyway, and such systems would be extremely uncommon and unlikely to even use KVM. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/arm.c | 1 + arch/arm64/kvm/pmu-emul.c | 11 ++++++++--- include/kvm/arm_pmu.h | 3 +++ 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 72dc53a75d1c..1d410dea21ac 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2053,6 +2053,7 @@ static int __init init_subsystems(void) goto out; kvm_register_perf_callbacks(NULL); + kvm_pmu_init(); out: if (err) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index dee83119e112..6fb5c59948a8 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -685,9 +685,6 @@ void kvm_host_pmu_init(struct arm_pmu *pmu) entry->arm_pmu = pmu; list_add_tail(&entry->entry, &arm_pmus); - if (list_is_singular(&arm_pmus)) - static_branch_enable(&kvm_arm_pmu_available); - out_unlock: mutex_unlock(&arm_pmus_lock); } @@ -1057,3 +1054,11 @@ u8 kvm_arm_pmu_get_pmuver_limit(void) ID_AA64DFR0_EL1_PMUVer_V3P5); return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp); } + +void kvm_pmu_init(void) +{ + u8 pmuver = kvm_arm_pmu_get_pmuver_limit(); + + if (pmuv3_implemented(pmuver)) + static_branch_enable(&kvm_arm_pmu_available); +} diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 847da6fc2713..9cf50e16305a 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -74,6 +74,7 @@ int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu); struct kvm_pmu_events *kvm_get_pmu_events(void); void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); +void kvm_pmu_init(void); #define kvm_vcpu_has_pmu(vcpu) \ (test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features)) @@ -110,6 +111,8 @@ static inline bool kvm_arm_support_pmu_v3(void) return false; } +static inline void kvm_pmu_init(void) {}; + #define kvm_arm_pmu_irq_initialized(v) (false) static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx) From patchwork Fri Jul 28 18:19:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13332257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CE8FC0015E for ; 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Fri, 28 Jul 2023 11:19:55 -0700 (PDT) Date: Fri, 28 Jul 2023 11:19:05 -0700 In-Reply-To: <20230728181907.1759513-1-reijiw@google.com> Mime-Version: 1.0 References: <20230728181907.1759513-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230728181907.1759513-4-reijiw@google.com> Subject: [PATCH v2 3/5] KVM: arm64: PMU: Avoid inappropriate use of host's PMUVer From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Avoid using the PMUVer of the host's PMU hardware to determine the PMU event mask, except in one case, as the value of host's PMUVer may differ from the value of ID_AA64DFR0_EL1.PMUVer for the guest. The exception case is when using the PMUVer to determine the valid range of events for KVM_ARM_VCPU_PMU_V3_FILTER, as it has been allowing userspace to specify events that are valid for the PMU hardware, regardless of the value of the guest's ID_AA64DFR0_EL1.PMUVer. KVM will use a valid range of events based on the value of the guest's ID_AA64DFR0_EL1.PMUVer, in order to effectively filter events that the guest attempts to program though. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/pmu-emul.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 6fb5c59948a8..f0cbc9024bb7 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -36,12 +36,8 @@ static struct kvm_pmc *kvm_vcpu_idx_to_pmc(struct kvm_vcpu *vcpu, int cnt_idx) return &vcpu->arch.pmu.pmc[cnt_idx]; } -static u32 kvm_pmu_event_mask(struct kvm *kvm) +static u32 __kvm_pmu_event_mask(unsigned int pmuver) { - unsigned int pmuver; - - pmuver = kvm->arch.arm_pmu->pmuver; - switch (pmuver) { case ID_AA64DFR0_EL1_PMUVer_IMP: return GENMASK(9, 0); @@ -56,6 +52,14 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm) } } +static u32 kvm_pmu_event_mask(struct kvm *kvm) +{ + u64 dfr0 = IDREG(kvm, SYS_ID_AA64DFR0_EL1); + u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, dfr0); + + return __kvm_pmu_event_mask(pmuver); +} + /** * kvm_pmc_is_64bit - determine if counter is 64bit * @pmc: counter context @@ -947,11 +951,17 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) return 0; } case KVM_ARM_VCPU_PMU_V3_FILTER: { + u8 pmuver = kvm_arm_pmu_get_pmuver_limit(); struct kvm_pmu_event_filter __user *uaddr; struct kvm_pmu_event_filter filter; int nr_events; - nr_events = kvm_pmu_event_mask(kvm) + 1; + /* + * Allow userspace to specify an event filter for the entire + * event range supported by PMUVer of the hardware, rather + * than the guest's PMUVer for KVM backward compatibility. + */ + nr_events = __kvm_pmu_event_mask(pmuver) + 1; uaddr = (struct kvm_pmu_event_filter __user *)(long)attr->addr; From patchwork Fri Jul 28 18:19:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13332258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DC1FC0015E for ; Fri, 28 Jul 2023 18:20:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235817AbjG1SUM (ORCPT ); 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Fri, 28 Jul 2023 11:20:07 -0700 (PDT) Date: Fri, 28 Jul 2023 11:19:06 -0700 In-Reply-To: <20230728181907.1759513-1-reijiw@google.com> Mime-Version: 1.0 References: <20230728181907.1759513-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230728181907.1759513-5-reijiw@google.com> Subject: [PATCH v2 4/5] KVM: arm64: PMU: Don't advertise the STALL_SLOT event From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently, KVM hides the STALL_SLOT event for guests if the host PMU version is PMUv3p4 or newer, as PMMIR_EL1 is handled as RAZ for the guests. But, this should be based on the guests' PMU version (instead of the host PMU version), as an older PMU that doesn't support PMMIR_EL1 could support the STALL_SLOT event, according to the Arm ARM. Exposing the STALL_SLOT event without PMMIR_EL1 won't be very useful anyway though. Stop advertising the STALL_SLOT event for guests unconditionally, rather than fixing or keeping the inaccurate checking to advertise the event for the case, where it is not very useful. Suggested-by: Oliver Upton Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/pmu-emul.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index f0cbc9024bb7..68f44f893b44 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -754,8 +754,7 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) * Don't advertise STALL_SLOT, as PMMIR_EL0 is handled * as RAZ */ - if (vcpu->kvm->arch.arm_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4) - val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32); + val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32); base = 32; } From patchwork Fri Jul 28 18:19:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13332259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2060C0015E for ; Fri, 28 Jul 2023 18:20:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235868AbjG1SUX (ORCPT ); Fri, 28 Jul 2023 14:20:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235910AbjG1SUU (ORCPT ); Fri, 28 Jul 2023 14:20:20 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50F724487 for ; Fri, 28 Jul 2023 11:20:19 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5840614b107so25167017b3.1 for ; Fri, 28 Jul 2023 11:20:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690568418; x=1691173218; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=2xpjPS24yC6WEaeqRzU4H7WlQVocjOmJ6iEHs3rd81g=; b=sb2e2ZicSoE/37geVNg2mh/h4mq9S8CUzH9QMg9+39Ayh8kR7c1EYB4Rv3pgMM7fq2 QAWPYWqDZ0lg+u3wNr50hD1JBmCXsagcMNol3qqVr9A0Vaea+UjBHyulaWRkhlkhQkjN GEfMqAftZfvBNVxT2Q25jJkD+pTC9PKkFy+XMJXNRl6qj2ev1nN4xMLBqXAy0Sx7PbTO 1AcTIVQeGb4HHnP8u+0VTSD22iyXQFDSnjl1bKavsRMD562NrSOYP8OX+vPoK5rm51wU 2JJFJzQFz4VzSFyooEzfTWRn/QQh0WwgNySDamrd97nPZoLr1WbDBpDtf1SlqKVsVSoT TmyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690568418; x=1691173218; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2xpjPS24yC6WEaeqRzU4H7WlQVocjOmJ6iEHs3rd81g=; b=d+siEfuWek5cjKk8YIAwD0y9lV1See9I4nX/H4QZVYFiutk1Gb1V5ZfXC1GsW6pLW2 FPDQfwa/EFf2TtXenijYzCdDxHRHDXD0qFGKJyukpfStk3+MT+bf3BdZZpsFwx4HlGrj ySo5bDuxYBP4YVYfHE6HGAcax5lUBmR6VqaZA0GQ6ne1JuntWLiouYpqo8gZroVnzwJs SvhvqHcyv9a+zvNKnHLMQ3GJB0dsHsO1o6Z8I3UHtJ4EmTR+Lw6tvdD/qJ5zrkg+cccv p1Vx2LVKuY0cofH87sxme5Fe3HNPabopg9V6ZpQajegUpDZqAPaS8ZvRk1gu1HW4a68c g71A== X-Gm-Message-State: ABy/qLYYvEADnf1bJzl1fk+wvh0jb4UKxq5vX+UyenJ/XX0DscPfqwXS 76DpTDpTwpLl4o7cHFWc747I6SNSLZU= X-Google-Smtp-Source: APBJJlGGMEKDyFVWW5wq3CmTjmWkAG6EK1Hulf1y3IEUhbUXkjIOZDJYusNOd29d4Wx+PcVgk7IhawHjcJc= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a05:690c:708:b0:583:96da:32dd with SMTP id bs8-20020a05690c070800b0058396da32ddmr20691ywb.0.1690568418572; Fri, 28 Jul 2023 11:20:18 -0700 (PDT) Date: Fri, 28 Jul 2023 11:19:07 -0700 In-Reply-To: <20230728181907.1759513-1-reijiw@google.com> Mime-Version: 1.0 References: <20230728181907.1759513-1-reijiw@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230728181907.1759513-6-reijiw@google.com> Subject: [PATCH v2 5/5] KVM: arm64: PMU: Don't advertise STALL_SLOT_{FRONTEND,BACKEND} From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Don't advertise STALL_SLOT_{FRONT,BACK}END events to the guest, similar to STALL_SLOT event, as when any of these three events are implemented, all three of them should be implemented, according to the Arm ARM. Suggested-by: Oliver Upton Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/pmu-emul.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 68f44f893b44..47a27941163c 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -751,10 +751,12 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) } else { val = read_sysreg(pmceid1_el0); /* - * Don't advertise STALL_SLOT, as PMMIR_EL0 is handled + * Don't advertise STALL_SLOT*, as PMMIR_EL0 is handled * as RAZ */ - val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32); + val &= ~(BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32) | + BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND - 32) | + BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND - 32)); base = 32; }