From patchwork Mon Jul 31 08:46:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hui Wang X-Patchwork-Id: 13334065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D08AC001DF for ; Mon, 31 Jul 2023 08:47:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=9JYt0OFNXlrJOoOScnRNcmtqv2NC690Yk38dOFeiTOU=; b=LLKvY34M01mql1 T786cH0//JgmRiJOaS2B6jQRTzddCiswMDnsAYoRRIEnyHTHmiMr4BdI9SzKVJ7a+UiN+b5LIGbLy J2xRJmwHHZwGMj2P8lMkMKsrgmWULsVc9hj++G3+8k9q4OjpfruxLvBn1E+/fOCfxnjz//p9rImti jYGX4UWDIi40MUWOJ+9CnZfjZlbPDGPJyYHte9j+JmtsRrPplR1HE/6rb3fEIJBJYTSCgtQY8fZ/i 8HLxprMvalGyb/d65kqrGrML3ofWxSTskzIWaUVl6NDInBscH37ICnIHb87F0dIlKG4LYnVijDDjb bgfJrm/5Le2awBW3wTNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qQOXx-00EaKu-1u; Mon, 31 Jul 2023 08:46:33 +0000 Received: from smtp-relay-canonical-1.canonical.com ([185.125.188.121]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qQOXu-00EaKB-21 for linux-arm-kernel@lists.infradead.org; Mon, 31 Jul 2023 08:46:32 +0000 Received: from hwang4-ThinkPad-T14s-Gen-2a.conference (unknown [114.249.186.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-canonical-1.canonical.com (Postfix) with ESMTPSA id 211B44025D; Mon, 31 Jul 2023 08:46:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1690793182; bh=2Xbf5doZGjbZsmH5DYil6iL/g/jDlmIssMGgFKwPkvk=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=jz3Myw6aanH/j6tLUClMhl+RGQqVSuSAxSlWLOyJXfQZH68B9vY4a1TDjU9xO95tY paMKDK11iPKAhFaShBJlmbRoz/3Qg2DojsQY/2dWN2zgsie+zr49gOlh3naUz+2aaP Ie6d4VWVEpQir1Rtw1UvpDxKPRJa48Tlbc0pYcPnZvcsTdNH2xdT1DxahfQMlEYo/7 Em1rt5bOFyAGI1hVwpr3LeemxDCfz0cTg7IHwYLavHFDMlNIIFM129yuN257uCnsYU 1pOCR4OGKfI1iKPOqWmSy305RnPpu8NB1TuOGaji1eubRdvgd+rC2CRuoLWZiFAqOE XV8mX0VJbbySA== From: Hui Wang To: linux-arm-kernel@lists.infradead.org, shawnguo@kernel.org Cc: leoyang.li@nxp.com, s.hauer@pengutronix.de, hui.wang@canonical.com Subject: [PATCH] arm64: dts: ls1028a: add l1 and l2 cache info Date: Mon, 31 Jul 2023 16:46:14 +0800 Message-Id: <20230731084614.59785-1-hui.wang@canonical.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230731_014631_067110_07D2489E X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When we ran the stress-ng cache related stressors, we got the log as below: ubuntu@ubuntu:~$ stress-ng --l1cache 4 stress-ng: info: [656] defaulting to a 86400 second (1 day, 0.00 secs) run per stressor stress-ng: info: [656] dispatching hogs: 4 l1cache stress-ng: info: [657] stress-ng-l1cache: skipping stressor, cannot determine cache level 1 information from kernel This is because the l1 and l2 cache info is missing in the devicetree, ls1028a has dual cortex-a72 cores and has 48KB icache, 32KB dcache and 1MB l2 ucache: - icache is 3-way set associative - dcache is 2-way set associative - l2cache is 16-way set associative - line size are 64bytes Signed-off-by: Hui Wang --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 9cbb31191cf9..eefe3577d94e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -28,6 +28,12 @@ cpu0: cpu@0 { reg = <0x0>; enable-method = "psci"; clocks = <&clockgen QORIQ_CLK_CMUX 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -39,6 +45,12 @@ cpu1: cpu@1 { reg = <0x1>; enable-method = "psci"; clocks = <&clockgen QORIQ_CLK_CMUX 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -48,6 +60,9 @@ l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; };