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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id h18-20020adff192000000b003113ed02080sm15296992wro.95.2023.08.01.01.55.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Aug 2023 01:55:06 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Andrew Jones Subject: [PATCH v3 1/4] riscv: Improve flush_tlb() Date: Tue, 1 Aug 2023 10:53:59 +0200 Message-Id: <20230801085402.1168351-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230801085402.1168351-1-alexghiti@rivosinc.com> References: <20230801085402.1168351-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: CD4D7140002 X-Stat-Signature: bf9t5g9iabfp51bbpab8fcs7qmh39119 X-HE-Tag: 1690880108-179503 X-HE-Meta: U2FsdGVkX1/dc56DFFY7Z4U98rAe6m4OvWFRn5qkdOTVL7/TzqEJ6imZfMUw9Dref7T8UCBc45H7qYVYD+fJxlYjlxdGBz8iQMlpQmcH5mCTry2UnMyevu93yk3XrQdBciq3yJX8DV+diJlYEqmFWlZFMrbjykbrTGweBR/grCUyiX1xONFojmwp4sjac3zRb/yN3c06BXvr1NhLR2skksr+4BgwWX3i3tGTNXrx2AWxvzXk92qxjMDNHn+hu/30t0VdIsenZWNSI6pWyeZIFDRGKRriMX2t4teMEUnkjitq3HNYDJH/YfINaI8CdvuG0oOOYVxP8ZmgJmXoYKujkw9sM1j2q0mbbIsNwy7gtVSqH96s0YCqMzSjPNnJflixLtDpHO1qbV68wjp8sAfBl+044uTSiDSh1Jug5j+KXBzGpmxX9P1Gg3ww2z23UM7zZd4kaHPrA8ZY5WLDNCmv1A8D+4rBBQJplSu0eSBsOg6aMD9S1HUMahgOZhXgXCJz3naP+EzY5TiotfnAaqLhkpSQ18Sn6cDnhKdJug0xLQS0dXTrfvltuKyTmTODX6UIjys5h5wXah2wAt50L5OnBr1nFOMFcgHB42vDxRuuSsQC8PWvRakBVDsh+W2HtuvRO/NEeDJ50GiMOpMXTRgVCRuQFhNKB1y+HTx+gANpNJhJH6AOR40y5O0Cq8qi7KgJ9f2vJxiHNf6jA40GZX4xw1iOH8VknptO/9UgG1vqUxplL8AbISfLgawwM18bCEi1Fwvu/k21q+SF+tcORAqMB1mSweAXZ5L8MX4xqjHf2VWYDhWXo3yUk9fic+WEegKk4Jtfpi0CPUpQzPZo5F0QEgJcj6UllwumUbRF3mtvzBagvyToZ5ZsPvq1TOpxJdbTpo1r8lAq0GxQKeq0TQeQLd5ZOfT/aAgJVgD3gy1xHEEJRDEInTdUypCyhgR4Q4ZIesNMuYVRfFpHFRDaDNz 181aF8b7 9HJECJ4WfPaNzq+qpnx9EU+EZrZWRJ5vqK8CkP4LkBlkFw81gpTssPNhz1i8JvPnX6jkRr9xd2s681CVS+VMLLeJWQsFpPl8nmJ5a2WddFZVINQp+kC5u1ZZV7B9NOMSeS0345+T/i+ehwax0qAi9aYKT+bBMeuJ2irEXdZLkvYndAhumtRuWoH/UCM01m+wwDDKQ4sv3VyXY1oaoMi8i2sNBxSw/Kt+Wk0OsNEtkYnUMYVfbCAWFK3J7GHp55DdAo3a4mUh4GPIrSX774oJ9B1RdmSZa8oJxdPXfYN5JGQUH3QwXhVXXvgyz5ij7nRZu5k6mhEl6ciYLEhZI6en6OYY4bvgdUKYFJn+Nw4K8fftVd9s2VAknRtQtFxCALpDnFQ05572HbrkRBubNZwxJZIlQygIVdGxnC92Z9aHQ/k86NGA2jqpVf+PANaiJX+CC3HzWd5lV2tTfDMCOdoyfiwneURQpPFc4v8p8rPdlje+Q8bp18lDeHpSK9X/eQY43PuIOW8be7R5Tev8nGmDjS96Btl/ykg/KhETlcGQQxXBTXGY= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: For now, flush_tlb() simply calls flush_tlb_mm() which results in a flush of the whole TLB. So let's use mmu_gather fields to provide a more fine-grained flush of the TLB. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- arch/riscv/include/asm/tlb.h | 8 +++++++- arch/riscv/include/asm/tlbflush.h | 3 +++ arch/riscv/mm/tlbflush.c | 7 +++++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.h index 120bcf2ed8a8..1eb5682b2af6 100644 --- a/arch/riscv/include/asm/tlb.h +++ b/arch/riscv/include/asm/tlb.h @@ -15,7 +15,13 @@ static void tlb_flush(struct mmu_gather *tlb); static inline void tlb_flush(struct mmu_gather *tlb) { - flush_tlb_mm(tlb->mm); +#ifdef CONFIG_MMU + if (tlb->fullmm || tlb->need_flush_all) + flush_tlb_mm(tlb->mm); + else + flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end, + tlb_get_unmap_size(tlb)); +#endif } #endif /* _ASM_RISCV_TLB_H */ diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index a09196f8de68..f5c4fb0ae642 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -32,6 +32,8 @@ static inline void local_flush_tlb_page(unsigned long addr) #if defined(CONFIG_SMP) && defined(CONFIG_MMU) void flush_tlb_all(void); void flush_tlb_mm(struct mm_struct *mm); +void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, + unsigned long end, unsigned int page_size); void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); @@ -52,6 +54,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, } #define flush_tlb_mm(mm) flush_tlb_all() +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() #endif /* !CONFIG_SMP || !CONFIG_MMU */ /* Flush a range of kernel pages */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 77be59aadc73..fa03289853d8 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -132,6 +132,13 @@ void flush_tlb_mm(struct mm_struct *mm) __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } +void flush_tlb_mm_range(struct mm_struct *mm, + unsigned long start, unsigned long end, + unsigned int page_size) +{ + __flush_tlb_range(mm, start, end - start, page_size); +} + void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); From patchwork Tue Aug 1 08:54:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13335912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CE30EB64DD for ; Tue, 1 Aug 2023 08:56:12 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 293D58E000B; Tue, 1 Aug 2023 04:56:12 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 21D4E8E0002; Tue, 1 Aug 2023 04:56:12 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 10C268E000B; Tue, 1 Aug 2023 04:56:12 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id F29D98E0002 for ; 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id l12-20020a7bc44c000000b003fe215e4492sm4763826wmi.4.2023.08.01.01.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Aug 2023 01:56:08 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Andrew Jones Subject: [PATCH v3 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Date: Tue, 1 Aug 2023 10:54:00 +0200 Message-Id: <20230801085402.1168351-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230801085402.1168351-1-alexghiti@rivosinc.com> References: <20230801085402.1168351-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: DE347100007 X-Rspam-User: X-Rspamd-Server: rspam05 X-Stat-Signature: whyr45hzsxst1bgtux55rqjnfkejhoju X-HE-Tag: 1690880169-965622 X-HE-Meta: U2FsdGVkX1/87ot5gLpwjMOuRe0FIah+PYErkjQuTB/pwDzOjLba6v+YQmp4dryA7lz+YdJhayEQ2If+F5uqHYcidvHqnFZ7Xx8yeYnfBt5UQH8T0HbvMSQNb5cdh6xJyq87tFrwZTQ/+bScv4LnBtJNnsFZ1c/Hzg/DQpUp9j3GsSVcoSE6N4wZYkuisSRQvKjMR+dqj2qoUEMG15GjqjJKaYkHMFPARDCLH+w5/60Nbd5PxSG0Wgm1FfVcgIwtRxcoTsE0oGDSOoR7eCivIvtDiFuXSQiVPZDI+qIfVeAFz6z9ooza0579Mv1K/P2558GwIbh2KIZEz2FS64WOGHPVnQs/Le7UrzMBijikaSRuDTPYmgc3O3LrLzs/mda3nSNIzfC+exwFSAQ98KPs4nJ/xHCJpwQiiMwMNPgYU90tsAsVUaR8DjsJLc87xewvYY+cKh0lJjshjSrraGUI1a8mZKL8iSkLpUPnHJZV9mtgzVLoJLyTtpOj0koI6s5jt/Kup6QRYyx0K9vI/C6j2zd8Oi8KfIAK+hvLVTMG1cg/64J5czDWbomYhQ4Pika+B+LWwZtyBJGmvniWKX+5QMDw/mPrmHhJdzI0ApcLXD97HNHKHb9tXzh5J4obo0D041zp07ryCiUG5ERl40aP92k0zWV5HIdRv7udBrqAPmYwGQ0pO3lA0F9MhpwQNW9Z8Gy61YUiSFKiMj++I8TT5sBcvlgliyBojDUKtf9n3KsPrB3n6V0aZtg6RvkYNNbd40pk8l/qMI+sQR7QUpS5BduzvWoKXJaLdwMPfy6eXl7tHYm1DViO3EvXaCGJQ4FNWNzAR5LDA49oWcjz47R2vsDm2UgGB+9iAQZWHbNC+j9y/HxTM1gkEWLGtUrNvWwFALCrwqlKkzrKMyhXr4vK1veLATmhH3IpozeL+oSPvaNOwbGd/f0ts/yb5VGvBUMWu68kcLbEAVWTc2XOpuN vil40sT+ Bq/aTOKUjxNWPEVspFEaA6STYkxx4HQhejg9n516V8FHCu1YovLMqU/i5D21C1P99dWjNzi5BR0EMBwm+HnSm0uAmhDvhio3jrW9LrAaJrygsrFO1+dNSoo2p3WVLp5uRBS5qGWyJUQGFOc8uMujaf+yvp9x1qh3z1/+ewLET3WuEiQx7vZTi5h76qOkyZpbGcTnKK2esWstv7w9jU88UD0Fc8RUL08/zdRV/GQvR9+nE9bn7Sg5qjJVKgFKodS81dLW5FtMuudu+ksf++DzLtqFBc6BWXvP5VoAB9jfB9vn95Ci0k4u8IfrSvx2xJxHFILNWQMOsuhBBk++a8tmC8HTnX2rpe0uRk3o8VrvWbvhDuGf5g0UjLwbk2qtTM5Iz+h5cZZf7ftOXUm9brxX6pbKShKThZqVZJQSND7TbOzUvDsZhLk0jZH97eJcUm26RMY9on3O12lVawGnUytbmwALZnapDQNb+973T6ItBeCm5Io1LxYJV/yMSteWpJe33JAxOj6MqJlY/rvB5K4nvx0HCD01JXnI8HBrQ7XXwxQQwTDo= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: flush_tlb_range() uses a fixed stride of PAGE_SIZE and in its current form, when a hugetlb mapping needs to be flushed, flush_tlb_range() flushes the whole tlb: so set a stride of the size of the hugetlb mapping in order to only flush the hugetlb mapping. Note that THPs are directly handled by flush_pmd_tlb_range(). Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- arch/riscv/mm/tlbflush.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index fa03289853d8..d883df0dee4a 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -147,7 +148,13 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); + unsigned long stride_size; + + stride_size = is_vm_hugetlb_page(vma) ? + huge_page_size(hstate_vma(vma)) : + PAGE_SIZE; + + __flush_tlb_range(vma->vm_mm, start, end - start, stride_size); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, From patchwork Tue Aug 1 08:54:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13335925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22E6CC001DF for ; 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id l27-20020a05600c1d1b00b003fe1b3e0852sm2908793wms.0.2023.08.01.01.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Aug 2023 01:57:09 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Andrew Jones Subject: [PATCH v3 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Date: Tue, 1 Aug 2023 10:54:01 +0200 Message-Id: <20230801085402.1168351-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230801085402.1168351-1-alexghiti@rivosinc.com> References: <20230801085402.1168351-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Stat-Signature: b7skkqhzbrskishz8a71exgcgna8ch3e X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 745EA40018 X-Rspam-User: X-HE-Tag: 1690880231-488944 X-HE-Meta: U2FsdGVkX196I6bMDWfLgVvcGrfEGCUrCr6gH9EyPgXQtgLmtlFScvzGx2E5mzSiVQFsDn7iLbY5ljLdiLAc1Iwybjvg4wogh+EoGAnbFPmk+V0kC2BRr/dUeR6i/dNDlxPrguBY9gEUZis5oYsyh+Mf0YgLusdxmm+arjS74CFXeNnr7kqf0cVy/NNxyY5RpPjmF1VnHKo7nB0NlApWqNXHSyksNGODxydQjEEhjHY6REiAm2naBSLhESnnPTB8KPo2Okdj38XKHVQdc1sBn6OJIFuOK6f4jBaCAfTOQ1ZQ4LuBf50KYE43kzdVPVkE6Gn9eOmOpT/7TlZUE9bJTkSMGwJ/rGoW3EwZ5ryMg2jw3yK/Rh5zWKp+Bh2ADIp6QpURAFOHW1mxKm4gqAj8eXqvK0tTjjd/yeJQ40YY1oiN9Pwr+SKHXVmHpCFiCjscSKuJCfHE5bgMJdQjn0nyXdgDwy2B6bTU4MquSIGYhsU7J4gjKOrZYZfolVIAY3DiDiAbWxXxI+WJhu9+CBADcgGMgYonmXMYO03Lu2Lri1rvj4lnqrwDRiLMcH4azY7dhRAGxlmnIKRVw2yso5vOLK4isvw/rke2hlw3YIxq7/PzGxXVHN2YLHSZcgHUcYbvSYMINieO45avodOVGBBogA281WIF30PRAsWrDkGIFo11pMGIUHVQF+K/YxTOnj8JxKAMOf3VWiRcvdrESeXpAbqt9TyGp2t9dKDjxN9q8XvnMubbxhjd7ekTnjOMywAnoqF2aUK/hlpTlhpaC987+EyzRux6EpXWw2ak/+G/B6pqkHVHw4QgfJpH7fc9GDKjc6xhiEPxkwtKFT0MGbnOdG1VWlxknqCQcpYKJlgs9UIZTyy0fmd/wUxM83KtQV0FhqoIK1sZDjIfAtVZlD9sEm8NX5ZGnJTafb1ytH0CUc5Y8/rbuLQGHYRIB51klq57SLNIQcOGcL1BdZ1nMVb 05TYBh8v Kf/RW5QsQov/DYlTvbFu5v4AFr2meMxGBBdDaLeCJantDAN063cE4dqGXa6DTOMURBdb1xrrJPdfMb7olq3I1qo6Nm6vHSUUkr3g5T6DfytIPy7qoJuMRbcXjstYBWqjeT6fxhReCuk54RYlPBDp94w5Z/6wY+FtHmJVhr19xYsxwvnse017DW/PCc8vjbMuw+HO4zpEkNSafvX0dO6knikO/0vwJ/aei+7Dy4/3mpKAAgGF8deWKXJY6wCygIMJKSpwYidQnpIsmghXsi82X/V27fMvcdYAlE2bIblkXOZFbNaza8aK3rdR9iwZWpP/E5KyR61wKURRDPrPAAr/lQOugH6+2YmuFDNY/PZLPDxUu/SqfJ2Zq+DnBeda9yFnUWmXZ0R8UqBvR/insxPXFoibNbLc/TWGNkwynJYGlY4Nx8fQgDatPVWb/EekpohxUGnlWrfQ0D83xURkIqDZLNtkCGLU4FTGUvwbaR1W/1Y8Y/1rojlqsGt2lYa9ktaz0es3TpBCHvDrPUngB66rqjkdB4AJMtsMzXa7BApAC8BU3W6o= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Currently, when the range to flush covers more than one page (a 4K page or a hugepage), __flush_tlb_range() flushes the whole tlb. Flushing the whole tlb comes with a greater cost than flushing a single entry so we should flush single entries up to a certain threshold so that: threshold * cost of flushing a single entry < cost of flushing the whole tlb. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- arch/riscv/mm/tlbflush.c | 48 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index d883df0dee4a..0c955c474f3a 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -7,6 +7,9 @@ #include #include +#define FLUSH_TLB_MAX_SIZE ((unsigned long)-1) +#define FLUSH_TLB_NO_ASID ((unsigned long)-1) + static inline void local_flush_tlb_all_asid(unsigned long asid) { __asm__ __volatile__ ("sfence.vma x0, %0" @@ -24,13 +27,48 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, : "memory"); } +/* + * Flush entire TLB if number of entries to be flushed is greater + * than the threshold below. + */ +static unsigned long tlb_flush_all_threshold __read_mostly = 64; + +static void local_flush_tlb_range_threshold_asid(unsigned long start, + unsigned long size, + unsigned long stride, + unsigned long asid) +{ + u16 nr_ptes_in_range = DIV_ROUND_UP(size, stride); + int i; + + if (nr_ptes_in_range > tlb_flush_all_threshold) { + if (asid != FLUSH_TLB_NO_ASID) + local_flush_tlb_all_asid(asid); + else + local_flush_tlb_all(); + return; + } + + for (i = 0; i < nr_ptes_in_range; ++i) { + if (asid != FLUSH_TLB_NO_ASID) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_page(start); + start += stride; + } +} + static inline void local_flush_tlb_range(unsigned long start, unsigned long size, unsigned long stride) { if (size <= stride) local_flush_tlb_page(start); - else + else if (size == FLUSH_TLB_MAX_SIZE) local_flush_tlb_all(); + else + local_flush_tlb_range_threshold_asid(start, size, stride, + FLUSH_TLB_NO_ASID); + } static inline void local_flush_tlb_range_asid(unsigned long start, @@ -38,8 +76,10 @@ static inline void local_flush_tlb_range_asid(unsigned long start, { if (size <= stride) local_flush_tlb_page_asid(start, asid); - else + else if (size == FLUSH_TLB_MAX_SIZE) local_flush_tlb_all_asid(asid); + else + local_flush_tlb_range_threshold_asid(start, size, stride, asid); } static void __ipi_flush_tlb_all(void *info) @@ -52,7 +92,7 @@ void flush_tlb_all(void) if (riscv_use_ipi_for_rfence()) on_each_cpu(__ipi_flush_tlb_all, NULL, 1); else - sbi_remote_sfence_vma(NULL, 0, -1); + sbi_remote_sfence_vma(NULL, 0, FLUSH_TLB_MAX_SIZE); } struct flush_tlb_range_data { @@ -130,7 +170,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, void flush_tlb_mm(struct mm_struct *mm) { - __flush_tlb_range(mm, 0, -1, PAGE_SIZE); + __flush_tlb_range(mm, 0, FLUSH_TLB_MAX_SIZE, PAGE_SIZE); } void flush_tlb_mm_range(struct mm_struct *mm, From patchwork Tue Aug 1 08:54:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13335926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C0E4C001DF for ; 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id c6-20020a05600c0ac600b003fe20db88e2sm5255370wmr.18.2023.08.01.01.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Aug 2023 01:58:10 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Andrew Jones Subject: [PATCH v3 4/4] riscv: Improve flush_tlb_kernel_range() Date: Tue, 1 Aug 2023 10:54:02 +0200 Message-Id: <20230801085402.1168351-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230801085402.1168351-1-alexghiti@rivosinc.com> References: <20230801085402.1168351-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 35C4318001E X-Stat-Signature: 6iahcpbmegdyn8rg8hizy4ui9dxyfhys X-HE-Tag: 1690880291-481436 X-HE-Meta: U2FsdGVkX1+ZMs9KFuPGaGrGtJ8aVK/LwrClulh+cvR5YA+ynHr1ckh6GOKktz62wDl70ORdrgzgeAVv3SiBpmI5zDC6N1FVvjNLPw8LYQumb1pSxexSI+8HlGeH9tCj9AYzejt7vTu/bVNVfxmauzD3+B3jklh2lqYW21XShrypisuoExfnZFI1VKG+9ge4UZAlZfEEYlMcR9kIy/fPRW6n2TKxlGvezPcbJcrTznJCk8UZ+OIkgse2hxK47L6YhUWqgfycqmtoZoCMIqaBD5IWlJ+qwXHJsGT1nQvK+efsp404+nDKVoMEOzIvPYFypXykMs4+6CCItl//O1FFIyxgi/ml3cyoF6GGENAx5491+JIkYbL1XDrAvZu/MY6MysvZYbLyOIL1vJFl3urMDD1TL11dSJpwDcsZjeVrMZYWWdwsUOoWeEDeZL3TfpcNiPkZE3cgJdO7u7EpNwwWrUrXRhnHT/KvIIqsw0owA1XyCrYc7wClIoeAlRA/ZC9X2DfiLojpzxW+XKW/iFSPo4I6CAHZfOL+c1Smn+wcnd6MaUg4YOMQBADjvw9rF5q3KAOxeJwEKzzyjdzyU7OT0gSZdW0HKwFiou2m35W2wdX7d/mDnGLVm0aq/iGhda0i7TNsU46ERKVQ3H3miS8zqdzOrh/qxTnKtTSHvwBgPhWnRyDdQBw9l6npMgsA1qnMRhFQxReJwxXYjtVOywvFkE0t6k8ztTwWxekF9dsIh5bWBSTYwiwb2znDXg9EeznB8RoIvtd5bpJJ7i2dFnBEPAgxz+/EQOaKxCms3zV+2fJi03L99/SkZ3Bj4a+hhhKhe4enBE7SKwOL8dB43BdxtBuZeoo2N5Cg/hfYC9tnq7+maks5qUHC1acydQvlAWSiLBoszF7vz3enVFpn+uxQjuEr8XDPgkOqwmYxPL0IpcXwgYhFvlhXVPJ+p1U/nTiV06SgpA6cZXH9oV6GXaH zJ/YlodE dr4gWbNW4JNEqb5a1b/wF3etUHSmKbvY3Hx8bXU+db5suOsVTk7cd1utePX8VRDboc+DuuvBwdnZzeXXPFnEOMRJARGOKk6hijrsUiP+WEt+oNCWzOJL8t2tL1hCS0g6xlsqnLb1y+8SITLkJf/X/IhzVY7IaHXunkwBYPCvZ5Q0FhDJIph9jO/zG7K3BtMo5Cq79rSDE/kIv2rYWUkfEeptCzhNCr72mYj//AoU16/2s1CQG0ma48w5bX6Uf77inqZWXcVnoISU8zAa3seyeH1JEoP5Vmu4fn7wZOyqnf7mqLlZQ/VAo6P81gI0Djp2kMiArWXL/cycZ7PsrCil3RjLjx3EYgqcI3dIyz0eLb0hq6Wh7tAxS2s82xMcWdeSEKIKrbbFzSnaglXPLFvkfui4szzy+sLImmKO/NY25FAXy3zQ/6O3XcqJX8K+0unYJLeAOP6NO8eFXJlACYgQpAeF/qxPmoHNIx4ebphBmFVpBGOEDJGyMtEk0uv64tfzCiCFvw7FoX4HRIULsHW1UeQAOOQFsvtWCECeY1QEMkklmiYs= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: This function used to simply flush the whole tlb of all harts, be more subtile and try to only flush the range. The problem is that we can only use PAGE_SIZE as stride since we don't know the size of the underlying mapping and then this function will be improved only if the size of the region to flush is < threshold * PAGE_SIZE. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- arch/riscv/include/asm/tlbflush.h | 11 +++++----- arch/riscv/mm/tlbflush.c | 34 +++++++++++++++++++++++-------- 2 files changed, 31 insertions(+), 14 deletions(-) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index f5c4fb0ae642..7426fdcd8ec5 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -37,6 +37,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); +void flush_tlb_kernel_range(unsigned long start, unsigned long end); #ifdef CONFIG_TRANSPARENT_HUGEPAGE #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, @@ -53,15 +54,15 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, local_flush_tlb_all(); } -#define flush_tlb_mm(mm) flush_tlb_all() -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() -#endif /* !CONFIG_SMP || !CONFIG_MMU */ - /* Flush a range of kernel pages */ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - flush_tlb_all(); + local_flush_tlb_all(); } +#define flush_tlb_mm(mm) flush_tlb_all() +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() +#endif /* !CONFIG_SMP || !CONFIG_MMU */ + #endif /* _ASM_RISCV_TLBFLUSH_H */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 0c955c474f3a..687808013758 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -120,18 +120,27 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long size, unsigned long stride) { struct flush_tlb_range_data ftd; - struct cpumask *cmask = mm_cpumask(mm); - unsigned int cpuid; + struct cpumask *cmask, full_cmask; bool broadcast; - if (cpumask_empty(cmask)) - return; + if (mm) { + unsigned int cpuid; + + cmask = mm_cpumask(mm); + if (cpumask_empty(cmask)) + return; + + cpuid = get_cpu(); + /* check if the tlbflush needs to be sent to other CPUs */ + broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; + } else { + cpumask_setall(&full_cmask); + cmask = &full_cmask; + broadcast = true; + } - cpuid = get_cpu(); - /* check if the tlbflush needs to be sent to other CPUs */ - broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; if (static_branch_unlikely(&use_asid_allocator)) { - unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask; + unsigned long asid = mm ? atomic_long_read(&mm->context.id) & asid_mask : 0; if (broadcast) { if (riscv_use_ipi_for_rfence()) { @@ -165,7 +174,8 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, } } - put_cpu(); + if (mm) + put_cpu(); } void flush_tlb_mm(struct mm_struct *mm) @@ -196,6 +206,12 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, __flush_tlb_range(vma->vm_mm, start, end - start, stride_size); } + +void flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + __flush_tlb_range(NULL, start, end, PAGE_SIZE); +} + #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)