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Tue, 1 Aug 2023 21:49:29 +0800 From: Kefeng Wang To: Andrew Morton , Catalin Marinas , Will Deacon , Mike Kravetz , Muchun Song , Mina Almasry , , , , , CC: , , <21cnbao@gmail.com>, Kefeng Wang Subject: [PATCH v3] arm64: hugetlb: enable __HAVE_ARCH_FLUSH_HUGETLB_TLB_RANGE Date: Tue, 1 Aug 2023 21:56:16 +0800 Message-ID: <20230801135616.165067-1-wangkefeng.wang@huawei.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801023145.17026-3-wangkefeng.wang@huawei.com> References: <20230801023145.17026-3-wangkefeng.wang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.113.25] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm100001.china.huawei.com (7.185.36.93) X-CFilter-Loop: Reflected X-Rspamd-Queue-Id: 3583940021 X-Rspam-User: X-Rspamd-Server: rspam11 X-Stat-Signature: kgi687rmw5gk1ichfaeg71xbqjkoybgd X-HE-Tag: 1690897774-433782 X-HE-Meta: U2FsdGVkX19AXDz3ZQ8Qe5LXBCZyRw/q3ZPUQoVrwNfUzVhPQp70/cChbM3j18kV6Tm5MVM2k074au04nL0elU4z74fkI5Dfir2bNIvr+zOZ4BmWK9UA+C/qfvWk15K9s0uQqEH94E94uDvBbpCkiWGZkva86BDEllJSe0xoY+HXSpg4pfx8K9WiI0UG6SRzdqp6ma2eEdcd/FDCCUas8Pglx7BbOefsS6zcfmkTvM5OZ6I/ew77YpSf9o6yvwxpcNsAv3vlzSoqfF4uyx/GuD7AIOLnVmbYCT6Cym+kno2Pq20HTscSCqLciPv+FUCkzMZNbAaOrOuzn51OCh6LOBMGcQtOl2lhyExXeK6W8oUhXClmAJZwqNbi2bHWRaB3m7quZueSiod9OeECX+m7jw6/Y4RYHs0D6N+93y2lxVllyCj3xG/W3abbfXBSKADvDjus2zMwCnDl7M1YSvnFLdPzfkSE9LdAwSRlMmlQrvfLr29xwEBZ2bSHe2ahFumP5Hv7YesUn6ENGezqx8l6JgeIRqcNOQsKnY+YAYGRTNCGRTsQO8iknjke8YN31h8zmAckdCXrT3/OPWufAjoBIWwJuj1QnUGXS/D5VDbXBvDAj+MotD6VNXx6Hh/+uNGAY6E70PWLFw7wPhh04L69wHTV5Ecoqqlfw3PN6adOAtild/iObD5oCy0kJn+lSXwLjNkdjonovN+eLNx7jXobPT1U69HFhrhqEuDmTW8ViWp9QUrNi0eZaf0n7GpVKkyxQUoUBwlzyC5K4U6IYtNJfru/gsAThKY3d2B06xAAHfl5BGuqVoD2SVZYGXvc2KGjGHUOFP+6RGuQHgOEXGvBJ1EFIm0UJ0LV9x54Pegpo35PhpabnLzd/I5UVYpPSd1ltIdTRdOzjDYQ1/qgVODwCk0x0F+QvJzAlGOkGPhjFb0Ejk4Lz08RyeYbcRbh6O3T2DyILNe4Bw0zfD2NfRz O0wRGsMV P6j4YRBKmfG191deualS88ycVH9enfv3aPuUeUgNuDAVKTZtK2uf78mae5p2cCAuH1DzK2uLESO8Kbswnz/OI6HqhCChUILQQDIhOy1H31vs8wZAg4nSJTpfw3WDIyMcnMeaBr/ViJcFZ6yGLARlBG/YuYJ0zUR694M7efq2hPAQilGkpZY+JDmUIwA9d5kUrflGufY+e481ujwl/Ohy0q2GXdJFRxUq0wQse X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: It is better to use huge page size instead of PAGE_SIZE for stride when flush hugepage, which reduces the loop in __flush_tlb_range(). Let's support arch's flush_hugetlb_tlb_range(), which is used in hugetlb_unshare_all_pmds(), move_hugetlb_page_tables() and hugetlb_change_protection() for now. Note, for hugepages based on contiguous bit, it has to be invalidated individually since the contiguous PTE bit is just a hint, the hardware may or may not take it into account. Signed-off-by: Kefeng Wang --- v3: add tlb_level hint by using flush_pud/pmd_tlb_range, suggested by Catalin Marinas arch/arm64/include/asm/hugetlb.h | 21 +++++++++++++++++++++ arch/arm64/include/asm/pgtable.h | 4 ++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h index 6a4a1ab8eb23..0acb1e8b41e9 100644 --- a/arch/arm64/include/asm/hugetlb.h +++ b/arch/arm64/include/asm/hugetlb.h @@ -60,4 +60,25 @@ extern void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, #include +#define __HAVE_ARCH_FLUSH_HUGETLB_TLB_RANGE +static inline void flush_hugetlb_tlb_range(struct vm_area_struct *vma, + unsigned long start, + unsigned long end) +{ + unsigned long stride = huge_page_size(hstate_vma(vma)); + + switch (stride) { +#ifndef __PAGETABLE_PMD_FOLDED + case PUD_SIZE: + flush_pud_tlb_range(vma, start, end); + break; +#endif + case PMD_SIZE: + flush_pmd_tlb_range(vma, start, end); + break; + default: + __flush_tlb_range(vma, start, end, PAGE_SIZE, false, 0); + } +} + #endif /* __ASM_HUGETLB_H */ diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 0bd18de9fd97..def402afcbe9 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -35,7 +35,7 @@ #include #include -#ifdef CONFIG_TRANSPARENT_HUGEPAGE +#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE /* Set stride and tlb_level in flush_*_tlb_range */ @@ -43,7 +43,7 @@ __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) #define flush_pud_tlb_range(vma, addr, end) \ __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) -#endif /* CONFIG_TRANSPARENT_HUGEPAGE */ +#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ static inline bool arch_thp_swp_supported(void) {