From patchwork Tue Aug 1 15:19:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 694DAC001E0 for ; Tue, 1 Aug 2023 15:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230327AbjHAPUY (ORCPT ); Tue, 1 Aug 2023 11:20:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234009AbjHAPUV (ORCPT ); Tue, 1 Aug 2023 11:20:21 -0400 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36BF61BFD for ; Tue, 1 Aug 2023 08:20:15 -0700 (PDT) Received: by mail-pf1-x449.google.com with SMTP id d2e1a72fcca58-6870e364e74so3001437b3a.2 for ; Tue, 01 Aug 2023 08:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690903214; x=1691508014; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=747YuA1Dx3SnOAWlrzcy+YkCaluTCLGvH8CPu7tzkC4=; b=4Fjv36NP8lCVIwsx0PzaNTkiNwo5hPlerQW1QsOJfYMtkV047Ll/r0RtmkZzhJalek I/KJmhiLZAC8fHFHn2YLO4WE0ovMwSxTJbzQJ16vnei+1rmckS6dmJNGRTXV14Eth9DN MTm4UbXHLhRm6vmxrdWEtASp/ef6HYG8si3LboTezWGQd4WonZ5Xi7eYVZ4R6nV2CTuv lCUadlN3DdlZOXQoqO8wyz273H2r+J5QShIbm85cBhUGn0u/21rNOLFiwMNUYYyww1rD ycBZ3ghYM7nsRvAxar4Ihvo7MpPR6ZU/CuhvXtDwIQ0oDYYfOx3hz4yz5evIYEkG91Tq pVYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690903214; x=1691508014; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=747YuA1Dx3SnOAWlrzcy+YkCaluTCLGvH8CPu7tzkC4=; b=a2h8EkaLM5jWcwyCLatSG3uMDZEkxsJPe7A1E+zRb2cZepIEwgzsn5Zd5gkjWsO8x5 0+VmAq2bkR6yRt7Rxx0Q4K0PfovNxkmW+dXWPzT/TA0FLWkCKBYMGifZJnpsA8R/Inks 76bpkNSrwYEuQup8oFRYo1iV8dqCfskKSIKPs29Rzrx2R7lY0l5kZ8OtZmZ2Y8D4FlMd 9VzG75HkNQBaVCh1HNWGViW3BI4immk1UBr7/FwCvOZqxWk2DXcirmjdOoF4+B852Pc6 LQLjmeSPMtT8QaJkGStT8JeMt/sOCNbmmYn6eXnlfLb7n5INa1O/IrrvejVb8c3bL4Y2 xjew== X-Gm-Message-State: ABy/qLbV5EmU6zXkei+Zv/O3vX2IKfGiAnBbmHVVhZ8ImLU2UKeyGvFA 6BsKNjPJVKgsiJGJ61IBvcVGwCrk6BhcCdtn1R2sOYFDsRXwFFyqRGxdPpn2bFBPR3ElYdOEG5T Zbbdkoq9QuxbQ8Q5Ibm74TawgA+ZVtuNctWpB9SV+3fcNCoEM4hauw3c7HDUrSwHu/XSJIzs= X-Google-Smtp-Source: APBJJlFYIduNuYy0wvIby8yBJwkrjNp6LvpOSugL72WbrXU69i6bGxB5cmDBygkjJXCN14JhWaFyNL7KmMaDXCMNOw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a05:6a00:21c3:b0:66a:4525:8264 with SMTP id t3-20020a056a0021c300b0066a45258264mr97688pfj.1.1690903213191; Tue, 01 Aug 2023 08:20:13 -0700 (PDT) Date: Tue, 1 Aug 2023 08:19:57 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-2-jingzhangos@google.com> Subject: [PATCH v7 01/10] KVM: arm64: Allow userspace to get the writable masks for feature ID registers From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a VM ioctl to allow userspace to get writable masks for feature ID registers in below system register space: op0 = 3, op1 = {0, 1, 3}, CRn = 0, CRm = {0 - 7}, op2 = {0 - 7} This is used to support mix-and-match userspace and kernels for writable ID registers, where userspace may want to know upfront whether it can actually tweak the contents of an idreg or not. Suggested-by: Marc Zyngier Suggested-by: Cornelia Huck Signed-off-by: Jing Zhang --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/uapi/asm/kvm.h | 25 +++++++++++++++ arch/arm64/kvm/arm.c | 3 ++ arch/arm64/kvm/sys_regs.c | 51 +++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 2 ++ 5 files changed, 83 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index d3dd05bbfe23..3996a3707f4e 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1074,6 +1074,8 @@ int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, struct kvm_arm_copy_mte_tags *copy_tags); int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, struct kvm_arm_counter_offset *offset); +int kvm_vm_ioctl_get_feature_id_writable_masks(struct kvm *kvm, + u64 __user *masks); /* Guest/host FPSIMD coordination helpers */ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index f7ddd73a8c0f..2970c0d792ee 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -505,6 +505,31 @@ struct kvm_smccc_filter { #define KVM_HYPERCALL_EXIT_SMC (1U << 0) #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) +/* Get feature ID registers userspace writable mask. */ +/* + * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model + * Feature Register 2"): + * + * "The Feature ID space is defined as the System register space in + * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, + * op2=={0-7}." + * + * This covers all R/O registers that indicate anything useful feature + * wise, including the ID registers. + */ +#define ARM64_FEATURE_ID_SPACE_IDX(op0, op1, crn, crm, op2) \ + ({ \ + __u64 __op1 = (op1) & 3; \ + __op1 -= (__op1 == 3); \ + (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ + }) + +#define ARM64_FEATURE_ID_SPACE_SIZE (3 * 8 * 8) + +struct feature_id_writable_masks { + __u64 mask[ARM64_FEATURE_ID_SPACE_SIZE]; +}; + #endif #endif /* __ARM_KVM_H__ */ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 72dc53a75d1c..c9cd14057c58 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1630,6 +1630,9 @@ int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) return kvm_vm_set_attr(kvm, &attr); } + case KVM_ARM_GET_FEATURE_ID_WRITABLE_MASKS: { + return kvm_vm_ioctl_get_feature_id_writable_masks(kvm, argp); + } default: return -EINVAL; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2ca2973abe66..d9317b640ba5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3560,6 +3560,57 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) return write_demux_regids(uindices); } +#define ARM64_FEATURE_ID_SPACE_INDEX(r) \ + ARM64_FEATURE_ID_SPACE_IDX(sys_reg_Op0(r), \ + sys_reg_Op1(r), \ + sys_reg_CRn(r), \ + sys_reg_CRm(r), \ + sys_reg_Op2(r)) + +static bool is_feature_id_reg(u32 encoding) +{ + return (sys_reg_Op0(encoding) == 3 && + (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && + sys_reg_CRn(encoding) == 0 && + sys_reg_CRm(encoding) <= 7); +} + +int kvm_vm_ioctl_get_feature_id_writable_masks(struct kvm *kvm, u64 __user *masks) +{ + /* Wipe the whole thing first */ + for (int i = 0; i < ARM64_FEATURE_ID_SPACE_SIZE; i++) + if (put_user(0, masks + i)) + return -EFAULT; + + for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { + const struct sys_reg_desc *reg = &sys_reg_descs[i]; + u32 encoding = reg_to_encoding(reg); + u64 val; + + if (!is_feature_id_reg(encoding) || !reg->set_user) + continue; + + /* + * For ID registers, we return the writable mask. Other feature + * registers return a full 64bit mask. That's not necessary + * compliant with a given revision of the architecture, but the + * RES0/RES1 definitions allow us to do that. + */ + if (is_id_reg(encoding)) { + if (!reg->val) + continue; + val = reg->val; + } else { + val = ~0UL; + } + + if (put_user(val, (masks + ARM64_FEATURE_ID_SPACE_INDEX(encoding)))) + return -EFAULT; + } + + return 0; +} + int __init kvm_sys_reg_table_init(void) { struct sys_reg_params params; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index f089ab290978..86ffdf134eb8 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1555,6 +1555,8 @@ struct kvm_s390_ucas_mapping { #define KVM_ARM_MTE_COPY_TAGS _IOR(KVMIO, 0xb4, struct kvm_arm_copy_mte_tags) /* Available with KVM_CAP_COUNTER_OFFSET */ #define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_arm_counter_offset) +#define KVM_ARM_GET_FEATURE_ID_WRITABLE_MASKS \ + _IOR(KVMIO, 0xb6, struct feature_id_writable_masks) /* ioctl for vm fd */ #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) From patchwork Tue Aug 1 15:19:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04825C001DF for ; Tue, 1 Aug 2023 15:20:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233294AbjHAPU0 (ORCPT ); Tue, 1 Aug 2023 11:20:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234056AbjHAPUW (ORCPT ); Tue, 1 Aug 2023 11:20:22 -0400 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 002702107 for ; Tue, 1 Aug 2023 08:20:15 -0700 (PDT) Received: by mail-pg1-x549.google.com with SMTP id 41be03b00d2f7-5646e695ec1so599977a12.1 for ; Tue, 01 Aug 2023 08:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690903215; x=1691508015; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=a5ITWAYN9R9rtf6GERIf9S362dBjLzTbE/fVZh0ZgOI=; b=fTiv3bmYN2oeWLkbMRJWsRtibsFGBoi0gQkakqnsftyey8XKIY3KI9TWKC8m7nSIjs NU3H7wmRc2rc7oOlaOdQL2IBo45YKH5vcbK0iGjj0t4gfvif1gUgKclwpH/iyXmxh1NC 3xDB8SEk5B/REEVEbmivjGhpoLf7jrnXFq/6HiJ5bOtUsLoETZHjbgsRNPpMjw+B5Eqx Kk721CF0oK4/0A+jq8UCjBsKLFh2/nHmEeOqzZNrY+cZac9cU8hOVCWV/eZ7Z3XeSSHj Tfpkt3e+/dxWeOl1WibUD/ZMPoJo1dGQoeKBly6GsqqSic3dS7+AYCkOAScuEABTaNdU 4mzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690903215; x=1691508015; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=a5ITWAYN9R9rtf6GERIf9S362dBjLzTbE/fVZh0ZgOI=; b=ap9C7hQ6LsMFhIDiCoIrwgeLtnMpNM2HltZrX3mYYV5nAfXylKsvv23ESCkH9YJWA9 FzvXt6JTnr5nXiBQ/rhK80JWS7UC+C7pgTdFiUAdga3MRd106rw32XQjPqi7cSYaFU96 Gk4up0tvlxNe1xVQR5uzGfqTbZQYOnRWNl9WRaHeuocuN5g6vvBVHdB8UcBvplDUpyj0 fqU9VHnmLQCCcz7Yao7ItB6i5TQZS4XK7ZuHPZchRqpEO81XV5M5Xzius06KOMTWWU21 hzG3U5cFd1NK1E45VH1peAFE5O9zOt+kRvdb3cpzmhsLPA4E3ws/xM6dyk3LyM9cxBlE G5VQ== X-Gm-Message-State: ABy/qLYmePOxE5PQGjZfbP0P+TsvQcF14QexJo10ldOGso0EtfZkzG80 yexjEyMRp6wt3vduxMQ9krpZGR/4PeJR7UNE9fvcAVputgHT6/icuMmooArO+k1dsO64tmSa3/w CmHMidllEHgbTdOa58QK93NBQi/de0oIYefoIr7CFg88kp6Z8VR82LS2LoQ3wDuPjCrDvTHc= X-Google-Smtp-Source: APBJJlEnPd5fAD0Aj5PY28l23CVy0dGlj5CAymKDeYm7SNgmyFCz9I6QMeDLMfXxJSbBI+IkBdoRqH8Wa5L+RyznOw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:903:1cb:b0:1bb:cf58:532f with SMTP id e11-20020a17090301cb00b001bbcf58532fmr62253plh.0.1690903215344; Tue, 01 Aug 2023 08:20:15 -0700 (PDT) Date: Tue, 1 Aug 2023 08:19:58 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-3-jingzhangos@google.com> Subject: [PATCH v7 02/10] KVM: arm64: Document KVM_ARM_GET_FEATURE_ID_WRITABLE_MASKS From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add some basic documentation on how to get feature ID register writable masks from userspace. Signed-off-by: Jing Zhang --- Documentation/virt/kvm/api.rst | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index c0ddd3035462..e6cda4169764 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -6068,6 +6068,32 @@ writes to the CNTVCT_EL0 and CNTPCT_EL0 registers using the SET_ONE_REG interface. No error will be returned, but the resulting offset will not be applied. +4.139 KVM_ARM_GET_FEATURE_ID_WRITABLE_MASKS +------------------------------------------- + +:Capability: none +:Architectures: arm64 +:Type: vm ioctl +:Parameters: struct feature_id_writable_masks (out) +:Returns: 0 on success, < 0 on error + + +:: + + #define ARM64_FEATURE_ID_SPACE_SIZE (3 * 8 * 8) + + struct feature_id_writable_masks { + __u64 mask[ARM64_FEATURE_ID_SPACE_SIZE]; + }; + +This ioctl would copy the writable masks for feature ID registers to userspace. +The Feature ID space is defined as the System register space in AArch64 with +op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}. +To get the index in ``mask`` array for a specified feature ID register, use the +macro ``ARM64_FEATURE_ID_SPACE_IDX(op0, op1, crn, crm, op2)``. +This allows the userspace to know upfront whether it can actually tweak the +contents of a feature ID register or not. + 5. The kvm_run structure ======================== From patchwork Tue Aug 1 15:19:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BCA2C001E0 for ; Tue, 1 Aug 2023 15:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234027AbjHAPU1 (ORCPT ); Tue, 1 Aug 2023 11:20:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234174AbjHAPUX (ORCPT ); Tue, 1 Aug 2023 11:20:23 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39DD72112 for ; Tue, 1 Aug 2023 08:20:18 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1bbbf96ebe1so45429105ad.1 for ; Tue, 01 Aug 2023 08:20:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690903217; x=1691508017; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=4m6WXeBLyRHr+QvNXIbI2jFxW3avFe83y+pcJg40hnI=; b=41CSSN+hrqV+uEQcg062xb3BDESzeeaZrpLGmBiFuxwUYBsb39Ajf4JSPo+BnqEgph GrjSldr+fqJbSsULyLROGCqdMwJ6TPcEvBoVqHSLOk+R/n87pDxRhy98pn9Hko3TkWy8 hadEWh7vpkVun5nkli3CBu22HaEfMwDlFX4/lfrHcwM+vpthhZekf6YFpnphlxc8mcOZ /tCUu6i1UfO7pHCYc/bz3S3y5IA4/rdr1KqkE9ugV+EJbcsx5MsA6+N2bJ3L/D9HokGN sFSp0hvkwd7iT7Xnq8UDGuYPwZVC1ofE4o7p8U193EiPY3+mMfFzysmq6ICIwWSgnw6c bQuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690903217; x=1691508017; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=4m6WXeBLyRHr+QvNXIbI2jFxW3avFe83y+pcJg40hnI=; b=Cb85TliiGtW6jOVLVUivomRYNipFamKfoZVyAOgm33VQ8c6aKSknqgxMXzyigsvb+/ tfdbty/2B9vfHSBsZrfWcjEGUT1rJffnSngMitXiEyvTCFXkQQ51jymmk/uSLhpmICl3 xieTFN1xQ5cPD7iXQKmo1JoMO1+qdi+9xKspChb4pfsR3mQGY0x1gf4XWhTNe+nwfAwE R5m8Nl/bZoI/OjxXuIfEkJtA+XGRrIq6VUdmXmSLSLlJpMttFJ2zj7q3vVFWXEq/DE/p LVs5Mf0XDMurRzvvA4vdwhhrmFgN6v67L9vceZwL4hwgqcjLvkCdDubzympxgATG3SlL O3Jg== X-Gm-Message-State: ABy/qLZL9n1QCDzIIcnbpwAwLFJG77JrGl1SZqdyT52Bi9oxDXQUmxUU RbcmEmfihXkAJKq+bKoHvRJTNzijZfE/u3QZXhMVOm7KN/zJr5p82eHfJPrgWDrZJeJDo2x2cQE 3wT5A89lcWKQsdhBr3CtUi0reSVc+rTLTwbVdGBtkBnIDTaUyaNBQAi7gHzSsFqeDewTtM4M= X-Google-Smtp-Source: APBJJlF5pQV//6JpAgPsrrwmu1eJKxYmdCqhfZm9zICtlUCY7L5aEFcjDBXXU7rrEPxZCvZlO/QmM5V89O0TvCqmmw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:902:7588:b0:1bc:1189:189 with SMTP id j8-20020a170902758800b001bc11890189mr53532pll.3.1690903217346; Tue, 01 Aug 2023 08:20:17 -0700 (PDT) Date: Tue, 1 Aug 2023 08:19:59 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-4-jingzhangos@google.com> Subject: [PATCH v7 03/10] KVM: arm64: Use guest ID register values for the sake of emulation From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since KVM now supports per-VM ID registers, use per-VM ID register values for the sake of emulation for DBGDIDR and LORegion. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d9317b640ba5..6eab45ce05d9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -379,7 +379,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + u64 val = IDREG(vcpu->kvm, SYS_ID_AA64MMFR1_EL1); u32 sr = reg_to_encoding(r); if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { @@ -2429,8 +2429,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu, if (p->is_write) { return ignore_write(vcpu, p); } else { - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + u64 dfr = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); + u64 pfr = IDREG(vcpu->kvm, SYS_ID_AA64PFR0_EL1); u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | From patchwork Tue Aug 1 15:20:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B3A8C001E0 for ; Tue, 1 Aug 2023 15:20:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234145AbjHAPUa (ORCPT ); Tue, 1 Aug 2023 11:20:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234204AbjHAPUX (ORCPT ); Tue, 1 Aug 2023 11:20:23 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05C541FD6 for ; Tue, 1 Aug 2023 08:20:20 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id 41be03b00d2f7-5646e695ec1so600074a12.1 for ; Tue, 01 Aug 2023 08:20:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690903219; x=1691508019; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=F/Zz52cr37YYz5qudyTKGXR9rwDQJucFObDOl9aUEDg=; b=pwD5NDzMN0ZaqAhUReAoaSGZuHJujSbu7LQv3w0SSLFlD8hdqiNKVD+AtyhpQV8ij0 6+P3+SCydVe1MmipFZVk5u2szQuAW0uXKIuNsIXW5v9vwsp6ON4LdkrI3bsegIU1gsMU BZ3x7uM5DtevwpLRXdbQAW1GRNdMBW/2vECxNZi3fhHneUHoVPAKsrjiKYbAEx0wQN8R ihWibgBta9V0Y5j40dYn3ATvLyx8XH/6Zl/lcWQnXjM48mGjW72CuRt9U1a2C71hTyEz gcTT3k171nabvSthY0WO13HT+E3NkqRNTCkObhFXpZId2TcshX8zF33z/j68NvS7VQkU F26Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690903219; x=1691508019; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=F/Zz52cr37YYz5qudyTKGXR9rwDQJucFObDOl9aUEDg=; b=L/VpiPeJVsqynj+B0KV6pmKTrbS08eNr+/CZ8OHOcVPJtRAJwXMbrWrlH9EgxtpARJ lAxnZUq9Sg5CGq7F5OErCMtEpl1quJ8XCtuSHxdouZMOqO/1IbiBNZSiOs+RQJtyrP/p Tg7q+yDKLMJJ0J9iIOKZJBdAm44cywTdXLm4n06dpGlFYJ7648ZdhOKP/uA22m4yBx9V GpYqCTBuYZ103mkXkfJKnDrKgKCvaNru0K9ie8QvaDWOlZwcwu0L+Q1bZm4j35myEeOA TspGP6ax5k/wfGgqGNZLHqkzPei31x1W+9JUxM1DpYT2pnZInXWfgUSxTeq9B70GZi3m 2imw== X-Gm-Message-State: ABy/qLZs+pd5GBrytvYHOt+qepIGiK8NjCv77DoBi+YJLrylZICqTQAA P8TanoPz7Vba0+M1MGLKs2jj3j42sHiaBwUAjfscgrPz84NdOnPoG+SSFOhss8p6lvmlBpFbnkn ePmFJ1vcJR9b4Na8Gp/0yWbXaz0+/FgqJMaQw9ntN5Depggk6paCgRifNd4tvIMhhvxsDXt0= X-Google-Smtp-Source: APBJJlEU6slKPFvHDou8lIX/zwI3ydVRH/xm4jxxrY4DkSK02BWVfX+/WC72cAYM7HGpHk9ZmMhsP8T4jRmLclfXjA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a63:794c:0:b0:55c:357a:95e0 with SMTP id u73-20020a63794c000000b0055c357a95e0mr65755pgc.6.1690903219210; Tue, 01 Aug 2023 08:20:19 -0700 (PDT) Date: Tue, 1 Aug 2023 08:20:00 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-5-jingzhangos@google.com> Subject: [PATCH v7 04/10] KVM: arm64: Reject attempts to set invalid debug arch version From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Oliver Upton The debug architecture is mandatory in ARMv8, so KVM should not allow userspace to configure a vCPU with less than that. Of course, this isn't handled elegantly by the generic ID register plumbing, as the respective ID register fields have a nonzero starting value. Add an explicit check for debug versions less than v8 of the architecture. Signed-off-by: Oliver Upton Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 6eab45ce05d9..7fcbc317f100 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1216,8 +1216,14 @@ static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, /* Some features have different safe value type in KVM than host features */ switch (id) { case SYS_ID_AA64DFR0_EL1: - if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT) + switch (kvm_ftr.shift) { + case ID_AA64DFR0_EL1_PMUVer_SHIFT: kvm_ftr.type = FTR_LOWER_SAFE; + break; + case ID_AA64DFR0_EL1_DebugVer_SHIFT: + kvm_ftr.type = FTR_LOWER_SAFE; + break; + } break; case SYS_ID_DFR0_EL1: if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) @@ -1469,14 +1475,22 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return val; } +#define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ +({ \ + u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ + (val) &= ~reg##_##field##_MASK; \ + (val) |= FIELD_PREP(reg##_##field##_MASK, \ + min(__f_val, (u64)reg##_##field##_##limit)); \ + (val); \ +}) + static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); /* Limit debug to ARMv8.0 */ - val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; - val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, IMP); /* * Only initialize the PMU version if the vCPU was configured with one. @@ -1496,6 +1510,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { + u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); /* @@ -1515,6 +1530,13 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; + /* + * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a + * nonzero minimum safe value. + */ + if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } @@ -1536,6 +1558,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, u64 val) { u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); + u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { val &= ~ID_DFR0_EL1_PerfMon_MASK; @@ -1551,6 +1574,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) return -EINVAL; + if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } From patchwork Tue Aug 1 15:20:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87960C0015E for ; Tue, 1 Aug 2023 15:20:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234141AbjHAPU2 (ORCPT ); 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Tue, 01 Aug 2023 08:20:21 -0700 (PDT) Date: Tue, 1 Aug 2023 08:20:01 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-6-jingzhangos@google.com> Subject: [PATCH v7 05/10] KVM: arm64: Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org All valid fields in ID_AA64DFR0_EL1 and ID_DFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7fcbc317f100..2183cd3af472 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2006,7 +2006,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .set_user = set_id_dfr0_el1, .visibility = aa32_id_visibility, .reset = read_sanitised_id_dfr0_el1, - .val = ID_DFR0_EL1_PerfMon_MASK, }, + .val = GENMASK(63, 0), }, ID_HIDDEN(ID_AFR0_EL1), AA32_ID_SANITISED(ID_MMFR0_EL1), AA32_ID_SANITISED(ID_MMFR1_EL1), @@ -2055,7 +2055,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, .reset = read_sanitised_id_aa64dfr0_el1, - .val = ID_AA64DFR0_EL1_PMUVer_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), ID_UNALLOCATED(5,3), From patchwork Tue Aug 1 15:20:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E77E2C001DF for ; Tue, 1 Aug 2023 15:20:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234590AbjHAPUe (ORCPT ); Tue, 1 Aug 2023 11:20:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233797AbjHAPUY (ORCPT ); Tue, 1 Aug 2023 11:20:24 -0400 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C724C1FC0 for ; Tue, 1 Aug 2023 08:20:23 -0700 (PDT) Received: by mail-pf1-x449.google.com with SMTP id d2e1a72fcca58-686bc3f123eso5797653b3a.1 for ; Tue, 01 Aug 2023 08:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690903223; x=1691508023; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=6FyTW1VsL4amGRSIg6wJqneP5gVog8VOaALdC61uAQM=; b=C0ZfPq3efOpnuDcjVLErVLMbvOkEBdQvbm4wQodeYlarW1FXMlMZid16hWYooPNHQg FySrGsafcV+pPcCeKbUiDJXzjc+1S4iffzB2PNPF7P3pEZ3/wA5J+oaXkexLLPEDBUTL 4EbZMcSnQSuQmvmJ6DxOhJX+twsw+aZlzTQC9E+KUFYuYNTgTVQW5bHIrFlpSZD2kjZ5 av1L2nNW80E8q9U4tCNyRXzWHt6OcoUQIt2DkunjdDA1YmF5bZUXBsYOnM4bsG7d7J2p OG0u8sL+1JVv9F0pgL21R5NOmzp+v1VmtztLqjLVQiyX4m33EH5jpctaIwsxb62NEABX /P6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690903223; x=1691508023; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6FyTW1VsL4amGRSIg6wJqneP5gVog8VOaALdC61uAQM=; b=bP160wYAEyEZpFXXveKSAvRQ5mjTRTuIljIfgg0nT6LUQqoe+cGEwqcotjcCMKk8V9 /whh2lPwPJEqfZK9BZtvOUOP+q06+oNnARUUcebfxU47LuNS6CpStVfRYhWyx9tqJR5R sBkinvmRH+snaWMDq+lVLjJHu6jMUnCRqvfqD4Bj7ClvuNhWQDc/dB8HxO7zc+G1X/tg q5iLEKKK7fE4fNnNIaJyZ+wYpeTrby4DMHMequoHTazObydAltYxubpFAx3C1EpK20uB jvKJ/nOEEJNBJNfSbqZ9YeyQqwGGOITh2INdrBb1WZCKnouFoTIssRii4sbGlew4XOf9 Pyyw== X-Gm-Message-State: ABy/qLZSO3RPqnaINQ9JKk8DH57pe504T9o78bCJ+Quazjf05XpF59gG dyGYotD9aZ11jIhUecVqP0McABZJD1hIxvQs2ebftns6s2Ip3F/VvCnMdecYl1yXYl62TIW3sVV oCTzHybCVey8a8h+VRjpSSpAByIgiUh9e7tVTdlpS0FbZCNpaLloZJFn5UYO1VCzMtka3j/s= X-Google-Smtp-Source: APBJJlEL3UUpI4AI77yIqdcAOJwFOq1i8j3nPTDlAWpLoDzAvhrkuZEeOT3azEun/jvOMdCuFYFKd2z4TNq9i2f2Qg== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a05:6a00:80a:b0:682:f33:fa97 with SMTP id m10-20020a056a00080a00b006820f33fa97mr109865pfk.6.1690903222997; Tue, 01 Aug 2023 08:20:22 -0700 (PDT) Date: Tue, 1 Aug 2023 08:20:02 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-7-jingzhangos@google.com> Subject: [PATCH v7 06/10] KVM: arm64: Bump up the default KVM sanitised debug version to v8p8 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Oliver Upton Since ID_AA64DFR0_EL1 and ID_DFR0_EL1 are now writable from userspace, it is safe to bump up the default KVM sanitised debug version to v8p8. Signed-off-by: Oliver Upton Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2183cd3af472..5a886ccb33fa 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1489,8 +1489,7 @@ static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, { u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - /* Limit debug to ARMv8.0 */ - val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); /* * Only initialize the PMU version if the vCPU was configured with one. @@ -1550,6 +1549,8 @@ static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, if (kvm_vcpu_has_pmu(vcpu)) val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); + return val; } From patchwork Tue Aug 1 15:20:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66EB3C0015E for ; Tue, 1 Aug 2023 15:20:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232705AbjHAPUg (ORCPT ); Tue, 1 Aug 2023 11:20:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234009AbjHAPU0 (ORCPT ); Tue, 1 Aug 2023 11:20:26 -0400 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 393A61BFD for ; Tue, 1 Aug 2023 08:20:26 -0700 (PDT) Received: by mail-pg1-x549.google.com with SMTP id 41be03b00d2f7-55bf2bf1cdeso5615391a12.3 for ; Tue, 01 Aug 2023 08:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690903225; x=1691508025; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=f1iJwrUwzrr4LImgyPThesTLhstaE6VPmgVvDL2bXp0=; b=5gd7OaRBrRYmMMIOxe18B8NXMNA1PK1Vvk4zSEoSg9JQcQOfWjTweZXq40eI9c+L1N Pjiy2HD7ipih05DuZXxzwty4Zw4J8+YSCFDSyWhYQhA/eRCTC3NQm/LNPt3/lxoIqT/H yEdDVYoCx3+f6eh5fJ3LuJn0o/Km7f1yoe+NQ9khAuuY1oAei/RTPdKYNFD0OwONNvvb kbXnJ3CRoz/wqDo4SV2g5RL02zHpUNdBV4qR9IumhIJdoJlaT5U/0IAW7sgDaA00TRO2 /GMyXkKsKtW8TNrQmuN0DxVxyEryPcHsKqI8SVdchgkvx3neZaCiwBlrlr7BGR0ut5s5 DjDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690903226; x=1691508026; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=f1iJwrUwzrr4LImgyPThesTLhstaE6VPmgVvDL2bXp0=; b=Rt74/rEXL8unWAalaJuUNIJzH7dIlqkR3bny3SBjxVIlKQ+QxahUt+zYFbx/YSuK+v 8s7YKZ8cWhFQGelLfapFmBrLiAXiKEF+9COYjvpQTGDWjDX/x70EozNXWNGPHPgiqUST iDshLwWF6Wxr6Xdy0XaJ2e+wtZss8HFVosNRpFk8RDeNXRLMKGwdjJrNOrSTuFku/4It F1CV1VG4pwyRtrvFVP2UHeQ21bO6OMtSVhtktxD0HtQ2nZ0JzbNXXUIkGr6pqNLqV4/9 6xpe9o21chxxpU/4tpeLVrkGOkFskrtSGUuSKGCpkoZYUBuk6WUZxDp9EmHhfe2n9/Br fmpg== X-Gm-Message-State: ABy/qLaI9HQSRuyTvxGjvNQ85aRFbASTZH4losD8GQtS8SXbjjGOZGc3 37bgvJC6jisGXMwI6+GF6qsGdcQBYh5BZgEMkMdtWZDQ4jOj6uwQ5V0cU2aSq+23sKLUDP2vwMX anNNSJmhcJ+e74NUT2Cv4b8nlRoRkrgS4VV6EZTb6XuejEasNvCh/j5+98Mx0DTrF5+6P0w4= X-Google-Smtp-Source: APBJJlGHdElaUhiJW+cJ/Bn2gO8XjYZHEO/Zt8CW/zpfo34kurpBDGJ2kXAnPcGIqggba9Ii19yPInx1FB+5h5bOeg== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a63:6dcf:0:b0:563:8dc4:c851 with SMTP id i198-20020a636dcf000000b005638dc4c851mr62368pgc.9.1690903225626; Tue, 01 Aug 2023 08:20:25 -0700 (PDT) Date: Tue, 1 Aug 2023 08:20:03 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-8-jingzhangos@google.com> Subject: [PATCH v7 07/10] KVM: arm64: Enable writable for ID_AA64PFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org All valid fields in ID_AA64PFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 5a886ccb33fa..0a406058abb9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2041,7 +2041,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_reg, .reset = read_sanitised_id_aa64pfr0_el1, - .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, + .val = GENMASK(63, 0), }, ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), From patchwork Tue Aug 1 15:20:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12615C001DF for ; Tue, 1 Aug 2023 15:20:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234470AbjHAPUh (ORCPT ); Tue, 1 Aug 2023 11:20:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233582AbjHAPUa (ORCPT ); Tue, 1 Aug 2023 11:20:30 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B85C81FCB for ; Tue, 1 Aug 2023 08:20:28 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-58456435437so68143317b3.0 for ; Tue, 01 Aug 2023 08:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690903228; x=1691508028; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=qCRHZVqddoTSJorH44HmZhNcqs8I6hBKdRtCxXPKdcc=; b=ePkYS21z2/X3ob7jSeC/nK45+fRe3ruhhAvWk7R/IgpeDZzNSYUvR8Cqquf1co6H0Q vNa9fK7rDmvnx13XMhJt9C8EDK56RtwWoXTWoQjZbsT0MJVbtXHmmrlLKOasGoQPfVwW ASXLd9KcfTKKBkm8dgWy/rOtVT9lvslKAZdEiSgx+L+X3OQdWZgOxzEz0ZBh6JBv+phY FAdIltq5ly5PdXtw8sIx/lL+YOh6CSJ5sa9WagZpdXbKUBFiAEdsTAaX/xa/kNlSZHO0 EoUltfBxFaRkgbFIZu/SUWLX+uqeyW8L4Cr9YO5FwQUM+mIvXJH+X4O6K/ouA+dXTbd8 jYDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690903228; x=1691508028; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qCRHZVqddoTSJorH44HmZhNcqs8I6hBKdRtCxXPKdcc=; b=kWGRZzJQFrV9s4a7NTekhyDudyBXGwjbNUQrLAEzIDcWd07SYvuj0txKLWWws3TW5s p7BE15jEGAYLhRMh92JNa2ep7RZFjo+6BO5vBSChDvA6Y0IDbhcnV6yvJA+FDTsb/XwY VRVRJkm3UVaVWgK5CNl5PTNXo4wEj9mSOwpJ1+mRQ51PkNaQhzJTl/jes/mseJB//l0o ADfy93fvvxz/SVJpRUXh++F1Pe2yYy5yoPWPRvGIpWLHYi+zX3AD3+hyDhg81OvLEQex 4tgCzQ/er4Tcd47ak8gGuVhXkS+F4tPt8Tt/3Ie+kTInZ/ShzLnNTvVH8ITznD+t6KgK fsTA== X-Gm-Message-State: ABy/qLYH6xfFgzRRVpn6oDCGQHSNF2XiCd5MsqCWBxaHglVIjemnphtt k5I4A/ZITn/kjSniCXosOikT0gEdzCcxrWETqsaTXQruTXsdrF+oxqImHaIMI3FzMJXHND3LQ3P mHdHjE41dQe2jPM9j6bFg0MG1euHy3iOTT/Uz5aU/eUWW0SPeAVMDJxm5lLmCRX4JXBMoeMM= X-Google-Smtp-Source: APBJJlEnpgyitr9PUTByZOiYn2bZXCXM8oRbrFOt19UqT5CZCMNf1UqGqdwhB7FXBYLGi3iq9DArG2kfHOXto4DNyA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a25:ab86:0:b0:d0d:a7bc:4040 with SMTP id v6-20020a25ab86000000b00d0da7bc4040mr92863ybi.0.1690903227620; Tue, 01 Aug 2023 08:20:27 -0700 (PDT) Date: Tue, 1 Aug 2023 08:20:04 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-9-jingzhangos@google.com> Subject: [PATCH v7 08/10] KVM: arm64: Refactor helper Macros for idreg desc From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add some helpers to ease the declaration for idreg desc. These Macros will be heavily used for future commits enabling writable for idregs. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 79 ++++++++++++++++----------------------- 1 file changed, 33 insertions(+), 46 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0a406058abb9..9ca23cfec9e5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1844,27 +1844,37 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, * from userspace. */ -/* sys_reg_desc initialiser for known cpufeature ID registers */ -#define ID_SANITISED(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = id_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ +#define ID_DESC(name, _set_user, _visibility, _reset, mask) { \ + SYS_DESC(SYS_##name), \ + .access = access_id_reg, \ + .get_user = get_id_reg, \ + .set_user = _set_user, \ + .visibility = _visibility, \ + .reset = _reset, \ + .val = mask, \ } /* sys_reg_desc initialiser for known cpufeature ID registers */ -#define AA32_ID_SANITISED(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = aa32_id_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ -} +#define _ID_SANITISED(name, _set_user, _reset) \ + ID_DESC(name, _set_user, id_visibility, _reset, 0) +#define ID_SANITISED(name) \ + _ID_SANITISED(name, set_id_reg, kvm_read_sanitised_id_reg) + +#define _ID_SANITISED_W(name, _set_user, _reset) \ + ID_DESC(name, _set_user, id_visibility, _reset, GENMASK(63, 0)) +#define ID_SANITISED_W(name) \ + _ID_SANITISED_W(name, set_id_reg, kvm_read_sanitised_id_reg) + +/* sys_reg_desc initialiser for known cpufeature ID registers */ +#define _AA32_ID_SANITISED(name, _set_user, _reset) \ + ID_DESC(name, _set_user, aa32_id_visibility, _reset, 0) +#define AA32_ID_SANITISED(name) \ + _AA32_ID_SANITISED(name, set_id_reg, kvm_read_sanitised_id_reg) + +#define _AA32_ID_SANITISED_W(name, _set_user, _reset) \ + ID_DESC(name, _set_user, aa32_id_visibility, _reset, GENMASK(63, 0)) +#define AA32_ID_SANITISED_W(name) \ + _AA32_ID_SANITISED_W(name, set_id_reg, kvm_read_sanitised_id_reg) /* * sys_reg_desc initialiser for architecturally unallocated cpufeature ID @@ -1886,15 +1896,8 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, * For now, these are exposed just like unallocated ID regs: they appear * RAZ for the guest. */ -#define ID_HIDDEN(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = raz_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ -} +#define ID_HIDDEN(name) \ + ID_DESC(name, set_id_reg, raz_visibility, kvm_read_sanitised_id_reg, 0) static bool access_sp_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, @@ -2001,13 +2004,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* CRm=1 */ AA32_ID_SANITISED(ID_PFR0_EL1), AA32_ID_SANITISED(ID_PFR1_EL1), - { SYS_DESC(SYS_ID_DFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_dfr0_el1, - .visibility = aa32_id_visibility, - .reset = read_sanitised_id_dfr0_el1, - .val = GENMASK(63, 0), }, + _AA32_ID_SANITISED_W(ID_DFR0_EL1, set_id_dfr0_el1, read_sanitised_id_dfr0_el1), ID_HIDDEN(ID_AFR0_EL1), AA32_ID_SANITISED(ID_MMFR0_EL1), AA32_ID_SANITISED(ID_MMFR1_EL1), @@ -2036,12 +2033,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* AArch64 ID registers */ /* CRm=4 */ - { SYS_DESC(SYS_ID_AA64PFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_reg, - .reset = read_sanitised_id_aa64pfr0_el1, - .val = GENMASK(63, 0), }, + _ID_SANITISED_W(ID_AA64PFR0_EL1, set_id_reg, read_sanitised_id_aa64pfr0_el1), ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), @@ -2051,12 +2043,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(4,7), /* CRm=5 */ - { SYS_DESC(SYS_ID_AA64DFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_aa64dfr0_el1, - .reset = read_sanitised_id_aa64dfr0_el1, - .val = GENMASK(63, 0), }, + _ID_SANITISED_W(ID_AA64DFR0_EL1, set_id_aa64dfr0_el1, read_sanitised_id_aa64dfr0_el1), ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), ID_UNALLOCATED(5,3), From patchwork Tue Aug 1 15:20:05 2023 Content-Type: text/plain; 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Tue, 01 Aug 2023 08:20:29 -0700 (PDT) Date: Tue, 1 Aug 2023 08:20:05 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-10-jingzhangos@google.com> Subject: [PATCH v7 09/10] KVM: arm64: Enable writable for ID_AA64MMFR{0, 1, 2, 3}_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Enable writable from userspace for ID_AA64MMFR{0, 1, 2, 3}_EL1. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 9ca23cfec9e5..67b50a088eac 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1346,9 +1346,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS); break; - case SYS_ID_AA64MMFR2_EL1: - val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; - break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -1581,6 +1578,15 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, return set_id_reg(vcpu, rd, val); } +static u64 read_sanitised_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + + val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; + return val; +} + /* * cpufeature ID register user accessors * @@ -2063,10 +2069,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(6,7), /* CRm=7 */ - ID_SANITISED(ID_AA64MMFR0_EL1), - ID_SANITISED(ID_AA64MMFR1_EL1), - ID_SANITISED(ID_AA64MMFR2_EL1), - ID_SANITISED(ID_AA64MMFR3_EL1), + ID_SANITISED_W(ID_AA64MMFR0_EL1), + ID_SANITISED_W(ID_AA64MMFR1_EL1), + _ID_SANITISED_W(ID_AA64MMFR2_EL1, set_id_reg, read_sanitised_id_aa64mmfr2_el1), + ID_SANITISED_W(ID_AA64MMFR3_EL1), ID_UNALLOCATED(7,4), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6), From patchwork Tue Aug 1 15:20:06 2023 Content-Type: text/plain; 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Tue, 01 Aug 2023 08:20:31 -0700 (PDT) Date: Tue, 1 Aug 2023 08:20:06 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-11-jingzhangos@google.com> Subject: [PATCH v7 10/10] KVM: arm64: selftests: Test for setting ID register from usersapce From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add tests to verify setting ID registers from userapce is handled correctly by KVM. Also add a test case to use ioctl KVM_ARM_GET_FEATURE_ID_WRITABLE_MASKS to get writable masks. Signed-off-by: Jing Zhang --- tools/arch/arm64/include/uapi/asm/kvm.h | 25 +++ tools/include/uapi/linux/kvm.h | 2 + tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/aarch64/set_id_regs.c | 191 ++++++++++++++++++ 4 files changed, 219 insertions(+) create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h index f7ddd73a8c0f..2970c0d792ee 100644 --- a/tools/arch/arm64/include/uapi/asm/kvm.h +++ b/tools/arch/arm64/include/uapi/asm/kvm.h @@ -505,6 +505,31 @@ struct kvm_smccc_filter { #define KVM_HYPERCALL_EXIT_SMC (1U << 0) #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) +/* Get feature ID registers userspace writable mask. */ +/* + * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model + * Feature Register 2"): + * + * "The Feature ID space is defined as the System register space in + * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, + * op2=={0-7}." + * + * This covers all R/O registers that indicate anything useful feature + * wise, including the ID registers. + */ +#define ARM64_FEATURE_ID_SPACE_IDX(op0, op1, crn, crm, op2) \ + ({ \ + __u64 __op1 = (op1) & 3; \ + __op1 -= (__op1 == 3); \ + (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ + }) + +#define ARM64_FEATURE_ID_SPACE_SIZE (3 * 8 * 8) + +struct feature_id_writable_masks { + __u64 mask[ARM64_FEATURE_ID_SPACE_SIZE]; +}; + #endif #endif /* __ARM_KVM_H__ */ diff --git a/tools/include/uapi/linux/kvm.h b/tools/include/uapi/linux/kvm.h index f089ab290978..9abe69cf4001 100644 --- a/tools/include/uapi/linux/kvm.h +++ b/tools/include/uapi/linux/kvm.h @@ -1555,6 +1555,8 @@ struct kvm_s390_ucas_mapping { #define KVM_ARM_MTE_COPY_TAGS _IOR(KVMIO, 0xb4, struct kvm_arm_copy_mte_tags) /* Available with KVM_CAP_COUNTER_OFFSET */ #define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_arm_counter_offset) +#define KVM_ARM_GET_FEATURE_ID_WRITABLE_MASKS \ + _IOR(KVMIO, 0xb6, struct kvm_arm_feature_id_masks) /* ioctl for vm fd */ #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index c692cc86e7da..87ceadc1292a 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -144,6 +144,7 @@ TEST_GEN_PROGS_aarch64 += aarch64/get-reg-list TEST_GEN_PROGS_aarch64 += aarch64/hypercalls TEST_GEN_PROGS_aarch64 += aarch64/page_fault_test TEST_GEN_PROGS_aarch64 += aarch64/psci_test +TEST_GEN_PROGS_aarch64 += aarch64/set_id_regs TEST_GEN_PROGS_aarch64 += aarch64/smccc_filter TEST_GEN_PROGS_aarch64 += aarch64/vcpu_width_config TEST_GEN_PROGS_aarch64 += aarch64/vgic_init diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c new file mode 100644 index 000000000000..9c8f439ac7b3 --- /dev/null +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * set_id_regs - Test for setting ID register from usersapce. + * + * Copyright (c) 2023 Google LLC. + * + * + * Test that KVM supports setting ID registers from userspace and handles the + * feature set correctly. + */ + +#include +#include "kvm_util.h" +#include "processor.h" +#include "test_util.h" +#include + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffsl(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffsl(_mask) - 1)) & (_mask)) + +struct reg_feature { + uint64_t reg; + uint64_t ftr_mask; +}; + +static void guest_code(void) +{ + for (;;) + GUEST_SYNC(0); +} + +static struct reg_feature lower_safe_reg_ftrs[] = { + { KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), ARM64_FEATURE_MASK(ID_AA64PFR0_EL3) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR0_FGT) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR1_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR1_PAN) }, + { KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR2_EL1), ARM64_FEATURE_MASK(ID_AA64MMFR2_FWB) }, +}; + +static void test_user_set_lower_safe(struct kvm_vcpu *vcpu) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lower_safe_reg_ftrs); i++) { + struct reg_feature *reg_ftr = lower_safe_reg_ftrs + i; + uint64_t val, new_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + + /* Set a safe value for the feature */ + if (ftr > 0) + ftr--; + + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + + vcpu_set_reg(vcpu, reg_ftr->reg, val); + vcpu_get_reg(vcpu, reg_ftr->reg, &new_val); + ASSERT_EQ(new_val, val); + } +} + +static void test_user_set_fail(struct kvm_vcpu *vcpu) +{ + int i, r; + + for (i = 0; i < ARRAY_SIZE(lower_safe_reg_ftrs); i++) { + struct reg_feature *reg_ftr = lower_safe_reg_ftrs + i; + uint64_t val, old_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + + /* Set a invalid value (too big) for the feature */ + if (ftr >= GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0)) + continue; + ftr++; + + old_val = val; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + } +} + +static struct reg_feature exact_reg_ftrs[] = { + /* Items will be added when there is appropriate field of type + * FTR_EXACT enabled writing from userspace later. + */ +}; + +static void test_user_set_exact(struct kvm_vcpu *vcpu) +{ + int i, r; + + for (i = 0; i < ARRAY_SIZE(exact_reg_ftrs); i++) { + struct reg_feature *reg_ftr = exact_reg_ftrs + i; + uint64_t val, old_val, ftr; + + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ftr = field_get(reg_ftr->ftr_mask, val); + old_val = val; + + /* Exact match */ + vcpu_set_reg(vcpu, reg_ftr->reg, val); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + + /* Smaller value */ + if (ftr > 0) { + ftr--; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + ftr++; + } + + /* Bigger value */ + ftr++; + val &= ~reg_ftr->ftr_mask; + val |= field_prep(reg_ftr->ftr_mask, ftr); + r = __vcpu_set_reg(vcpu, reg_ftr->reg, val); + TEST_ASSERT(r < 0 && errno == EINVAL, + "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno); + vcpu_get_reg(vcpu, reg_ftr->reg, &val); + ASSERT_EQ(val, old_val); + } +} + +static uint32_t writable_regs[] = { + SYS_ID_DFR0_EL1, + SYS_ID_AA64DFR0_EL1, + SYS_ID_AA64PFR0_EL1, + SYS_ID_AA64MMFR0_EL1, + SYS_ID_AA64MMFR1_EL1, + SYS_ID_AA64MMFR2_EL1, +}; + +void test_user_get_writable_masks(struct kvm_vm *vm) +{ + struct feature_id_writable_masks masks; + + vm_ioctl(vm, KVM_ARM_GET_FEATURE_ID_WRITABLE_MASKS, &masks); + + for (int i = 0; i < ARRAY_SIZE(writable_regs); i++) { + uint32_t reg = writable_regs[i]; + int idx = ARM64_FEATURE_ID_SPACE_IDX(sys_reg_Op0(reg), + sys_reg_Op1(reg), sys_reg_CRn(reg), + sys_reg_CRm(reg), sys_reg_Op2(reg)); + + ASSERT_EQ(masks.mask[idx], GENMASK_ULL(63, 0)); + } +} + +int main(void) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + + ksft_print_header(); + ksft_set_plan(4); + + test_user_get_writable_masks(vm); + ksft_test_result_pass("test_user_get_writable_masks\n"); + + test_user_set_exact(vcpu); + ksft_test_result_pass("test_user_set_exact\n"); + + test_user_set_fail(vcpu); + ksft_test_result_pass("test_user_set_fail\n"); + + test_user_set_lower_safe(vcpu); + ksft_test_result_pass("test_user_set_lower_safe\n"); + + kvm_vm_free(vm); + + ksft_finished(); +}