From patchwork Thu Aug 3 10:57:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 13339716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06FD3C41513 for ; Thu, 3 Aug 2023 10:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235463AbjHCK6c (ORCPT ); Thu, 3 Aug 2023 06:58:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235100AbjHCK6Y (ORCPT ); Thu, 3 Aug 2023 06:58:24 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D708230E4; Thu, 3 Aug 2023 03:58:23 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 373ASJ6l001878; Thu, 3 Aug 2023 10:58:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=XzLUvkAz8qwD4XnFIccvceRCsJ6MDLtK6pIhVjI0oqQ=; b=Aonkotw0GAUOOW1qb9D2rd7sbFdieZSRbglqjJnkrLR2oWFdNk6iW1y3a00WsNmywNkr LB3zh240SjKMTCiuXLtgwbylmgodtpJytjumZUvuEBBf9Jkwrs03HpvVBNv9nW7fP1bj bUy+WprtrVN5H4QjPlwmtg8/X4rgC6D+Q1YiZgVb2pGXOoQjrWhLhIaWznjQtd4IOFSf wiPFiIPcJh12RsLksV/5OUz8Ey+kaQ3lpm+aCjhxjCIc6n/2Y4rAJOV7uXlfpJ5LRBDw ci1uhc2iYxi1QYNyhk5CpplIpL3wm+E120Q6OK0geeNgGRy+2K5NzlAHzNypd/1w/iPh WA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s85fxrmyy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 03 Aug 2023 10:58:19 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 373AwJpo026588 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 3 Aug 2023 10:58:19 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 3 Aug 2023 03:58:13 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , Dmitry Baryshkov , Melody Olvera , , , , , Jagadeesh Kona , "Ajit Pandey" , Satya Priya Kakitapalli , Rob Herring Subject: [PATCH V5 1/8] dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs Date: Thu, 3 Aug 2023 16:27:34 +0530 Message-ID: <20230803105741.2292309-2-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803105741.2292309-1-quic_imrashai@quicinc.com> References: <20230803105741.2292309-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Sd9HzNe-OcHz5q2gnJ_lt-Hj1M69yg98 X-Proofpoint-ORIG-GUID: Sd9HzNe-OcHz5q2gnJ_lt-Hj1M69yg98 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-03_09,2023-08-03_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 mlxscore=0 clxscore=1011 priorityscore=1501 mlxlogscore=999 bulkscore=0 phishscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308030098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by: Imran Shaik Acked-by: Rob Herring --- Changes since v4: - Updated the commit text Changes since v3: - None Changes since v2: - None Changes since v1: - Removed the v2 variant compatible string changes - Updated the maintainers list Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++- include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml index 767a9d03aa32..d712b1a87e25 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 maintainers: - - Melody Olvera + - Taniya Das + - Imran Shaik description: | Qualcomm global clock control module which supports the clocks, resets and diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h index ddbc6b825e80..2fd36cbfddbb 100644 --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ /* - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H @@ -138,6 +138,8 @@ #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 #define GCC_PCIE_0_PIPE_CLK_SRC 129 #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 +#define GCC_GPLL1_OUT_EVEN 131 +#define GCC_DDRSS_ECPRI_GSI_CLK 132 /* GCC resets */ #define GCC_ECPRI_CC_BCR 0 From patchwork Thu Aug 3 10:57:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 13339717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19E1FC41513 for ; Thu, 3 Aug 2023 10:58:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235512AbjHCK6y (ORCPT ); Thu, 3 Aug 2023 06:58:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235466AbjHCK6p (ORCPT ); Thu, 3 Aug 2023 06:58:45 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26E013A95; Thu, 3 Aug 2023 03:58:31 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 373AkTSm024073; Thu, 3 Aug 2023 10:58:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=H0hyPgFsN3rrtEP0ALoiF8TOZT704TBpnLiHmk0qdCs=; b=MrD63mbz6mONvfzzMtmbQaFEuficTykNHqNMniHMf7IRc9M+1A9e//s6hdriGRPud6b5 sJhqwb6plAEEe0nJsPQnPUZ9L4F7ea+8crZFvVYjdErkE8nXG3YTFsYiN1Yrw4jUZ4ru InMNcu0L9mgbK6wEVrbtQw7ifofSOlrBlnDF9hgl0do+vtKhm+GcLmpwaY6g1D5//wZB pGFI6OJMsdPEXOYytheOkqkiu0erOsMURcw3gLuACWdg5azh3WPf3VA1HeuxBQt41iYM XUyl2z1bN1HIQOwIpbLP0gf+eA5ufoH5nMqiuqYobqpIM7lHqCTvN6FCS8219aZ81ULf OQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s87jhge13-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 03 Aug 2023 10:58:25 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 373AwOsQ017827 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 3 Aug 2023 10:58:24 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 3 Aug 2023 03:58:19 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , Dmitry Baryshkov , Melody Olvera , , , , , Jagadeesh Kona , "Ajit Pandey" , Satya Priya Kakitapalli Subject: [PATCH V5 2/8] clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling Date: Thu, 3 Aug 2023 16:27:35 +0530 Message-ID: <20230803105741.2292309-3-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803105741.2292309-1-quic_imrashai@quicinc.com> References: <20230803105741.2292309-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 3t9bPkklLMwrv0NOFzBXDZDdZyzV5SuP X-Proofpoint-ORIG-GUID: 3t9bPkklLMwrv0NOFzBXDZDdZyzV5SuP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-03_09,2023-08-03_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308030098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops implementation to let the clock framework automatically park the clock at XO when the clock is switched off and restore the parent when the clock is switched on. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - None Changes since v3: - None Changes since v2: - Updated the commit text Changes since v1: - Newly added drivers/clk/qcom/gcc-qdu1000.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 328b306297ef..9fa0616952d9 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -371,16 +371,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { { .index = DT_TCXO_IDX }, }; -static const struct parent_map gcc_parent_map_7[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_7[] = { - { .index = DT_PCIE_0_PIPE_CLK_IDX }, - { .index = DT_TCXO_IDX }, -}; - static const struct parent_map gcc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -440,16 +430,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x9d064, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_7, - .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_0_PIPE_CLK_IDX, + }, + .num_parents = 1, .ops = &clk_regmap_phy_mux_ops, }, }, From patchwork Thu Aug 3 10:57:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 13339718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22719C00528 for ; Thu, 3 Aug 2023 10:59:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235536AbjHCK7A (ORCPT ); Thu, 3 Aug 2023 06:59:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235457AbjHCK6t (ORCPT ); Thu, 3 Aug 2023 06:58:49 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7496D30F1; Thu, 3 Aug 2023 03:58:35 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3736nw5L030213; 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Thu, 3 Aug 2023 10:58:30 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 3 Aug 2023 03:58:24 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , Dmitry Baryshkov , Melody Olvera , , , , , Jagadeesh Kona , "Ajit Pandey" , Satya Priya Kakitapalli Subject: [PATCH V5 3/8] clk: qcom: gcc-qdu1000: Fix clkref clocks handling Date: Thu, 3 Aug 2023 16:27:36 +0530 Message-ID: <20230803105741.2292309-4-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803105741.2292309-1-quic_imrashai@quicinc.com> References: <20230803105741.2292309-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: KajWLGGAivijm5xfZVnY9oWZTyEGiETS X-Proofpoint-ORIG-GUID: KajWLGGAivijm5xfZVnY9oWZTyEGiETS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-03_09,2023-08-03_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 priorityscore=1501 adultscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308030098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's status bit is not inverted in the latest hardware version of QDU1000 and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Update the commit text Changes since v3: - None Changes since v2: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 9fa0616952d9..6a6e0f55516a 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1448,14 +1448,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { static struct clk_branch gcc_pcie_0_clkref_en = { .halt_reg = 0x9c004, - .halt_bit = 31, - .halt_check = BRANCH_HALT_ENABLE, + .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9c004, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_clkref_en", - .ops = &clk_branch_ops, + .ops = &clk_branch2_ops, }, }, }; @@ -2275,14 +2274,13 @@ static struct clk_branch gcc_tsc_etu_clk = { static struct clk_branch gcc_usb2_clkref_en = { .halt_reg = 0x9c008, - .halt_bit = 31, - .halt_check = BRANCH_HALT_ENABLE, + .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9c008, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_usb2_clkref_en", - .ops = &clk_branch_ops, + .ops = &clk_branch2_ops, }, }, }; From patchwork Thu Aug 3 10:57:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 13339719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96353C41513 for ; Thu, 3 Aug 2023 10:59:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235505AbjHCK7R (ORCPT ); Thu, 3 Aug 2023 06:59:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235503AbjHCK6x (ORCPT ); Thu, 3 Aug 2023 06:58:53 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDB6A3C3E; Thu, 3 Aug 2023 03:58:40 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 373AH7rm015672; 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Thu, 3 Aug 2023 10:58:35 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 3 Aug 2023 03:58:30 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , Dmitry Baryshkov , Melody Olvera , , , , , Jagadeesh Kona , "Ajit Pandey" , Satya Priya Kakitapalli Subject: [PATCH V5 4/8] clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock Date: Thu, 3 Aug 2023 16:27:37 +0530 Message-ID: <20230803105741.2292309-5-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803105741.2292309-1-quic_imrashai@quicinc.com> References: <20230803105741.2292309-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PYq9lq9O5uXTSqLEFDK3_cZnOUk847A2 X-Proofpoint-GUID: PYq9lq9O5uXTSqLEFDK3_cZnOUk847A2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-03_09,2023-08-03_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308030098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org gcc_gpll1_out_even clock is referenced as a parent, but not registered with the clock framework. Hence add support to register the same. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Split the gcc_ddrss_ecpri_gsi_clk clock changes - Update the commit text Changes since v3: - None Changes since v2: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 6a6e0f55516a..97fd1947637a 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -2522,6 +2522,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = { From patchwork Thu Aug 3 10:57:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 13339720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A244DC00528 for ; Thu, 3 Aug 2023 10:59:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235537AbjHCK73 (ORCPT ); Thu, 3 Aug 2023 06:59:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235538AbjHCK7B (ORCPT ); Thu, 3 Aug 2023 06:59:01 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC7EB35A6; Thu, 3 Aug 2023 03:58:46 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3739rxYJ018463; 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Thu, 3 Aug 2023 10:58:41 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 3 Aug 2023 03:58:35 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , Dmitry Baryshkov , Melody Olvera , , , , , Jagadeesh Kona , "Ajit Pandey" , Satya Priya Kakitapalli Subject: [PATCH V5 5/8] clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support Date: Thu, 3 Aug 2023 16:27:38 +0530 Message-ID: <20230803105741.2292309-6-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803105741.2292309-1-quic_imrashai@quicinc.com> References: <20230803105741.2292309-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MYL_YMJT-fcAlmc425GK1uP33GKpYaSr X-Proofpoint-ORIG-GUID: MYL_YMJT-fcAlmc425GK1uP33GKpYaSr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-03_09,2023-08-03_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308030098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware version of QDU1000 and QRU100 SoCs. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Split the patch - Newly added drivers/clk/qcom/gcc-qdu1000.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 97fd1947637a..5bf62f04cf12 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1132,6 +1132,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { }, }; +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { + .halt_reg = 0x54298, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x54298, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x54298, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ddrss_ecpri_gsi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_ecpri_ahb_clk = { .halt_reg = 0x3a008, .halt_check = BRANCH_HALT_VOTED, @@ -2523,6 +2543,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = { From patchwork Thu Aug 3 10:57:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 13339721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EEDAC00528 for ; Thu, 3 Aug 2023 10:59:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234484AbjHCK7f (ORCPT ); Thu, 3 Aug 2023 06:59:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235493AbjHCK7I (ORCPT ); Thu, 3 Aug 2023 06:59:08 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75205422A; 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Thu, 03 Aug 2023 10:58:47 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 373Awko3010055 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 3 Aug 2023 10:58:47 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 3 Aug 2023 03:58:41 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , Dmitry Baryshkov , Melody Olvera , , , , , Jagadeesh Kona , "Ajit Pandey" , Satya Priya Kakitapalli Subject: [PATCH V5 6/8] clk: qcom: gcc-qdu1000: Add support for GDSCs Date: Thu, 3 Aug 2023 16:27:39 +0530 Message-ID: <20230803105741.2292309-7-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803105741.2292309-1-quic_imrashai@quicinc.com> References: <20230803105741.2292309-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LM-akJmkrX8wf9CGPTvziB431ML9Oujf X-Proofpoint-ORIG-GUID: LM-akJmkrX8wf9CGPTvziB431ML9Oujf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-03_09,2023-08-03_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 suspectscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308030098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the GDSCs support for QDU1000 and QRU1000 SoCs. Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - None Changes since v3: - None Changes since v2: - None Changes since v1: - Newly added drivers/clk/qcom/gcc-qdu1000.c | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 5bf62f04cf12..fe1d0e8946a7 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -18,6 +18,7 @@ #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" #include "clk-regmap-phy-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -2410,6 +2411,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { }, }; +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x9d004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_0_phy_gdsc = { + .gdscr = 0x7c004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_pcie_0_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc = { + .gdscr = 0x49004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, @@ -2546,6 +2580,12 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; +static struct gdsc *gcc_qdu1000_gdscs[] = { + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, +}; + static const struct qcom_reset_map gcc_qdu1000_resets[] = { [GCC_ECPRI_CC_BCR] = { 0x3e000 }, [GCC_ECPRI_SS_BCR] = { 0x3a000 }, @@ -2607,6 +2647,8 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = { .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), .resets = gcc_qdu1000_resets, .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), + .gdscs = gcc_qdu1000_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs), }; static const struct of_device_id gcc_qdu1000_match_table[] = { From patchwork Thu Aug 3 10:57:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 13339722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6715FC04A94 for ; Thu, 3 Aug 2023 10:59:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235500AbjHCK7u (ORCPT ); Thu, 3 Aug 2023 06:59:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235502AbjHCK7Q (ORCPT ); Thu, 3 Aug 2023 06:59:16 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 810E43A95; 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Thu, 03 Aug 2023 10:58:53 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 373Awqbr010107 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 3 Aug 2023 10:58:52 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 3 Aug 2023 03:58:47 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , Dmitry Baryshkov , Melody Olvera , , , , , Jagadeesh Kona , "Ajit Pandey" , Satya Priya Kakitapalli Subject: [PATCH V5 7/8] clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops Date: Thu, 3 Aug 2023 16:27:40 +0530 Message-ID: <20230803105741.2292309-8-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803105741.2292309-1-quic_imrashai@quicinc.com> References: <20230803105741.2292309-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: d5Pqnaae04j4FHcRfUTQ0RmW911Tx0SK X-Proofpoint-ORIG-GUID: d5Pqnaae04j4FHcRfUTQ0RmW911Tx0SK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-03_09,2023-08-03_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 mlxscore=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308030098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update the GCC SDCC clock RCG ops to clk_rcg2_floor_ops to avoid the overclocking issues on QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Updated the commit text Changes since v3: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index fe1d0e8946a7..82391918c93e 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -904,7 +904,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { .name = "gcc_sdcc5_apps_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -923,7 +923,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { .name = "gcc_sdcc5_ice_core_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; From patchwork Thu Aug 3 10:57:41 2023 Content-Type: text/plain; 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Thu, 3 Aug 2023 10:58:58 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 3 Aug 2023 03:58:52 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , Dmitry Baryshkov , Melody Olvera , , , , , Jagadeesh Kona , "Ajit Pandey" , Satya Priya Kakitapalli Subject: [PATCH V5 8/8] clk: qcom: gcc-qdu1000: Update the RCGs ops Date: Thu, 3 Aug 2023 16:27:41 +0530 Message-ID: <20230803105741.2292309-9-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230803105741.2292309-1-quic_imrashai@quicinc.com> References: <20230803105741.2292309-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4-UhPPWSMfGdf0zf_zINMrBkU_iEwjO8 X-Proofpoint-GUID: 4-UhPPWSMfGdf0zf_zINMrBkU_iEwjO8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-03_09,2023-08-03_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308030098 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The clock RCGs are required to be parked at safe clock source(XO) during disable as per the hardware expectation and clk_rcg2_shared_ops are the closest implementation for the same. Hence update the clock RCG ops to clk_rcg2_shared_ops. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- Changes since v4: - Updated the commit text Changes since v3: - Split the patch as per the review comments - Newly added drivers/clk/qcom/gcc-qdu1000.c | 58 +++++++++++++++++----------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 82391918c93e..9f42d2601464 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -476,7 +476,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { .name = "gcc_aggre_noc_ecpri_dma_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -496,7 +496,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { .name = "gcc_aggre_noc_ecpri_gsi_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -515,7 +515,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -529,7 +529,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -543,7 +543,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -562,7 +562,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -582,7 +582,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { .name = "gcc_pcie_0_phy_rchng_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -601,7 +601,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -623,7 +623,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { @@ -639,7 +639,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { @@ -655,7 +655,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { @@ -671,7 +671,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { @@ -687,7 +687,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { @@ -708,7 +708,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { @@ -724,7 +724,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { @@ -740,7 +740,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { @@ -756,7 +756,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { @@ -772,7 +772,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { @@ -788,7 +788,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { @@ -804,7 +804,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { @@ -820,7 +820,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { @@ -836,7 +836,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { @@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { .name = "gcc_qupv3_wrap1_s6_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { @@ -868,7 +868,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { .name = "gcc_qupv3_wrap1_s7_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { @@ -937,7 +937,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { .name = "gcc_sm_bus_xo_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -956,7 +956,7 @@ static struct clk_rcg2 gcc_tsc_clk_src = { .name = "gcc_tsc_clk_src", .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -976,7 +976,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -990,7 +990,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1004,7 +1004,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, };