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While this bug doesn't seem to cause issue in newer kernels with jevents.py script, it prevents building older perf tools with the backported patch. Fixes: a9650b7f6fc0 ("perf vendor events arm64: Add AmpereOne core PMU events") Reported-by: Dave Kleikamp Closes: https://lore.kernel.org/all/76bb2e47-ce44-76ae-838e-53279047084d@oracle.com/ Signed-off-by: Ilkka Koskinen Reviewed-by: John Garry Reviewed-by: Ian Rogers --- tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json | 3 --- 1 file changed, 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json index fc0633054211..7a2b7b200f14 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json @@ -92,9 +92,6 @@ { "ArchStdEvent": "L1D_CACHE_LMISS_RD" }, - { - "ArchStdEvent": "L1D_CACHE_LMISS" - }, { "ArchStdEvent": "L1I_CACHE_LMISS" }, From patchwork Thu Aug 3 21:13:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilkka Koskinen X-Patchwork-Id: 13340840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C262C001DB for ; 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The follow up metrics patch will include correct way to calculate the impacted events. Signed-off-by: Ilkka Koskinen Reviewed-by: John Garry --- .../arch/arm64/ampere/ampereone/pipeline.json | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/pipeline.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/pipeline.json index f9fae15f7555..711028377f3e 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/pipeline.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/pipeline.json @@ -1,18 +1,24 @@ [ { - "ArchStdEvent": "STALL_FRONTEND" + "ArchStdEvent": "STALL_FRONTEND", + "Errata": "Errata AC03_CPU_29", + "BriefDescription": "Impacted by errata, use metrics instead -" }, { "ArchStdEvent": "STALL_BACKEND" }, { - "ArchStdEvent": "STALL" + "ArchStdEvent": "STALL", + "Errata": "Errata AC03_CPU_29", + "BriefDescription": "Impacted by errata, use metrics instead -" }, { "ArchStdEvent": "STALL_SLOT_BACKEND" }, { - "ArchStdEvent": "STALL_SLOT_FRONTEND" + "ArchStdEvent": "STALL_SLOT_FRONTEND", + "Errata": "Errata AC03_CPU_29", + "BriefDescription": "Impacted by errata, use metrics instead -" }, { "ArchStdEvent": "STALL_SLOT" From patchwork Thu Aug 3 21:13:30 2023 Content-Type: text/plain; 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The metrics also work around the issue related to some of the events. Signed-off-by: Ilkka Koskinen --- .../arch/arm64/ampere/ampereone/metrics.json | 362 ++++++++++++++++++ 1 file changed, 362 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/ampere/ampereone/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/metrics.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/metrics.json new file mode 100644 index 000000000000..1e7e8901a445 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/metrics.json @@ -0,0 +1,362 @@ +[ + { + "MetricExpr": "BR_MIS_PRED / BR_PRED", + "BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch", + "MetricGroup": "Branch Prediction", + "MetricName": "Misprediction" + }, + { + "MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED", + "BriefDescription": "Branch predictor misprediction rate", + "MetricGroup": "Branch Prediction", + "MetricName": "Misprediction (retired)" + }, + { + "MetricExpr": "BUS_ACCESS / ( BUS_CYCLES * 1)", + "BriefDescription": "Core-to-uncore bus utilization", + "MetricGroup": "Bus", + "MetricName": "Bus utilization" + }, + { + "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", + "BriefDescription": "L1D cache miss rate", + "MetricGroup": "Cache", + "MetricName": "L1D cache miss" + }, + { + "MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD", + "BriefDescription": "L1D cache read miss rate", + "MetricGroup": "Cache", + "MetricName": "L1D cache read miss" + }, + { + "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", + "BriefDescription": "L1I cache miss rate", + "MetricGroup": "Cache", + "MetricName": "L1I cache miss" + }, + { + "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE", + "BriefDescription": "L2 cache miss rate", + "MetricGroup": "Cache", + "MetricName": "L2 cache miss" + }, + { + "MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE", + "BriefDescription": "L1I cache read miss rate", + "MetricGroup": "Cache", + "MetricName": "L1I cache read miss" + }, + { + "MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD", + "BriefDescription": "L2 cache read miss rate", + "MetricGroup": "Cache", + "MetricName": "L2 cache read miss" + }, + { + "MetricExpr": "(L1D_CACHE_LMISS_RD * 1000) / INST_RETIRED", + "BriefDescription": "Misses per thousand instructions (data)", + "MetricGroup": "Cache", + "MetricName": "MPKI data" + }, + { + "MetricExpr": "(L1I_CACHE_LMISS * 1000) / INST_RETIRED", + "BriefDescription": "Misses per thousand instructions (instruction)", + "MetricGroup": "Cache", + "MetricName": "MPKI instruction" + }, + { + "MetricExpr": "ASE_SPEC / OP_SPEC", + "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) operations", + "MetricGroup": "Instruction", + "MetricName": "ASE mix" + }, + { + "MetricExpr": "CRYPTO_SPEC / OP_SPEC", + "BriefDescription": "Proportion of crypto data processing operations", + "MetricGroup": "Instruction", + "MetricName": "Crypto mix" + }, + { + "MetricExpr": "VFP_SPEC / (duration_time *1000000000)", + "BriefDescription": "Giga-floating point operations per second", + "MetricGroup": "Instruction", + "MetricName": "GFLOPS_ISSUED" + }, + { + "MetricExpr": "DP_SPEC / OP_SPEC", + "BriefDescription": "Proportion of integer data processing operations", + "MetricGroup": "Instruction", + "MetricName": "Integer mix" + }, + { + "MetricExpr": "INST_RETIRED / CPU_CYCLES", + "BriefDescription": "Instructions per cycle", + "MetricGroup": "Instruction", + "MetricName": "IPC" + }, + { + "MetricExpr": "LD_SPEC / OP_SPEC", + "BriefDescription": "Proportion of load operations", + "MetricGroup": "Instruction", + "MetricName": "Load mix" + }, + { + "MetricExpr": "LDST_SPEC/ OP_SPEC", + "BriefDescription": "Proportion of load & store operations", + "MetricGroup": "Instruction", + "MetricName": "Load-store mix" + }, + { + "MetricExpr": "INST_RETIRED / (duration_time * 1000000)", + "BriefDescription": "Millions of instructions per second", + "MetricGroup": "Instruction", + "MetricName": "MIPS_RETIRED" + }, + { + "MetricExpr": "INST_SPEC / (duration_time * 1000000)", + "BriefDescription": "Millions of instructions per second", + "MetricGroup": "Instruction", + "MetricName": "MIPS_UTILIZATION" + }, + { + "MetricExpr": "PC_WRITE_SPEC / OP_SPEC", + "BriefDescription": "Proportion of software change of PC operations", + "MetricGroup": "Instruction", + "MetricName": "PC write mix" + }, + { + "MetricExpr": "ST_SPEC / OP_SPEC", + "BriefDescription": "Proportion of store operations", + "MetricGroup": "Instruction", + "MetricName": "Store mix" + }, + { + "MetricExpr": "VFP_SPEC / OP_SPEC", + "BriefDescription": "Proportion of FP operations", + "MetricGroup": "Instruction", + "MetricName": "VFP mix" + }, + { + "MetricExpr": "1 - (OP_RETIRED/ (CPU_CYCLES * 4))", + "BriefDescription": "Proportion of slots lost", + "MetricGroup": "Speculation / TDA", + "MetricName": "CPU lost" + }, + { + "MetricExpr": "OP_RETIRED/ (CPU_CYCLES * 4)", + "BriefDescription": "Proportion of slots retiring", + "MetricGroup": "Speculation / TDA", + "MetricName": "CPU utilization" + }, + { + "MetricExpr": "OP_RETIRED - OP_SPEC", + "BriefDescription": "Operations lost due to misspeculation", + "MetricGroup": "Speculation / TDA", + "MetricName": "Operations lost" + }, + { + "MetricExpr": "1 - (OP_RETIRED / OP_SPEC)", + "BriefDescription": "Proportion of operations lost", + "MetricGroup": "Speculation / TDA", + "MetricName": "Operations lost (ratio)" + }, + { + "MetricExpr": "OP_RETIRED / OP_SPEC", + "BriefDescription": "Proportion of operations retired", + "MetricGroup": "Speculation / TDA", + "MetricName": "Operations retired" + }, + { + "MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES", + "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss", + "MetricGroup": "Stall", + "MetricName": "Stall backend cache cycles" + }, + { + "MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES", + "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full", + "MetricGroup": "Stall", + "MetricName": "Stall backend resource cycles" + }, + { + "MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES", + "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss", + "MetricGroup": "Stall", + "MetricName": "Stall backend tlb cycles" + }, + { + "MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES", + "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss", + "MetricGroup": "Stall", + "MetricName": "Stall frontend cache cycles" + }, + { + "MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES", + "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss", + "MetricGroup": "Stall", + "MetricName": "Stall frontend tlb cycles" + }, + { + "MetricExpr": "DTLB_WALK / L1D_TLB", + "BriefDescription": "D-side walk per d-side translation request", + "MetricGroup": "TLB", + "MetricName": "DTLB walks" + }, + { + "MetricExpr": "ITLB_WALK / L1I_TLB", + "BriefDescription": "I-side walk per i-side translation request", + "MetricGroup": "TLB", + "MetricName": "ITLB walks" + }, + { + "MetricExpr": "STALL_SLOT_BACKEND / (CPU_CYCLES * 4)", + "BriefDescription": "Fraction of slots backend bound", + "MetricGroup": "TopDownL1", + "MetricName": "backend" + }, + { + "MetricExpr": "1 - (retiring + lost + backend)", + "BriefDescription": "Fraction of slots frontend bound", + "MetricGroup": "TopDownL1", + "MetricName": "frontend" + }, + { + "MetricExpr": "((OP_SPEC - OP_RETIRED) / (CPU_CYCLES * 4))", + "BriefDescription": "Fraction of slots lost due to misspeculation", + "MetricGroup": "TopDownL1", + "MetricName": "lost" + }, + { + "MetricExpr": "(OP_RETIRED / (CPU_CYCLES * 4))", + "BriefDescription": "Fraction of slots retiring, useful work", + "MetricGroup": "TopDownL1", + "MetricName": "retiring" + }, + { + "MetricExpr": "backend - backend_memory", + "BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues", + "MetricGroup": "TopDownL2", + "MetricName": "backend_core" + }, + { + "MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE + STALL_BACKEND_MEM) / CPU_CYCLES ", + "BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)", + "MetricGroup": "TopDownL2", + "MetricName": "backend_memory" + }, + { + "MetricExpr": " (BR_MIS_PRED_RETIRED / GPC_FLUSH) * lost", + "BriefDescription": "Fraction of slots lost due to branch misprediciton", + "MetricGroup": "TopDownL2", + "MetricName": "branch_mispredict" + }, + { + "MetricExpr": "frontend - frontend_latency", + "BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)", + "MetricGroup": "TopDownL2", + "MetricName": "frontend_bandwidth" + }, + { + "MetricExpr": "(STALL_FRONTEND - ((STALL_SLOT_FRONTEND - (frontend * CPU_CYCLES * 4)) / 4)) / CPU_CYCLES", + "BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch", + "MetricGroup": "TopDownL2", + "MetricName": "frontend_latency" + }, + { + "MetricExpr": "lost - branch_mispredict", + "BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation", + "MetricGroup": "TopDownL2", + "MetricName": "other_clears" + }, + { + "MetricExpr": "(IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6)", + "BriefDescription": "Fraction of execute slots utilized", + "MetricGroup": "TopDownL2", + "MetricName": "pipe_utilization" + }, + { + "MetricExpr": "STALL_BACKEND_MEM / CPU_CYCLES", + "BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss", + "MetricGroup": "TopDownL3", + "MetricName": "d_cache_l2_miss" + }, + { + "MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES", + "BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss", + "MetricGroup": "TopDownL3", + "MetricName": "d_cache_miss" + }, + { + "MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES", + "BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss", + "MetricGroup": "TopDownL3", + "MetricName": "d_tlb_miss" + }, + { + "MetricExpr": "FSU_ISSUED / (CPU_CYCLES * 2)", + "BriefDescription": "Fraction of FSU execute slots utilized", + "MetricGroup": "TopDownL3", + "MetricName": "fsu_pipe_utilization" + }, + { + "MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES", + "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss", + "MetricGroup": "TopDownL3", + "MetricName": "i_cache_miss" + }, + { + "MetricExpr": " STALL_FRONTEND_TLB / CPU_CYCLES ", + "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss", + "MetricGroup": "TopDownL3", + "MetricName": "i_tlb_miss" + }, + { + "MetricExpr": "IXU_NUM_UOPS_ISSUED / (CPU_CYCLES / 4)", + "BriefDescription": "Fraction of IXU execute slots utilized", + "MetricGroup": "TopDownL3", + "MetricName": "ixu_pipe_utilization" + }, + { + "MetricExpr": "IDR_STALL_FLUSH / CPU_CYCLES", + "BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery", + "MetricGroup": "TopDownL3", + "MetricName": "recovery" + }, + { + "MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES", + "BriefDescription": "Fraction of cycles the CPU was stalled due to core resource shortage", + "MetricGroup": "TopDownL3", + "MetricName": "resource" + }, + { + "MetricExpr": "IDR_STALL_FSU_SCHED / CPU_CYCLES ", + "BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full", + "MetricGroup": "TopDownL4", + "MetricName": "stall_fsu_sched" + }, + { + "MetricExpr": "IDR_STALL_IXU_SCHED / CPU_CYCLES ", + "BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full", + "MetricGroup": "TopDownL4", + "MetricName": "stall_ixu_sched" + }, + { + "MetricExpr": "IDR_STALL_LOB_ID / CPU_CYCLES ", + "BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full", + "MetricGroup": "TopDownL4", + "MetricName": "stall_lob_id" + }, + { + "MetricExpr": "IDR_STALL_ROB_ID / CPU_CYCLES", + "BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full", + "MetricGroup": "TopDownL4", + "MetricName": "stall_rob_id" + }, + { + "MetricExpr": "IDR_STALL_SOB_ID / CPU_CYCLES ", + "BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full", + "MetricGroup": "TopDownL4", + "MetricName": "stall_sob_id" + } +] From patchwork Thu Aug 3 21:13:31 2023 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some of the events included in the ampereone/core-imp-def are not supported on AmpereOne, remove them. Signed-off-by: Ilkka Koskinen --- .../arm64/ampere/ampereone/core-imp-def.json | 120 ------------------ 1 file changed, 120 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json index 95c30243f2b2..88b23b85e33c 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json @@ -533,66 +533,6 @@ "EventName": "MMU_D_OTB_ALLOC", "BriefDescription": "L2D OTB allocate" }, - { - "PublicDescription": "DTLB Translation cache hit on S1L2 walk cache entry", - "EventCode": "0xD801", - "EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK", - "BriefDescription": "DTLB Translation cache hit on S1L2 walk cache entry" - }, - { - "PublicDescription": "DTLB Translation cache hit on S1L1 walk cache entry", - "EventCode": "0xD802", - "EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK", - "BriefDescription": "DTLB Translation cache hit on S1L1 walk cache entry" - }, - { - "PublicDescription": "DTLB Translation cache hit on S1L0 walk cache entry", - "EventCode": "0xD803", - "EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK", - "BriefDescription": "DTLB Translation cache hit on S1L0 walk cache entry" - }, - { - "PublicDescription": "DTLB Translation cache hit on S2L2 walk cache entry", - "EventCode": "0xD804", - "EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK", - "BriefDescription": "DTLB Translation cache hit on S2L2 walk cache entry" - }, - { - "PublicDescription": "DTLB Translation cache hit on S2L1 walk cache entry", - "EventCode": "0xD805", - "EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK", - "BriefDescription": "DTLB Translation cache hit on S2L1 walk cache entry" - }, - { - "PublicDescription": "DTLB Translation cache hit on S2L0 walk cache entry", - "EventCode": "0xD806", - "EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK", - "BriefDescription": "DTLB Translation cache hit on S2L0 walk cache entry" - }, - { - "PublicDescription": "D-side S1 Page walk cache lookup", - "EventCode": "0xD807", - "EventName": "MMU_D_S1_WALK_CACHE_LOOKUP", - "BriefDescription": "D-side S1 Page walk cache lookup" - }, - { - "PublicDescription": "D-side S1 Page walk cache refill", - "EventCode": "0xD808", - "EventName": "MMU_D_S1_WALK_CACHE_REFILL", - "BriefDescription": "D-side S1 Page walk cache refill" - }, - { - "PublicDescription": "D-side S2 Page walk cache lookup", - "EventCode": "0xD809", - "EventName": "MMU_D_S2_WALK_CACHE_LOOKUP", - "BriefDescription": "D-side S2 Page walk cache lookup" - }, - { - "PublicDescription": "D-side S2 Page walk cache refill", - "EventCode": "0xD80A", - "EventName": "MMU_D_S2_WALK_CACHE_REFILL", - "BriefDescription": "D-side S2 Page walk cache refill" - }, { "PublicDescription": "D-side Stage1 tablewalk fault", "EventCode": "0xD80B", @@ -617,66 +557,6 @@ "EventName": "MMU_I_OTB_ALLOC", "BriefDescription": "L2I OTB allocate" }, - { - "PublicDescription": "ITLB Translation cache hit on S1L2 walk cache entry", - "EventCode": "0xD901", - "EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK", - "BriefDescription": "ITLB Translation cache hit on S1L2 walk cache entry" - }, - { - "PublicDescription": "ITLB Translation cache hit on S1L1 walk cache entry", - "EventCode": "0xD902", - "EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK", - "BriefDescription": "ITLB Translation cache hit on S1L1 walk cache entry" - }, - { - "PublicDescription": "ITLB Translation cache hit on S1L0 walk cache entry", - "EventCode": "0xD903", - "EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK", - "BriefDescription": "ITLB Translation cache hit on S1L0 walk cache entry" - }, - { - "PublicDescription": "ITLB Translation cache hit on S2L2 walk cache entry", - "EventCode": "0xD904", - "EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK", - "BriefDescription": "ITLB Translation cache hit on S2L2 walk cache entry" - }, - { - "PublicDescription": "ITLB Translation cache hit on S2L1 walk cache entry", - "EventCode": "0xD905", - "EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK", - "BriefDescription": "ITLB Translation cache hit on S2L1 walk cache entry" - }, - { - "PublicDescription": "ITLB Translation cache hit on S2L0 walk cache entry", - "EventCode": "0xD906", - "EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK", - "BriefDescription": "ITLB Translation cache hit on S2L0 walk cache entry" - }, - { - "PublicDescription": "I-side S1 Page walk cache lookup", - "EventCode": "0xD907", - "EventName": "MMU_I_S1_WALK_CACHE_LOOKUP", - "BriefDescription": "I-side S1 Page walk cache lookup" - }, - { - "PublicDescription": "I-side S1 Page walk cache refill", - "EventCode": "0xD908", - "EventName": "MMU_I_S1_WALK_CACHE_REFILL", - "BriefDescription": "I-side S1 Page walk cache refill" - }, - { - "PublicDescription": "I-side S2 Page walk cache lookup", - "EventCode": "0xD909", - "EventName": "MMU_I_S2_WALK_CACHE_LOOKUP", - "BriefDescription": "I-side S2 Page walk cache lookup" - }, - { - "PublicDescription": "I-side S2 Page walk cache refill", - "EventCode": "0xD90A", - "EventName": "MMU_I_S2_WALK_CACHE_REFILL", - "BriefDescription": "I-side S2 Page walk cache refill" - }, { "PublicDescription": "I-side Stage1 tablewalk fault", "EventCode": "0xD90B",