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Message-ID: Date: Mon, 7 Aug 2023 17:20:11 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: [PATCH 1/4] x86emul: support AVX-VNNI-INT16 Content-Language: en-US From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= References: <96f70f2f-8712-9f93-34e3-f56deae364a8@suse.com> In-Reply-To: <96f70f2f-8712-9f93-34e3-f56deae364a8@suse.com> X-ClientProxiedBy: FR2P281CA0069.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:9a::10) To DU2PR04MB8790.eurprd04.prod.outlook.com (2603:10a6:10:2e1::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8790:EE_|PA4PR04MB8014:EE_ X-MS-Office365-Filtering-Correlation-Id: 723d360b-97c5-4a33-54a2-08db9759cbeb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bOE5R/VJNuZWazyd+j6sn0HG6R4WeOlm3Lh5LuGo1FLSaKgU+1l66I40dXVSlznKbdw4/+SCRvjuwpKlFLBQfCcTqeaSfyDzZ8kHbiurYn0dNzNpV8Yd0MN9e48YT6x6pUfI4KtOkmQeUbFvuMpuGqaFPsj8CNKxwiaVQIqCJjB3RDyFqmw/5keVt4ZCXajeiCz1esl/Ob3T3gPnEd6JLHdLXveDgUa5hXGdwjglVs1DCtZiJRla4hLHGUekAXJZLAFjwttYloZqhQ9AhwTX8wG3o66g6FR4TTrMKgyjPEjZyppgIkRaBNs9T1I8Q9M0fztQR/izl2faIgrpgvvYzKPJF/zgppxvCytqDBwUFXOPucz4/3qZwBWtzigAR1nmVXAHHcobJB79LrEwmpF1Ylekr0lJ/o2hq6AKIRmrUF5LoRpc4dwuA7nX1p8hUdynzPTak4POxjbbKkpTgUI7OOBSIeEEmzEI6VyEEYCfWJTUsD4l/DLP+wtUiDm9+oXUDgeVvPL/FSw0m39wi6gxwTY7wKCmvDJYvA0G0X0vrvY3TLQJHrDJoKOHTEMBozQbH2kmrDlWtSJuT6CZCVas6amSpZ9pzCuLSPP5YG09vnQvCq02mYJVJVVrZAuQBxdSUxwG5xrI5x0Kt8SoeqKqyA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU2PR04MB8790.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(396003)(376002)(136003)(39860400002)(366004)(346002)(451199021)(186006)(1800799003)(86362001)(31696002)(41300700001)(478600001)(6506007)(8936002)(8676002)(26005)(38100700002)(6486002)(2616005)(5660300002)(36756003)(2906002)(83380400001)(54906003)(31686004)(316002)(66476007)(66556008)(66946007)(6916009)(4326008)(6512007)(45980500001)(43740500002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?imCQ5RN0Fx7U15miOF1Z8TXQmP34?= =?utf-8?q?LrZc8VPruvxTBorWJbTACejg7BZY/bQcDiqL+vqlW9r9+ejUy7ehKMdcEQaSTdyBA?= =?utf-8?q?Ookm/PuOf+8oLnFTthqIWUSJGAiKOVibPg9veRVAKAhKJT9VUeLTDejXqozNFVZEI?= =?utf-8?q?CtKr4ofqvru2z6hPO2sc7aY5p1Kfutn/WlzWtn7uAA8IKKSP4HYXmz6uHgF5yh/+O?= =?utf-8?q?xy0VWj18zePbWyn75F0Jg3ozKA+krZULWLCidEQ+8dDk6Kj4RTpdDMBze095QMVMD?= =?utf-8?q?39/IFJ/wBEfpIoEO8v4jLJa5d8s6z/KbUADlrxnkq2VnvJDcztOD6RJHITbz1oS7O?= =?utf-8?q?ei6wS3HweSnw1EkfcgviQyykLUXXC91eN1X6nRmrbr3hzCa5gvrfykD/i2M9vUsvB?= =?utf-8?q?r38SUELiInFFNElSD9zwBng+tU19YDzQpKiEZK6SDQIT4i8wooTTXFR6RfwOuo6JT?= =?utf-8?q?mHuSa8aUG3RDGY5DLzW0m3qglQXiv5omrhZFzh6lU+oMJ4lOvrfH9Xl0z007ZDiO6?= =?utf-8?q?v9Wd4dQJUHKy8dmJZ506mCiyAd5Dgxw423wLlrfvWZYTqC2jO+Xa2uUBBUhx5gZIR?= =?utf-8?q?uzOJXXussHXziMcvj+CVgSnLsyrHPcOefTNCKX00qGDhAhpi2TnzzFufjSNVybZ5n?= =?utf-8?q?RnxXtbGCzU8zQ4U457wAbnDPMwmXg4HwpyVxelqDBpFjpgUhcUaEdGm4ME4KRhfuB?= =?utf-8?q?q4N3UC4zz4VLcw7/BD1O1beta5W028kyl3Gd2kV+9CrRNfIsLIJuY/Xzq3vjqOe9d?= =?utf-8?q?daoN3Lnk/0ITWGd/mEB5YZX4WPgJJ7I2yYO6sFMNh4cMiD3knmetISchFEbNuPd7S?= =?utf-8?q?DNu+Sg8y9qxFPF+lRgSg9E57MFdUD7UaFiJpGgx3v40z6AkF5xVXJzOG1nN5ySn9I?= =?utf-8?q?McKwcFXXJSfJ44TB+nbnhNUxa1NLoeOkl5dEszW980OMSGUupf11y078joxKL4/XS?= =?utf-8?q?uGAr3Qtsmfw7Am09hsyY5DahHPo5JmIP5WqeJuFIMsvqZr7zVDUvJtUIdGDHuAqVq?= =?utf-8?q?/nUxntJ3tXSwXNZaqUlGAguI5YItkisVl87VmwsDF9aqU9bUIyK36zM685cgbsBIf?= =?utf-8?q?mU39aWDIs8eu8CQkY8tzaOHx6fL4WA66BMefZzAhGM2uy6Z0HrM780kAsu+DWqU+K?= =?utf-8?q?B7P4fBd7OXvDFtcuQlWxMhr6Lu/GARDorMTjl/P8eDz1uhESQEUCG6ftrJl9dMS97?= =?utf-8?q?CzD1lfvPlb+TFFrwxkxcf5xYBZPIAnWF1m8L979RTARmGqwGpRRMXZgIkEK96fWqG?= =?utf-8?q?bAlRIG7cMV8hATqd+hsIlB19vwLXoJpzomt2QZYtY/KTc4RB9/AVGYpFEjvALYMkq?= =?utf-8?q?ku+jIy7LYCQpdJoI0qPR9P3StTcCBPo2lKVZbWgd+z5fe3mWx3lwrveOCPHsGz8in?= =?utf-8?q?X158tuaFll8wwjMcvIE1OO0Fv7W8hESgtyydciZZeSsYrogMHm4w1GoSV3oFlLK9f?= =?utf-8?q?2nOxM4mHXANZjfEKBbdKJ6egC9aZuXYy2r5Kz6Og7pgQalSDTMg6/DQZ63eeJxm3I?= =?utf-8?q?hg86ide34ya0?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 723d360b-97c5-4a33-54a2-08db9759cbeb X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8790.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2023 15:20:13.3647 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Wh4BoECcbDA9mF4aSPXGL+oKUYqP/eeEv4cAGIBdpGIhc0AD+MemHwXmC18ZwKN6R4Bw1z1dykNigylhtxpPvQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR04MB8014 These are close relatives of the AVX-VNNI and AVX-VNNI-INT8 ISA extensions. Since the insns here and in particular their memory access patterns follow the usual scheme (and especially the word variants of AVX-VNNI), I didn't think it was necessary to add a contrived test specifically for them. Signed-off-by: Jan Beulich --- I'm actually pondering whether to contrive dot_product() for these and the other AVX-VNNI* insns, by additionally performing a horizontal add on the result vectors. Main thing I dislike about it is that everything else in simd_test() would then be re-run for no real purpose. Yet making a new standalone simd-dotp.c also doesn't look very attractive. --- SDE: -arl, -lnl, or -future --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -217,6 +217,8 @@ static const char *const str_7d1[32] = { [ 4] = "avx-vnni-int8", [ 5] = "avx-ne-convert", + [10] = "avx-vnni-int16", + [18] = "cet-sss", }; --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1397,6 +1397,12 @@ static const struct vex { { { 0xbe }, 2, T, R, pfx_66, Wn, Ln }, /* vnmsub231p{s,d} */ { { 0xbf }, 2, T, R, pfx_66, Wn, LIG }, /* vnmsub231s{s,d} */ { { 0xcf }, 2, T, R, pfx_66, W0, Ln }, /* vgf2p8mulb */ + { { 0xd2 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuud */ + { { 0xd2 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusd */ + { { 0xd2 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsud */ + { { 0xd3 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuuds */ + { { 0xd3 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusds */ + { { 0xd3 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsuds */ { { 0xdb }, 2, T, R, pfx_66, WIG, L0 }, /* vaesimc */ { { 0xdc }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenc */ { { 0xdd }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenclast */ --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -183,6 +183,7 @@ void wrpkru(unsigned int val); #define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6)) #define cpu_has_avx_vnni_int8 (cp.feat.avx_vnni_int8 && xcr0_mask(6)) #define cpu_has_avx_ne_convert (cp.feat.avx_ne_convert && xcr0_mask(6)) +#define cpu_has_avx_vnni_int16 (cp.feat.avx_vnni_int16 && xcr0_mask(6)) #define cpu_has_xgetbv1 (cpu_has_xsave && cp.xstate.xgetbv1) --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -183,6 +183,7 @@ static inline bool boot_cpu_has(unsigned /* CPUID level 0x00000007:1.edx */ #define cpu_has_avx_vnni_int8 boot_cpu_has(X86_FEATURE_AVX_VNNI_INT8) #define cpu_has_avx_ne_convert boot_cpu_has(X86_FEATURE_AVX_NE_CONVERT) +#define cpu_has_avx_vnni_int16 boot_cpu_has(X86_FEATURE_AVX_VNNI_INT16) /* MSR_ARCH_CAPS */ #define cpu_has_rdcl_no boot_cpu_has(X86_FEATURE_RDCL_NO) --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -435,6 +435,8 @@ static const struct ext0f38_table { [0xcc] = { .simd_size = simd_packed_fp, .two_op = 1, .d8s = d8s_vl }, [0xcd] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq }, [0xcf] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, + [0xd2] = { .simd_size = simd_other }, + [0xd3] = { .simd_size = simd_other }, [0xd6] = { .simd_size = simd_other, .d8s = d8s_vl }, [0xd7] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq }, [0xdb] = { .simd_size = simd_packed_int, .two_op = 1 }, --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -593,6 +593,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert) +#define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16) #define vcpu_must_have(feat) \ generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6871,6 +6871,17 @@ x86_emulate( elem_bytes = 1; goto avx512f_no_sae; + case X86EMUL_OPC_VEX (0x0f38, 0xd2): /* vpdpwuud [xy]mm/mem,[xy]mm,[xy]mm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xd2): /* vpdpwusd [xy]mm/mem,[xy]mm,[xy]mm */ + case X86EMUL_OPC_VEX_F3(0x0f38, 0xd2): /* vpdpwsud [xy]mm/mem,[xy]mm,[xy]mm */ + case X86EMUL_OPC_VEX (0x0f38, 0xd3): /* vpdpwuuds [xy]mm/mem,[xy]mm,[xy]mm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xd3): /* vpdpwusds [xy]mm/mem,[xy]mm,[xy]mm */ + case X86EMUL_OPC_VEX_F3(0x0f38, 0xd3): /* vpdpwsuds [xy]mm/mem,[xy]mm,[xy]mm */ + host_and_vcpu_must_have(avx_vnni_int16); + generate_exception_if(vex.w, X86_EXC_UD); + op_bytes = 16 << vex.l; + goto simd_0f_ymm; + case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */ --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -306,6 +306,7 @@ XEN_CPUFEATURE(MCDT_NO, 13*32 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */ XEN_CPUFEATURE(AVX_VNNI_INT8, 15*32+ 4) /*A AVX-VNNI-INT8 Instructions */ XEN_CPUFEATURE(AVX_NE_CONVERT, 15*32+ 5) /*A AVX-NE-CONVERT Instructions */ +XEN_CPUFEATURE(AVX_VNNI_INT16, 15*32+10) /*A AVX-VNNI-INT16 Instructions */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow Stacks safe to use */ /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -284,7 +284,8 @@ def crunch_numbers(state): # feature flags. If want to use AVX512, AVX2 must be supported and # enabled. Certain later extensions, acting on 256-bit vectors of # integers, better depend on AVX2 than AVX. - AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA, AVX_VNNI_INT8], + AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA, AVX_VNNI_INT8, + AVX_VNNI_INT16], # AVX512F is taken to mean hardware support for 512bit registers # (which in practice depends on the EVEX prefix to encode) as well From patchwork Mon Aug 7 15:20:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 13344425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12FE1C001DB for ; Mon, 7 Aug 2023 15:20:49 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.578628.906226 (Exim 4.92) (envelope-from ) id 1qT229-0002wy-4H; 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Signed-off-by: Jan Beulich --- The need to set op_bytes here is a little odd; I'm inclined to move the generate_exception_if(!op_bytes, X86_EXC_UD) at the top of SIMD handling (near the bottom of x86_emulate()) into the "ea.type == OP_MEM" conditional, as it's relevant (used) only there. --- SDE: -arl, -lnl, or -future --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -185,6 +185,8 @@ static const char *const str_7d0[32] = static const char *const str_7a1[32] = { + [ 0] = "sha512", + [ 4] = "avx-vnni", [ 5] = "avx512-bf16", [10] = "fzrm", [11] = "fsrs", --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1396,6 +1396,9 @@ static const struct vex { { { 0xbd }, 2, T, R, pfx_66, Wn, LIG }, /* vnmadd231s{s,d} */ { { 0xbe }, 2, T, R, pfx_66, Wn, Ln }, /* vnmsub231p{s,d} */ { { 0xbf }, 2, T, R, pfx_66, Wn, LIG }, /* vnmsub231s{s,d} */ + { { 0xcb, 0xc0 }, 2, F, N, pfx_f2, W0, L1 }, /* vsha512rnds2 */ + { { 0xcc, 0xc0 }, 2, F, N, pfx_f2, W0, L1 }, /* vsha512msg1 */ + { { 0xcd, 0xc0 }, 2, F, N, pfx_f2, W0, L1 }, /* vsha512msg2 */ { { 0xcf }, 2, T, R, pfx_66, W0, Ln }, /* vgf2p8mulb */ { { 0xd2 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuud */ { { 0xd2 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusd */ --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -178,6 +178,7 @@ void wrpkru(unsigned int val); #define cpu_has_avx512_vp2intersect (cp.feat.avx512_vp2intersect && xcr0_mask(0xe6)) #define cpu_has_serialize cp.feat.serialize #define cpu_has_avx512_fp16 (cp.feat.avx512_fp16 && xcr0_mask(0xe6)) +#define cpu_has_sha512 (cp.feat.sha512 && xcr0_mask(6)) #define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6)) #define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6)) #define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6)) --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -176,6 +176,7 @@ static inline bool boot_cpu_has(unsigned #define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS) /* CPUID level 0x00000007:1.eax */ +#define cpu_has_sha512 boot_cpu_has(X86_FEATURE_SHA512) #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) #define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16) #define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA) --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -916,6 +916,14 @@ decode_0f38(struct x86_emulate_state *s, case X86EMUL_OPC_EVEX_66(0, 0x7c): /* vpbroadcast{d,q} */ break; + case X86EMUL_OPC_VEX_F2(0, 0xcc): /* vsha512msg1 */ + case X86EMUL_OPC_VEX_F2(0, 0xcd): /* vsha512msg2 */ + s->desc |= TwoOp; + /* fallthrough */ + case X86EMUL_OPC_VEX_F2(0, 0xcb): /* vsha512rnds2 */ + s->simd_size = simd_other; + break; + case 0xf0: /* movbe / crc32 */ s->desc |= s->vex.pfx == vex_f2 ? ByteOp : Mov; if ( s->vex.pfx >= vex_f3 ) --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -587,6 +587,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_serialize() (ctxt->cpuid->feat.serialize) #define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk) #define vcpu_has_avx512_fp16() (ctxt->cpuid->feat.avx512_fp16) +#define vcpu_has_sha512() (ctxt->cpuid->feat.sha512) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6856,6 +6856,14 @@ x86_emulate( host_and_vcpu_must_have(avx512er); goto simd_zmm_scalar_sae; + case X86EMUL_OPC_VEX_F2(0x0f38, 0xcb): /* vsha512rnds2 xmm,ymm,ymm */ + case X86EMUL_OPC_VEX_F2(0x0f38, 0xcc): /* vsha512msg1 xmm,ymm */ + case X86EMUL_OPC_VEX_F2(0x0f38, 0xcd): /* vsha512msg2 ymm,ymm */ + host_and_vcpu_must_have(sha512); + generate_exception_if(ea.type != OP_REG || vex.w || !vex.l, X86_EXC_UD); + op_bytes = 32; + goto simd_0f_ymm; + case X86EMUL_OPC_66(0x0f38, 0xcf): /* gf2p8mulb xmm/m128,xmm */ host_and_vcpu_must_have(gfni); goto simd_0f38_common; --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -276,6 +276,7 @@ XEN_CPUFEATURE(CORE_CAPS, 9*32+30) / XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */ /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ +XEN_CPUFEATURE(SHA512, 10*32+ 0) /*A SHA512 Instructions */ XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */ XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -285,7 +285,7 @@ def crunch_numbers(state): # enabled. Certain later extensions, acting on 256-bit vectors of # integers, better depend on AVX2 than AVX. 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Signed-off-by: Jan Beulich --- SDE: -arl, -lnl, or -future --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -185,7 +185,7 @@ static const char *const str_7d0[32] = static const char *const str_7a1[32] = { - [ 0] = "sha512", + [ 0] = "sha512", [ 1] = "sm3", [ 4] = "avx-vnni", [ 5] = "avx512-bf16", --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1406,6 +1406,8 @@ static const struct vex { { { 0xd3 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuuds */ { { 0xd3 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusds */ { { 0xd3 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsuds */ + { { 0xda }, 2, T, R, pfx_no, W0, L0 }, /* vsm3msg1 */ + { { 0xda }, 2, T, R, pfx_66, W0, L0 }, /* vsm3msg2 */ { { 0xdb }, 2, T, R, pfx_66, WIG, L0 }, /* vaesimc */ { { 0xdc }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenc */ { { 0xdd }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenclast */ @@ -1490,6 +1492,7 @@ static const struct vex { { { 0x7f }, 3, T, R, pfx_66, Wn, LIG }, /* vfnmsubsd */ { { 0xce }, 3, T, R, pfx_66, W1, Ln }, /* vgf2p8affineqb */ { { 0xcf }, 3, T, R, pfx_66, W1, Ln }, /* vgf2p8affineinvqb */ + { { 0xde }, 3, T, R, pfx_66, W0, L0 }, /* vsm3rnds2 */ { { 0xdf }, 3, T, R, pfx_66, WIG, Ln }, /* vaeskeygenassist */ { { 0xf0 }, 3, T, R, pfx_f2, Wn, L0 }, /* rorx */ }; --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -179,6 +179,7 @@ void wrpkru(unsigned int val); #define cpu_has_serialize cp.feat.serialize #define cpu_has_avx512_fp16 (cp.feat.avx512_fp16 && xcr0_mask(0xe6)) #define cpu_has_sha512 (cp.feat.sha512 && xcr0_mask(6)) +#define cpu_has_sm3 (cp.feat.sm3 && xcr0_mask(6)) #define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6)) #define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6)) #define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6)) --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -177,6 +177,7 @@ static inline bool boot_cpu_has(unsigned /* CPUID level 0x00000007:1.eax */ #define cpu_has_sha512 boot_cpu_has(X86_FEATURE_SHA512) +#define cpu_has_sm3 boot_cpu_has(X86_FEATURE_SM3) #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) #define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16) #define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA) --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -439,6 +439,7 @@ static const struct ext0f38_table { [0xd3] = { .simd_size = simd_other }, [0xd6] = { .simd_size = simd_other, .d8s = d8s_vl }, [0xd7] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq }, + [0xda] = { .simd_size = simd_other }, [0xdb] = { .simd_size = simd_packed_int, .two_op = 1 }, [0xdc ... 0xdf] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, [0xf0] = { .two_op = 1 }, @@ -519,6 +520,7 @@ static const struct ext0f3a_table { [0xc2] = { .simd_size = simd_any_fp, .d8s = d8s_vl }, [0xcc] = { .simd_size = simd_other }, [0xce ... 0xcf] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, + [0xde] = { .simd_size = simd_other }, [0xdf] = { .simd_size = simd_packed_int, .two_op = 1 }, [0xf0] = {}, }; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -588,6 +588,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk) #define vcpu_has_avx512_fp16() (ctxt->cpuid->feat.avx512_fp16) #define vcpu_has_sha512() (ctxt->cpuid->feat.sha512) +#define vcpu_has_sm3() (ctxt->cpuid->feat.sm3) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6890,6 +6890,12 @@ x86_emulate( op_bytes = 16 << vex.l; goto simd_0f_ymm; + case X86EMUL_OPC_VEX (0x0f38, 0xda): /* vsm3msg1 xmm/mem,xmm,xmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0xda): /* vsm3msg2 xmm/mem,xmm,xmm */ + generate_exception_if(vex.w || vex.l, X86_EXC_UD); + host_and_vcpu_must_have(sm3); + goto simd_0f_ymm; + case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */ @@ -7762,6 +7768,12 @@ x86_emulate( fault_suppression = false; goto avx512f_imm8_no_sae; + case X86EMUL_OPC_VEX_66(0x0f3a, 0xde): /* vsm3rnds2 $imm8,xmm/mem,xmm,xmm */ + host_and_vcpu_must_have(sm3); + generate_exception_if(vex.w || vex.l, X86_EXC_UD); + op_bytes = 16; + goto simd_0f_imm8_ymm; + case X86EMUL_OPC_66(0x0f3a, 0xdf): /* aeskeygenassist $imm8,xmm/m128,xmm */ case X86EMUL_OPC_VEX_66(0x0f3a, 0xdf): /* vaeskeygenassist $imm8,xmm/m128,xmm */ host_and_vcpu_must_have(aesni); --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -277,6 +277,7 @@ XEN_CPUFEATURE(SSBD, 9*32+31) / /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ XEN_CPUFEATURE(SHA512, 10*32+ 0) /*A SHA512 Instructions */ +XEN_CPUFEATURE(SM3, 10*32+ 1) /*A SM3 Instructions */ XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */ XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -262,7 +262,7 @@ def crunch_numbers(state): # for the XOP prefix). VEX/XOP-encoded GPR instructions, such as # those from the BMI{1,2}, TBM and LWP sets function fine in the # absence of any enabled xstate. - AVX: [FMA, FMA4, F16C, AVX2, XOP, AVX_NE_CONVERT], + AVX: [FMA, FMA4, F16C, AVX2, XOP, AVX_NE_CONVERT, SM3], # This dependency exists solely for the shadow pagetable code. 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Signed-off-by: Jan Beulich --- SDE: -arl, -lnl, or -future --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -186,7 +186,7 @@ static const char *const str_7d0[32] = static const char *const str_7a1[32] = { [ 0] = "sha512", [ 1] = "sm3", - + [ 2] = "sm4", [ 4] = "avx-vnni", [ 5] = "avx512-bf16", [10] = "fzrm", [11] = "fsrs", --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1408,6 +1408,8 @@ static const struct vex { { { 0xd3 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsuds */ { { 0xda }, 2, T, R, pfx_no, W0, L0 }, /* vsm3msg1 */ { { 0xda }, 2, T, R, pfx_66, W0, L0 }, /* vsm3msg2 */ + { { 0xda }, 2, T, R, pfx_f3, W0, Ln }, /* vsm4key4 */ + { { 0xda }, 2, T, R, pfx_f2, W0, Ln }, /* vsm4rnds4 */ { { 0xdb }, 2, T, R, pfx_66, WIG, L0 }, /* vaesimc */ { { 0xdc }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenc */ { { 0xdd }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenclast */ --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -180,6 +180,7 @@ void wrpkru(unsigned int val); #define cpu_has_avx512_fp16 (cp.feat.avx512_fp16 && xcr0_mask(0xe6)) #define cpu_has_sha512 (cp.feat.sha512 && xcr0_mask(6)) #define cpu_has_sm3 (cp.feat.sm3 && xcr0_mask(6)) +#define cpu_has_sm4 (cp.feat.sm4 && xcr0_mask(6)) #define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6)) #define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6)) #define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6)) --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -178,6 +178,7 @@ static inline bool boot_cpu_has(unsigned /* CPUID level 0x00000007:1.eax */ #define cpu_has_sha512 boot_cpu_has(X86_FEATURE_SHA512) #define cpu_has_sm3 boot_cpu_has(X86_FEATURE_SM3) +#define cpu_has_sm4 boot_cpu_has(X86_FEATURE_SM4) #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) #define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16) #define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA) --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -589,6 +589,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx512_fp16() (ctxt->cpuid->feat.avx512_fp16) #define vcpu_has_sha512() (ctxt->cpuid->feat.sha512) #define vcpu_has_sm3() (ctxt->cpuid->feat.sm3) +#define vcpu_has_sm4() (ctxt->cpuid->feat.sm4) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6896,6 +6896,13 @@ x86_emulate( host_and_vcpu_must_have(sm3); goto simd_0f_ymm; + case X86EMUL_OPC_VEX_F3(0x0f38, 0xda): /* vsm4key4 [xy]mm/mem,[xy]mm,[xy]mm */ + case X86EMUL_OPC_VEX_F2(0x0f38, 0xda): /* vsm4rnds4 [xy]mm/mem,[xy]mm,[xy]mm */ + host_and_vcpu_must_have(sm4); + generate_exception_if(vex.w, X86_EXC_UD); + op_bytes = 16 << vex.l; + goto simd_0f_ymm; + case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */ --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -278,6 +278,7 @@ XEN_CPUFEATURE(SSBD, 9*32+31) / /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ XEN_CPUFEATURE(SHA512, 10*32+ 0) /*A SHA512 Instructions */ XEN_CPUFEATURE(SM3, 10*32+ 1) /*A SM3 Instructions */ +XEN_CPUFEATURE(SM4, 10*32+ 2) /*A SM4 Instructions */ XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */ XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -285,7 +285,7 @@ def crunch_numbers(state): # enabled. Certain later extensions, acting on 256-bit vectors of # integers, better depend on AVX2 than AVX. AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA, AVX_VNNI_INT8, - AVX_VNNI_INT16, SHA512], + AVX_VNNI_INT16, SHA512, SM4], # AVX512F is taken to mean hardware support for 512bit registers # (which in practice depends on the EVEX prefix to encode) as well