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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH] xen/arm64: head: Introduce a helper to flush local TLBs Date: Tue, 8 Aug 2023 13:07:39 +0200 Message-ID: <20230808110739.1296-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|PH7PR12MB7283:EE_ X-MS-Office365-Filtering-Correlation-Id: f24e20f8-192f-417c-2192-08db97ffc18e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: B0P1CZDQni3sh3uR2xhjue+eNo6UdVIkRFgQ6Zsm91UczCyfNdKpQ+hFml8r/sNo027WSXHu42Q7Krmu2tlhL9vdsRfNcUfVvCfLzoIMHJL5EJCCOnTlJJMOU5x3VR2VK31geNTCIEmkIK+Kf4pHMtvNpCrLXGBgBlDuuF0tbZWFpBiR2doofbrmirhr/MPkZz+F8VSQt2wA3+9bgsDKI+mjkNHsBsMfzNcf2ZfbXgQDB7lPNdiuRYvmVtxNveOZzsgEr4nDRmyDBJJgqSC/SicQ3A35nVMSwB1HDgivR2KnZLci1saLrHLY+Zqpy7f2N7ge/EnnbCnsY/hGJwNOq+cjEDjxKZ2iS6B3FizidoncFg8+IezIFvcUlftl3nTa+tjQ05wldiCF+d8cJQoI4UOJNg1nHT0gdMqiRjf/o4W4VxlHqKhkjfvOKTPQ859it2RASznbB87na7o8/aLYlLi6ANoOu4D3E1LukDJ3mxricY4Om86BSblifmOlYj5VfthNTaic/04kmAP99QWcoK+c8v8e+SBCH+BjjRP+Jskxbs4LMP0jrmGOAKlJAkaSvdagoGmAt/kF7KLCNr1ntC4xlV0YfuTJ967ZWob5m1SMG1HdLBOmz1NHG0qc8OFw34YbrWciO6BvE7y1J6TwG4RNEF8sfDoN5SUK5sfRfmb7xVtGniroTbszOOu8LP9iA6kua7rq2kd+El3ST9dGsp0AK4onmfpJQxI+EvrJV6zvVbAuhXMT1eQS2HjarHpMLbghQ4Mro84Ew54Pj9oTKg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(39860400002)(376002)(136003)(451199021)(186006)(82310400008)(1800799003)(46966006)(36840700001)(40470700004)(40480700001)(2616005)(40460700003)(6666004)(356005)(82740400003)(478600001)(86362001)(81166007)(26005)(36756003)(1076003)(41300700001)(5660300002)(8936002)(316002)(44832011)(8676002)(54906003)(2906002)(6916009)(4326008)(70586007)(70206006)(336012)(83380400001)(36860700001)(47076005)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 11:08:12.1735 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f24e20f8-192f-417c-2192-08db97ffc18e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7283 Instead of repeating the same sequence of instructions to flush the TLBs in various places, introduce a macro flush_xen_tlb_local and make use of it. This is similar to what was done for arm32 by the commit: dea9dddeceec8a1d68da24b14d5b2396effe555f This is also making the flush sequence in enable_mmu more clear and consistent. Signed-off-by: Michal Orzel Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini Reviewed-by: Julien Grall --- xen/arch/arm/arm64/head.S | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 31cdb54d74e5..8bca9afa27b2 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -136,6 +136,18 @@ add \xb, \xb, x20 .endm +/* + * Flush local TLBs + * + * See asm/arm64/flushtlb.h for the explanation of the sequence. + */ +.macro flush_xen_tlb_local + dsb nshst + tlbi alle2 + dsb nsh + isb +.endm + .section .text.header, "ax", %progbits /*.aarch64*/ @@ -721,8 +733,7 @@ enable_mmu: * The state of the TLBs is unknown before turning on the MMU. * Flush them to avoid stale one. */ - tlbi alle2 /* Flush hypervisor TLBs */ - dsb nsh + flush_xen_tlb_local /* Write Xen's PT's paddr into TTBR0_EL2 */ msr TTBR0_EL2, x4 @@ -786,11 +797,7 @@ remove_identity_mapping: str xzr, [x0, x1, lsl #3] identity_mapping_removed: - /* See asm/arm64/flushtlb.h for the explanation of the sequence. */ - dsb nshst - tlbi alle2 - dsb nsh - isb + flush_xen_tlb_local ret ENDPROC(remove_identity_mapping) @@ -872,14 +879,8 @@ ENTRY(switch_ttbr_id) msr SCTLR_EL2, x1 isb - /* - * 3) Flush the TLBs. - * See asm/arm64/flushtlb.h for the explanation of the sequence. - */ - dsb nshst - tlbi alle2 - dsb nsh - isb + /* 3) Flush the TLBs */ + flush_xen_tlb_local /* 4) Update the TTBR */ msr TTBR0_EL2, x0