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[71.184.142.128]) by smtp.gmail.com with ESMTPSA id e8-20020a0ce3c8000000b00637615a1f33sm1179234qvl.20.2023.08.09.13.37.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 13:37:12 -0700 (PDT) From: Eric Chanudet To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Eric Chanudet , Caleb Connolly Subject: [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable rtc Date: Wed, 9 Aug 2023 16:32:33 -0400 Message-ID: <20230809203506.1833205-1-echanude@redhat.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SA8540P-ride is one of the Qualcomm platforms that does not have access to UEFI runtime services and on which the RTC registers are read-only, as described in: https://lore.kernel.org/all/20230202155448.6715-1-johan+linaro@kernel.org/ Reserve four bytes in one of the PMIC registers to hold the RTC offset the same way as it was done for sc8280xp-crd which has similar limitations: commit e67b45582c5e ("arm64: dts: qcom: sc8280xp-crd: enable rtc") On SA8540P-ride, the register bank SDAM6 of the first PMIC is not writable. Following recommendations provided during the review, use SDAM2 from the second PMIC at offset 0xa0 instead. Reviewed-by: Caleb Connolly Signed-off-by: Eric Chanudet --- Changes in v3: * Reserve rtc-offset@a0 in pmm8540c_sdam_2 instead of rtc-offset@ac in pmm8540a_sdam_7. * v2: https://lore.kernel.org/linux-arm-msm/20230718145105.3464105-1-echanude@redhat.com/ Changes in v2: * Default pmm8540a_sdam_7 status to "disabled" in sa8540p-pmics.dtsi. * v1: https://lore.kernel.org/linux-arm-msm/20230717182351.3389252-1-echanude@redhat.com/ arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi | 11 ++++++++++- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 15 +++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi index 1221be89b3de..a1fbb477fafe 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi @@ -14,7 +14,7 @@ pmm8540a: pmic@0 { #address-cells = <1>; #size-cells = <0>; - rtc@6000 { + pmm8540a_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; @@ -39,6 +39,15 @@ pmm8540c: pmic@4 { #address-cells = <1>; #size-cells = <0>; + pmm8540c_sdam_2: nvram@b110 { + compatible = "qcom,spmi-sdam"; + reg = <0xb110>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb110 0xb0>; + status = "disabled"; + }; + pmm8540c_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 5a26974dcf8f..b04f72ec097c 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -407,6 +407,21 @@ &pcie3a_phy { status = "okay"; }; +&pmm8540a_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; + + status = "okay"; +}; + +&pmm8540c_sdam_2 { + status = "okay"; + + rtc_offset: rtc-offset@a0 { + reg = <0xa0 0x4>; + }; +}; + &qup0 { status = "okay"; };